JP2009004780A - 緩衝層を有する半導体素子 - Google Patents
緩衝層を有する半導体素子 Download PDFInfo
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- JP2009004780A JP2009004780A JP2008159106A JP2008159106A JP2009004780A JP 2009004780 A JP2009004780 A JP 2009004780A JP 2008159106 A JP2008159106 A JP 2008159106A JP 2008159106 A JP2008159106 A JP 2008159106A JP 2009004780 A JP2009004780 A JP 2009004780A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 230000007423 decrease Effects 0.000 claims description 10
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000035515 penetration Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000000541 pulsatile effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Light Receiving Elements (AREA)
Abstract
【解決手段】第1ドーピングから第2ドーピングへの少なくとも1つの変換部、即ち少なくとも1つのpn接合を有し、第1ドーピングを有する第1主面(H1)側の第1区域(10)と、この第1区域に続き第2ドーピングの低濃度を有する第2区域(20)と、この第2区域に続く第2ドーピングの緩衝層、即ち第3区域(30)と、この第3区域に続き第2ドーピングの高濃度を有する第2主面(H2)側の第4区域(40)との層順番を有する半導体素子において、緩衝層(30)の第2ドーピングの濃度が第2区域に対するその第1境界面(G1)で第4区域に対するその第2境界面(G2)におけるよりも高いこと。本発明に従い緩衝層(30)はイオン注入法を用いて生成される。
【選択図】図3
Description
H2 ダイオードの第2主面
10 第1区域
20 第2区域
30 第3区域(緩衝層)
40 第4区域
C1 緩衝層の濃度
C2 緩衝層の濃度
G1 緩衝層の境界面
G2 緩衝層の境界面
Claims (7)
- 第1ドーピングから第2ドーピングへの少なくとも1つの変換部、即ち少なくとも1つのpn接合を有し、第1ドーピングを有する第1主面(H1)側の第1区域(10)と、この第1区域に続き第2ドーピングの低濃度を有する第2区域(20)と、この第2区域に続く第2ドーピングの緩衝層、即ち第3区域(30)と、この第3区域に続き第2ドーピングの高濃度を有する第2主面(H2)側の第4区域(40)との層順番を有する半導体素子において、
緩衝層(30)の第2ドーピングの濃度が第2区域(20)に対するその第1境界面(G1)で第4区域(40)に対するその第2境界面(G2)におけるよりも高いことを特徴とする半導体素子。 - 第1区域(10)がp型にドーピングされていて、第2区域(20)がn−型にドーピングされていて、第4区域(40)がn+型にドーピングされていて、緩衝層、即ち第3区域(30)が第2区域(20)の最大濃度よりも大きく且つ第4区域(40)の最大濃度よりも小さいn型ドーピングの濃度を有することを特徴とする、請求項1に記載の半導体素子。
- n−型にドーピングされた第2区域(20)が1013から1015までの最大濃度を有し、第3区域(30)即ち緩衝層が1017の最大濃度を有し、n+型にドーピングされた第4区域(40)が1020のオーダーの最大濃度を有することを特徴とする、請求項2に記載の半導体素子。
- 緩衝層(30)の濃度(C1、C2)がその第1境界面(G1)から第2境界面(G2)へと指数関数的に又は線形的に又は脈動的に減少することを特徴とする、請求項1に記載の半導体素子。
- 請求項1に記載の半導体素子を製造するための方法において、
緩衝層(30)がイオン注入法により生成されることを特徴とする方法。 - ドーピング原子の浸入深さが各々異なる複数の注入ステップにより緩衝層(30)の脈動的に減少する濃度(C2)が生成されることを特徴とする、請求項5に記載の方法。
- イオン注入が第1主面(H1)から行われることを特徴とする、請求項5に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102007028316.6 | 2007-06-20 | ||
DE102007028316A DE102007028316B3 (de) | 2007-06-20 | 2007-06-20 | Halbleiterbauelement mit Pufferschicht und Verfahren zu dessen Herstellung |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009004780A true JP2009004780A (ja) | 2009-01-08 |
JP5358129B2 JP5358129B2 (ja) | 2013-12-04 |
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Application Number | Title | Priority Date | Filing Date |
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JP2008159106A Expired - Fee Related JP5358129B2 (ja) | 2007-06-20 | 2008-06-18 | 緩衝層を有する半導体素子 |
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US (1) | US8415773B2 (ja) |
EP (1) | EP2015350B1 (ja) |
JP (1) | JP5358129B2 (ja) |
CN (1) | CN101330109B (ja) |
AT (1) | ATE556430T1 (ja) |
DE (1) | DE102007028316B3 (ja) |
DK (1) | DK2015350T3 (ja) |
ES (1) | ES2384280T3 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105789287A (zh) * | 2014-12-25 | 2016-07-20 | 无锡华润上华半导体有限公司 | 场截止绝缘栅双极晶体管及其制备方法 |
JP6846119B2 (ja) * | 2016-05-02 | 2021-03-24 | 株式会社 日立パワーデバイス | ダイオード、およびそれを用いた電力変換装置 |
CN113555418B (zh) * | 2021-07-21 | 2023-03-10 | 西安电子科技大学 | 基于P区和I区渐变掺杂的4H-SiC PIN微波二极管及制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000223720A (ja) * | 1999-01-29 | 2000-08-11 | Meidensha Corp | 半導体素子およびライフタイム制御方法 |
JP2003152198A (ja) * | 2001-02-23 | 2003-05-23 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004039842A (ja) * | 2002-07-03 | 2004-02-05 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20070108558A1 (en) * | 2005-11-10 | 2007-05-17 | Fuji Electric Device Technology Co., Ltd | Semiconductor device and method of manufacturing the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1167786A (ja) * | 1997-08-25 | 1999-03-09 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP4129106B2 (ja) * | 1999-10-27 | 2008-08-06 | 三菱電機株式会社 | 半導体装置 |
DE10207522B4 (de) * | 2001-02-23 | 2018-08-02 | Fuji Electric Co., Ltd. | Halbleiterbauelement und Verfahren zu dessen Herstellung |
JP4539011B2 (ja) * | 2002-02-20 | 2010-09-08 | 富士電機システムズ株式会社 | 半導体装置 |
DE10243758A1 (de) * | 2002-09-20 | 2004-04-01 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Verfahren zur Herstellung einer vergrabenen Stoppzone in einem Halbleiterbauelement und Halbleiterbauelement mit einer vergrabenen Stoppzone |
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2007
- 2007-06-20 DE DE102007028316A patent/DE102007028316B3/de active Active
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2008
- 2008-05-31 EP EP08009987A patent/EP2015350B1/de active Active
- 2008-05-31 AT AT08009987T patent/ATE556430T1/de active
- 2008-05-31 ES ES08009987T patent/ES2384280T3/es active Active
- 2008-05-31 DK DK08009987.2T patent/DK2015350T3/da active
- 2008-06-18 JP JP2008159106A patent/JP5358129B2/ja not_active Expired - Fee Related
- 2008-06-19 CN CN2008101251868A patent/CN101330109B/zh active Active
- 2008-06-20 US US12/214,641 patent/US8415773B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000223720A (ja) * | 1999-01-29 | 2000-08-11 | Meidensha Corp | 半導体素子およびライフタイム制御方法 |
JP2003152198A (ja) * | 2001-02-23 | 2003-05-23 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004039842A (ja) * | 2002-07-03 | 2004-02-05 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20070108558A1 (en) * | 2005-11-10 | 2007-05-17 | Fuji Electric Device Technology Co., Ltd | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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JP5358129B2 (ja) | 2013-12-04 |
CN101330109A (zh) | 2008-12-24 |
DK2015350T3 (da) | 2012-07-23 |
EP2015350A1 (de) | 2009-01-14 |
ATE556430T1 (de) | 2012-05-15 |
DE102007028316B3 (de) | 2008-10-30 |
ES2384280T3 (es) | 2012-07-03 |
US8415773B2 (en) | 2013-04-09 |
CN101330109B (zh) | 2012-05-02 |
US20090032912A1 (en) | 2009-02-05 |
EP2015350B1 (de) | 2012-05-02 |
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