JP2009004593A - Semiconductor laminate structure, semiconductor device using it and their manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor laminate structure which is excellent in connection reliability, has high productivity and can achieve thinning by using a conductive resin, a semiconductor device using it and their manufacturing method. <P>SOLUTION: The semiconductor laminate structure 1 for which at least a first semiconductor chip 10 having a first wiring electrode and a second semiconductor chip 11 having a second wiring electrode are laminated includes at least the first semiconductor chip 10 connected with the second semiconductor chip 11 in a lamination direction and provided with a first conductive via 10d connected with a prescribed first wiring electrode and filled with a conductive resin and the second semiconductor chip 11 connected with the first semiconductor chip 10 in the lamination direction and provided with a second conductive via 11d connected with a prescribed second wiring electrode and filled with the conductive resin. The first conductive via 10d and the second conductive via 11d facing each other are electrically connected through a conductive connector 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor laminated structure in which a plurality of semiconductor chips having conductive vias are laminated, a semiconductor device using the same, and a method for manufacturing the same.

  2. Description of the Related Art In recent years, with increasing performance and miniaturization of electronic devices, a plurality of semiconductor chips are arranged in one package to form a multi-chip package (Multi Chip Package: MCP). It is planned. The multichip package includes a plurality of semiconductor chips arranged in a plane and a plurality of semiconductor chips stacked in the thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, and therefore contributes little to downsizing of electronic devices. For this reason, development of stacked MCPs in which semiconductor chips are stacked has been actively conducted.

  For example, through a through-hole penetrating a semiconductor chip on which an electrode pad is formed, through a conduction pin comprising a head portion joined to the electrode pad and a shaft portion with the tip protruding from the back surface of the semiconductor chip. An example of a semiconductor device in which a plurality of semiconductor chips are stacked is disclosed (for example, see Patent Document 1). As a result, the stacked semiconductor chips can be electrically connected by the conduction pins inserted into the through holes. Furthermore, since it is connected with a conductive pin, it is said that the multichip can be efficiently made.

  In addition, an example of a semiconductor device in which a plurality of semiconductor chips are stacked via a projecting bump having a seat part welded and bonded to an electrode pad formed on a through hole and a pin part protruding longer than the chip thickness standing from now on. Is disclosed (for example, see Patent Document 2). As a result, the stacked semiconductor chips can be electrically connected by the protruding bumps inserted into the through holes.

  However, in the semiconductor devices of Patent Document 1 and Patent Document 2, since the semiconductor chips are stacked via the heads of the conductive pins and the seats of the protruding bumps, it is difficult to reduce the thickness of the MCP and improve the mounting density. There was a problem that I could not. Further, since the head portion of the conductive pin or the seat portion of the protruding bump and the electrode pad of the semiconductor chip are connected by pressure contact, the semiconductor chip is liable to be cracked or damaged, and there is a problem in reliability.

  Further, in Patent Document 1 and Patent Document 2, it is an impediment to productivity improvement to reduce the size of the conductive pins and the protrusion-shaped bumps corresponding to the narrowing of the pitch and insert them into through holes having a small diameter. It was.

Therefore, in order to avoid the above problem, a module in which LSIs having electrode take-out pads are stacked via an insulating resin, and a conductive resin is filled in and connected to the opening provided at the position of the electrode take-out pad. Are disclosed (for example, see Patent Document 3). As a result, it can be modularized with the use of general LSI and the minimum required mounting area.
JP 2001-77296 A JP 2001-135785 A JP-A-10-163411

  However, in the module of Patent Document 3, since the LSIs are connected with a conductive resin after being stacked, if there is a problem with the stacked LSIs, the repair is difficult and the productivity is low due to a decrease in yield. is there. In addition, an opening cannot be formed only between LSIs stacked inside, and the opening must be made from at least the outermost LSI. Further, in order to cope with the narrow pitch, it is difficult to fill the openings having a fine diameter provided integrally with the plurality of semiconductor chips with the conductive resin. Therefore, for example, when the conductive resin is cured by heating the conductive resin by lowering the viscosity and the conductive resin is heated, the amount of cure shrinkage is large and it is easy to become porous. There is a problem of causing defects.

  In order to avoid this, a method is conceivable in which a plurality of LSIs are stacked after through holes are individually formed through LSIs and filled with a conductive resin. However, as described above, in general, when a conductive resin is filled and cured, the conductive resin is dented on the upper and lower surfaces of the LSI through hole due to curing shrinkage. Therefore, there is a problem that the stacked LSIs cannot be electrically connected reliably.

  The present invention has been made in order to solve the above-described problems. A semiconductor multilayer structure using a conductive resin, excellent in connection reliability, high in productivity, and capable of realizing thinning, and a semiconductor using the same It is an object of the present invention to provide an apparatus and a manufacturing method thereof.

  In order to achieve the above-described object, a semiconductor multilayer structure according to the present invention includes a semiconductor multilayer structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked. A first semiconductor chip having a first conductive via that is connected to the second semiconductor chip in the stacking direction and filled with a conductive resin that is connected to a predetermined first wiring electrode, and the first semiconductor chip in the stacking direction. And at least a second semiconductor chip having a second conductive via filled with a conductive resin to be connected to a predetermined second wiring electrode, and the first conductive via and the second conductive via facing each other are conductively connected. It has a configuration that is electrically connected through the body.

  Further, the conductive connection body is made of an individual member having a plurality of protrusions. Furthermore, the individual member may be configured by metal plating the outer periphery of a cured conductive resin or a cured insulating resin. Furthermore, the individual member may be configured by metal-plating the outer periphery of a photocurable conductive resin cured product or a photocurable insulating resin cured product formed by an optical modeling method. Further, the volume of the conductive connection body is larger than the space volume of the first conductive via and the second conductive via, which are hardened and contracted by the conductive resin.

  With these configurations, it is possible to compensate the dent of the conductive via due to the curing shrinkage of the conductive resin with the conductive connection body, and it is possible to realize a semiconductor laminated structure excellent in connection reliability by reliable connection.

  Furthermore, the conductive connection body may be made of a photocurable conductive resin cured product formed by an optical modeling method having at least one convex portion. Furthermore, the volume of at least the convex portion of the conductive connection body may be larger than the space volume of the first conductive via and the conductive resin of the second conductive via that is cured and contracted.

  Accordingly, the recesses of the conductive via due to the curing shrinkage of the conductive resin can be compensated by the convex portion made of the photocurable conductive resin cured product, and a semiconductor laminated structure excellent in connection reliability can be realized by reliable connection.

  Furthermore, the conductive resin and the conductive connector may be made of a photocurable conductive resin integrally formed by an optical modeling method.

  Thereby, since a conductive resin and a conductive connection body can be formed integrally, it is possible to realize a semiconductor laminated structure having excellent productivity and high connection reliability.

  In addition, a semiconductor device of the present invention has a configuration in which the above-described semiconductor multilayer structure is mounted on a wiring board and electrically connected to a connection electrode of the wiring board through a first conductive via. With this configuration, a thin semiconductor device having excellent connection reliability can be realized.

  The method for manufacturing a semiconductor multilayer structure according to the present invention is a method for manufacturing a semiconductor multilayer structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked. Connecting the first semiconductor chip to the second semiconductor chip in the stacking direction and forming a first through hole connecting to a predetermined first wiring electrode; and connecting the first semiconductor chip to the first semiconductor chip in the stacking direction. And forming a second through-hole connected to a predetermined second wiring electrode, filling the first through-hole and the second through-hole with conductive resin paste, and filling the first semiconductor chip with the first conductive via and the second through-hole. A conductive via forming step of forming a second conductive via in the semiconductor chip; a conductive connector forming step of forming a conductive connector; and at least one surface of the first semiconductor chip or the second semiconductor chip A conductive connection body disposing step of disposing the conductive connection body in the first conductive via or the second conductive via; and a first conductive via of the predetermined first semiconductor chip and a second conductive via of the second semiconductor chip. And a semiconductor chip stacking step of electrically connecting the first conductive via and the second conductive via via the conductive connection bodies that are combined and adhered.

  By this method, the conductive via dent due to the curing shrinkage of the conductive resin can be compensated with the conductive connecting body, and a reliable semiconductor connection structure with excellent connection reliability can be produced with high productivity.

  Further, in the conductive connector forming step, a photocurable conductive resin liquid or a photocurable insulating resin liquid is exposed and developed into a predetermined shape by an optical modeling method using a liquid crystal mask or a laser beam, and a non-exposed portion is formed. May be included, and a conductive connection body of the photocurable conductive resin cured product or a conductive connection body in which the outer periphery of the formed photocurable insulating resin cured product is metal-plated may be included.

  Thereby, the electroconductive connection body which has arbitrary shapes can be produced cheaply with high productivity.

  Further, the conductive connector having at least one convex portion at a position that is connected to the first conductive via of the first semiconductor chip and that faces the second conductive via of the second semiconductor chip in the steps after the conductive via forming step. The conductive connecting body forming step for forming the first conductive conductor by aligning the convex portion of the predetermined conductive connecting body with the second conductive via of the second semiconductor chip, and the first conductive through the conductive connecting body. A semiconductor chip stacking step of electrically connecting the via and the second conductive via.

  This makes it possible to compensate the dents in the conductive via due to the curing shrinkage of the conductive resin with the convex portion made of the photo-curing conductive resin cured product, realize a reliable connection, and achieve a highly reliable semiconductor laminated structure with high productivity. Can be made.

  The method for manufacturing a semiconductor multilayer structure according to the present invention is a method for manufacturing a semiconductor multilayer structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked. Connecting the first semiconductor chip to the second semiconductor chip in the stacking direction and forming a first through hole connecting to a predetermined first wiring electrode; and connecting the first semiconductor chip to the first semiconductor chip in the stacking direction. And a step of forming a second through hole connected to a predetermined second wiring electrode, and a step of immersing the first semiconductor chip in a photo-curable conductive resin liquid, and the photo-curable conductive resin in the first through-hole Forming a first conductive via by photocuring, and a step of forming a conductive connector connected to the first conductive via, and further immersing the second semiconductor chip in the photocurable conductive resin liquid, Pair with conductive connector Aligning with the second through hole to be formed, photo-curing the photocurable conductive resin in the second through hole to form a second conductive via, and the first conductive via and the second through the conductive connector And a semiconductor chip stacking step for electrically connecting the conductive vias.

  As a result, the semiconductor via structure can be formed by continuously and integrally forming the conductive via and the conductive connection body with the photocurable conductive resin. Furthermore, since there is no connection interface between the conductive via and the conductive connector, the connection strength is excellent and a connection with low resistance is obtained.

  The method for manufacturing a semiconductor multilayer structure according to the present invention is a method for manufacturing a semiconductor multilayer structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked. A first conductive via is formed in the first semiconductor chip by filling the first semiconductor chip with a conductive resin paste in a first through-hole connected to the first semiconductor chip in the stacking direction with the second semiconductor chip. And a first semiconductor chip forming step of forming a conductive connection body having at least one convex portion connected to the first conductive via by an optical modeling method, and connecting the first semiconductor chip to the second semiconductor chip in the stacking direction. And a second semiconductor chip forming step of forming a second conductive via in the second semiconductor chip by filling a second through hole connected to a predetermined second wiring electrode with a conductive resin paste, and a first semiconductor Semiconductor chip lamination in which the convex portion of the conductive connection body of the chip and the second conductive via of the second semiconductor chip are aligned, and the first conductive via and the second conductive via are electrically connected via the conductive connection body And a process.

  By this method, the first semiconductor chip and the second semiconductor chip provided with the conductive connection body can be individually manufactured and arbitrarily combined to manufacture the semiconductor multilayer structure. Therefore, a semiconductor multilayer structure with a high degree of design freedom can be easily manufactured.

  Moreover, the semiconductor device manufacturing method of the present invention may be mounted by connecting the semiconductor multilayer structure formed by the above manufacturing method to the connection electrode of the wiring board.

  By this method, a thin semiconductor device having excellent connection reliability can be manufactured with high productivity.

  According to the semiconductor multilayer structure of the present invention, the semiconductor device using the semiconductor multilayer structure, and the manufacturing method thereof, the conductive resin is used, the connection reliability is excellent, the productivity is high, and the thinned semiconductor multilayer structure or It has a great effect on the realization of a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and description may be abbreviate | omitted. In the following, a semiconductor device mounted with a semiconductor multilayer structure will be described as an example, but it goes without saying that only the semiconductor multilayer structure may be basically used. Furthermore, in the following description, a configuration in which two semiconductor chips are stacked will be described, but it is needless to say that the present invention is not limited to this.

(First embodiment)
FIG. 1A is a plan view showing the configuration of the semiconductor multilayer structure 1 according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of FIG. FIG. 1C is a cross-sectional view showing a configuration of the semiconductor device 100 on which the semiconductor multilayer structure 1 according to the first embodiment of the present invention is mounted.

  As shown in FIGS. 1A and 1B, the semiconductor multilayer structure 1 includes a first semiconductor chip 10 having at least a first wiring electrode (not shown) and a second wiring electrode (not shown). The second semiconductor chip 11 is stacked. The first semiconductor chip 10 includes a first conductive via 10d filled with a conductive resin 10c connected to the second semiconductor chip 11 in the stacking direction and connected to a predetermined first wiring electrode. Similarly, the second semiconductor chip 11 includes a second conductive via 11d filled with a conductive resin 11c connected to the first semiconductor chip 10 in the stacking direction and connected to a predetermined second wiring electrode. Further, at least the predetermined first conductive via 10d and the second conductive via 11d are electrically connected via, for example, a conductive connection body 12 including an individual member 12a having a plurality of protrusions 12b, and the semiconductor laminated structure 1 is configured.

  At this time, the conductive resins 10c and 11c are made of, for example, a cured conductive resin including a paste in which conductive particles such as silver, copper, and nickel are mixed with a thermosetting resin or a photocurable thermosetting resin. ing. Therefore, as shown in FIG. 1B, the first conductive via 10d and the second conductive via 11d are generally dented at the upper and lower ends due to the curing shrinkage of the conductive resins 10c and 11c (hereinafter referred to as “concave portions”). 13 is produced. As a result, when the first semiconductor chip and the second semiconductor chip are stacked and connected, the generation of the concave portion causes an increase or variation in connection resistance, and further causes connection failure. Therefore, the first conductive via 10d of the first semiconductor chip 10 and the second conductive via 11d of the second semiconductor chip 11 are connected to each other by, for example, pressing the protrusion 12b of the conductive connection body 12 between the recesses 13. 12 for electrical connection.

  In addition, as will be described in detail below, the individual member 12a of the conductive connection body 12 is a photocurable conductive resin cured product or photocurable insulating resin cured product formed into a predetermined shape by an optical modeling method. The outer periphery of is formed by metal plating.

  According to this embodiment, the conductive connection body connects the recesses due to the curing shrinkage of the conductive via filled with the conductive resin, thereby realizing a stable connection between the first semiconductor chip and the second semiconductor chip. it can.

  Even if a semiconductor chip is connected using a conductive resin having a higher resistivity than metal, the connection resistance variation is reduced by connecting through a conductive connector having a low resistivity, resulting in high-speed operation. It is possible to realize a semiconductor laminated structure that can be used.

  Moreover, since the composition of the conductive resin filling the conductive via and the photocurable conductive resin of the conductive connection body can be made of substantially the same material, a stable connection that hardly causes peeling due to thermal history can be realized. Furthermore, the conductive resin and the conductive connector can be integrated by heating to be firmly connected.

  Further, as shown in FIG. 1C, the semiconductor multilayer structure 1 having the above-described configuration is mounted on a wiring substrate 110 such as a glass epoxy substrate or a ceramic substrate having a wiring pattern 110a, for example. Composed. Then, the connection electrode 113 made of, for example, a conductive resin and the first conductive via 10d of the first semiconductor chip 10 of the semiconductor multilayer structure 1 formed in part of the wiring pattern 110a of the wiring substrate 110 are electrically connected. Connected to. At this time, it is preferable that the volume of the connection electrode 113 is larger than the space volume of the recess of the first conductive via 10d. Further, the conductive connection body 12 may be provided between the first conductive via 10d and the connection electrode 113, and the connection may be made therebetween.

  Thereby, the thin semiconductor device 100 with excellent connection reliability can be realized in which the semiconductor multilayer structure 1 is mounted with high density.

  In the present embodiment, the conductive connecting body has been described as an example in which at least a part of the protrusion is pushed into the opposing conductive resin and connected, but the present invention is not limited thereto. For example, by embedding a conductive connection body having a size equal to or larger than the space volume of the recess, the space of the recess is filled with the conductive resin and connected with the conductive connection body, and the conductive vias facing each other are connected with the conductive resin. May be. As a result, it is possible to realize a semiconductor multilayer structure and a semiconductor device with further reduced connection resistance. Furthermore, since the gap between the semiconductor chips is further narrowed by embedding the conductive connection body, a thinner semiconductor multilayer structure and semiconductor device can be realized.

  Moreover, although this Embodiment demonstrated in the example using the photocurable conductive resin hardened | cured material or the metal-plated photocurable insulating resin hardened | cured material as an electroconductive connection body, it is not restricted to this. For example, a conductive dendritic conductor having a conductive protrusion, for example, a conductive whisker such as a quadrangular pyramidal needle-shaped crystalline conductor, or a plurality of dendritic crystals grown on the surface of silver particles or nickel particles. Particles, conductive particles using a conductive polymer, or the like may be used. Thereby, a semiconductor multilayer structure and a semiconductor device can be obtained at low cost and high productivity.

  Further, in the present embodiment, the example in which the semiconductor chips are connected only by the conductive connection member has been described, but the present invention is not limited to this, and an insulating adhesive may be injected and bonded between the semiconductor chips excluding the connection part. Good. Thereby, reliability, such as the mechanical strength of a semiconductor laminated structure and a semiconductor device, and the moisture resistance of a connection part, can be improved.

  Moreover, although this Embodiment demonstrated the individual member which has a sharp projection part as an example as an electroconductive connection body, it is not restricted to this. For example, as shown in the conceptual cross-sectional view of FIG. 2A, the conductive connector 121 may be formed of an individual member 121a having a plurality of conductive protrusions 121b having a rectangular convex shape protruding in six directions of vertical and horizontal directions. . Further, as shown in the conceptual cross-sectional view of FIG. 2B, for example, the conductive connecting body 122 formed of the individual member 122a having a plurality of star-shaped protrusions 122b may be used, and the conceptual cross-sectional view of FIG. As shown by, for example, the conductive connecting member 123 may be formed of an individual member 123a having a plurality of dendritic protrusions 123b. In addition, if a conductive connection body is a shape which has a projection part, it will not restrict | limit in particular. By using these, the same effect can be obtained.

  Hereinafter, a method for manufacturing the semiconductor multilayer structure and the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  3 and 4 are cross-sectional views illustrating a method for manufacturing the semiconductor multilayer structure 1 and the semiconductor device 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 3A, by the following method, the silicon substrate 10a to be the first semiconductor chip 10 is connected to the second semiconductor chip in the stacking direction and to a predetermined first wiring electrode. A first through hole 10b having a diameter of 100 μm to 200 μm is formed.

  That is, first, a silicon oxide film is formed on at least one surface 100a of the first semiconductor chip 10 by using, for example, a CVD method. Then, an opening 102 having a predetermined shape is formed in the silicon oxide film by using a photolithography technique to form an etching pattern mask 101. Furthermore, the silicon substrate 10a is etched to a predetermined depth from the opening 102 by using an etching method to form a plurality of first through holes 10b. At this time, the first through hole 10b is not formed with a functional part (not shown) of the silicon substrate 10a, for example, an outer peripheral part of the electrode pad of the first wiring electrode (not shown) connected to the functional part. It is formed at a position where it is connected only to the wiring electrodes of the semiconductor chips stacked above and below. The first through hole 10b may be formed through the silicon substrate 10a. However, when the silicon substrate 10a is isotropically etched, the first through hole 10b should be stopped to a predetermined depth (about 100 μm). preferable. Further, although not shown, the etching pattern mask 101 is removed, and an insulating film (not shown) with at least the electrode pad exposed is formed as necessary.

  Next, as shown in FIG. 3B, the conductive resin paste 103 is filled into the first through hole 10b of the silicon substrate 10a with, for example, a squeegee 104 or the like. At this time, a conductive paste material in which conductive particles and a thermosetting resin are kneaded is used as the conductive resin paste 103. Here, silver, copper, nickel, or the like can be used as the conductive particles, and an epoxy resin or an acrylic resin can be used as the thermosetting resin. Then, the silicon substrate 10a is polished from the other surface 100b to a predetermined thickness, for example, 50 μm, using, for example, a polishing method to produce a first semiconductor chip. At this time, polishing may be performed after the conductive resin paste 103 is filled or before.

  Next, as shown in FIG. 3C, in the manufactured first semiconductor chip 10, for example, the conductive resin paste 103 is thermally cured at a low temperature and the semiconductive resin 10 c is used to form the first semiconductor chip 10. A first conductive via 10d is formed. At this time, since the conductive resin 10c is in a semi-cured state, it is soft and sticky. However, since the thermally cured conductive resin 10c shrinks in volume at the time of curing, the first conductive via 10d is depressed from the one surface 100a or the other surface 100b of the first semiconductor chip 10 in the first through hole 10b. A recess 13 is formed.

  Next, as shown in FIG. 3 (d), a conductive connection body 12 is prepared, which is formed by a method described later, for example, and includes a plurality of individual members 12a having sharp-shaped protrusions 12b in six vertical and horizontal directions. To do. At this time, it is preferable to form the volume of the conductive connection body 12 larger than the space volume of the first conductive via 10d that is hardened and contracted by the conductive resin 10c. Moreover, it is preferable to form the protrusion part 12b with the length longer than the depth of the recessed part 13 of the conductive resin 10c at least.

  Next, as shown in FIG. 3 (e), the conductive connection body 12 is formed on the one surface 100a of the first semiconductor chip 10 by a method such as spraying, and the conductive resin 10c of the first conductive via 10d. The conductive connector 12 is attached to the surface of the recess 13. Thereafter, the non-adhesive conductive connection body 12 is removed from the first semiconductor chip 10 by spraying an inert gas such as nitrogen gas. At this time, since the conductive resin 10c is in a semi-cured state, at least one or a plurality of the conductive connectors 12 dispersed by the adhesiveness adhere to the surface of the conductive resin 10c.

  Next, as shown in FIG. 4A, the first semiconductor chip 10 manufactured in the steps of FIGS. 3A to 3E and the same as in FIGS. 3A to 3C. The second semiconductor chip 11 produced in the process is prepared. At this time, the second semiconductor chip 11 has the second conductive via 11d filled with the conductive resin 11c connected to the first semiconductor chip 10 in the stacking direction and connected to the second wiring electrode (not shown). is doing.

  Then, the first conductive via 10d of the predetermined first semiconductor chip 10 and the second conductive via 11d of the second semiconductor chip 11 are aligned and pressed, for example, in the direction of the arrow in the drawing.

  Further, while pressurizing the first semiconductor chip 10 and the second semiconductor chip 11, the conductive resins 10 c and 11 c are thermally cured at a temperature (for example, 150 ° C.) higher than the temperature at the time of semi-curing to be stacked and fixed.

  As a result, at least a part of the protrusion 12b of the conductive connecting body 12 attached to the surface of the conductive resin 10c is pushed between the conductive resins 10c and 11c facing each other, and the first conductive via 10d and the second conductive via 11d. Are electrically connected through at least the conductive connecting body 12. At this time, since the conductive resins 10c and 11c pushed away by the conductive connecting body 12 also fill the recess 13 space, they are also connected between the conductive resins. Furthermore, if the volume of the conductive connection body 12 is larger than the volume of the recess 13 space of the first conductive via 10d and the second conductive via 11d, the recess 13 can be reliably filled with the conductive resins 10c and 11c. A reliable connection can be realized.

  Through the above-described process, the semiconductor multilayer structure 1 having the MCP structure in which at least the first semiconductor chip 10 and the second semiconductor chip 11 are laminated via the conductive connection body 12 as shown in FIG. .

  The heating step is performed when the semiconductor multilayer structure is a finished product. For example, when mounting on a wiring board, the conductive resin proceeds to the following step in a semi-cured state.

  Next, as shown in FIG. 4C, the first conductive via 10d of the semiconductor multilayer structure 1 and the connection electrode 113 formed at a predetermined position of the wiring pattern 110a of the wiring substrate 110 are aligned. Pressurize. At this time, the connection electrode 113 is, for example, a bump formed of solder, gold, conductive resin, or the like.

  Then, as illustrated in FIG. 4D, the semiconductor device 100 is manufactured by curing the conductive resins 10 c and 11 c while being pressed and connected.

  Below, the manufacturing method of the electroconductive connection body used for the 1st Embodiment of this invention is demonstrated using FIG.

  FIG. 5 is a cross-sectional view illustrating a method for manufacturing the conductive connector 12 used in the first embodiment of the present invention.

  First, as shown in FIG. 5A, a stage 44 that can move at least up and down in a container 43 filled with a photocurable conductive resin liquid 42 is disposed at the level of the liquid level of the photocurable conductive resin liquid 42. To do. Then, for example, ultraviolet light or visible light is irradiated from the opening 41 a of the liquid crystal mask 41, and the photocurable conductive resin liquid 42 is photocured while the stage 44 is submerged. In addition, as the photocurable conductive resin liquid 42, for example, a mixture of conductive particles such as silver and an acrylic photocurable resin liquid can be used.

  Next, as shown in FIG. 5B, the stage 44 is sunk stepwise or continuously, and the shape of the opening 41a of the liquid crystal mask 41 is controlled in synchronism therewith, so that a photocurable conductive resin liquid is obtained. 42 is exposed to a predetermined shape and photocured.

  Next, as shown in FIG.5 (c), the stage 44 is taken out from the container 43, the surrounding uncured photocurable conductive resin liquid 42 is removed, and the electroconductive connection body 12 is produced.

  And the conductive connection body 12 which consists of the individual member 12a which has the some projection part 12b as shown in FIG.5 (d) by the said process is obtained.

  Thereby, the conductive connection body which consists of an individual member which has the projection part of a predetermined shape can be freely formed in a large quantity and a simple method.

  In this embodiment, the example in which the conductive connection body is collectively formed using the liquid crystal mask has been described, but the present invention is not limited thereto. For example, the conductive connection body may be formed by performing exposure in synchronization with the movement of the stage while scanning a laser beam on the surface of the photocurable conductive resin liquid 42.

  Moreover, although this Embodiment demonstrated the example which formed the electroconductive connection body with the photocurable conductive resin, it is not restricted to this. For example, even if a conductive connection body is formed by forming a photocurable insulating resin cured product using a photocurable insulating resin such as an acrylic resin and plating the outer periphery thereof with a metal such as gold, for example. Good. Accordingly, the connection resistance can be further reduced by the metal-plated conductive connector having a small specific resistivity.

(Second Embodiment)
A semiconductor stacked structure and a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG.

  FIG. 6A is a plan view showing the configuration of the semiconductor multilayer structure 2 according to the second embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along line AA of FIG. FIG. 6C is a cross-sectional view showing a configuration of the semiconductor device 200 on which the semiconductor multilayer structure 2 according to the second embodiment of the present invention is mounted.

  The semiconductor multilayer structure 2 shown in FIG. 6 is configured such that the conductive connection body 52 is formed of a photocurable conductive resin cured product having at least one convex portion 52b formed in the first conductive via. This is different from the first embodiment made up of individual members. Then, the conductive connection body 52 is formed directly on the first conductive via 10d by an optical modeling method. At this time, if necessary, the volume of at least the convex portion 52b of the conductive connecting body 52 is set to the spatial volume of the concave portion 13 generated by the curing shrinkage of the conductive resins 10c and 11c of the first conductive via 10d and the second conductive via 11d. Larger than that.

  Then, as shown in FIG. 6B, the semiconductor laminated structure 2 is configured by electrically connecting the opposing first conductive via 10d and second conductive via 11d via the conductive connection body 52. Is done.

  According to the present embodiment, the conductive connection body can be connected by filling the concave portions due to the curing shrinkage of the conductive via filled with the conductive resin, so that there is a variation in the connection resistance between the first semiconductor chip and the second semiconductor chip. A semiconductor stacked structure having a small and stable connection can be realized.

  Moreover, since the connection with the electrode pad (not shown) of the first semiconductor chip 10 can be formed together with the formation of the conductive connection body, a reliable and reliable semiconductor multilayer structure can be realized. In general, the electrode pad has a diameter slightly larger than the diameter of the conductive via of the semiconductor chip and is provided on the surface thereof.

  Further, as shown in FIG. 6C, the semiconductor laminated structure 2 having the above configuration is mounted on a wiring substrate 110 such as a glass epoxy substrate or a ceramic substrate having a wiring pattern 110a, for example. Composed. Then, the connection electrode 113 made of, for example, a conductive resin and the first conductive via 10d of the first semiconductor chip 10, for example, formed on a part of the wiring pattern 110a of the wiring substrate 110 are electrically connected. Connected to. At this time, it is preferable that the volume of the connection electrode 113 is larger than the space volume of the recess of the first conductive via 10d.

  Thereby, it is possible to realize a thin semiconductor device 200 having the semiconductor laminated structure 2 mounted with high density and excellent in connection reliability.

  In addition, since the conductive connection body 52 can be manufactured using the same material as the conductive connection body 12 of the first embodiment, description thereof is omitted.

  Hereinafter, a method for manufacturing a semiconductor multilayer structure and a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.

  7 and 8 are cross-sectional views illustrating a method for manufacturing the semiconductor multilayer structure 2 and the semiconductor device 200 according to the second embodiment of the present invention.

  In the second embodiment, the steps after the conductive via formation step are different from those in the first embodiment, and the other steps are the same. Therefore, referring to FIGS. 3 and 4 as appropriate. explain. That is, the process after the formation of the conductive via includes a process of forming a conductive connection body having at least one convex portion on the first conductive via of the first semiconductor chip by an optical modeling method, and a predetermined conductivity. This includes a semiconductor chip stacking step in which the first conductive via and the second conductive via are electrically connected via the convex portion of the connection body.

  First, as shown in FIG. 7A, a first semiconductor chip 10 having a first conductive via 10d formed by a method similar to that shown in FIGS. 3A to 3C is prepared.

  Next, as shown in FIG. 7B, the first semiconductor chip 10 placed on the stage 64 that can move at least up and down in the container 60 filled with the photocurable conductive resin liquid 62 is photocurable. It is immersed in the liquid level position of the conductive resin liquid 62. Then, for example, ultraviolet light or visible light is irradiated from the opening 61 a of the liquid crystal mask 61, and the photocurable conductive resin liquid 62 is photocured while the stage 64 is submerged.

  Furthermore, the stage 64 is submerged stepwise or continuously, and the shape of the opening 61a of the liquid crystal mask 61 is controlled in synchronization with the stage 64, and the photocurable conductive resin liquid 62 is exposed to a predetermined shape and photocured. . In FIG. 7B, the openings 61a of the liquid crystal mask 61 are sequentially reduced and hardened with sharp convex portions such as a triangular pyramid or a conical shape.

  Next, as shown in FIG. 7C, the first semiconductor chip 10 is taken out of the container 60, and the surrounding uncured photocurable conductive resin liquid 62 is removed. As a result, the first semiconductor chip 10 in which the conductive connection body 52 having the sharp convex portion 52b in which the concave portion 13 of the first conductive via 10d of the first semiconductor chip 10 is filled is formed. At this time, the conductive connection body 52 is preferably formed so as to cover the electrode pads of the first semiconductor chip 10. In addition, the conductive connection body 52 is formed such that at least the volume of the convex portion 52b is larger than the space volume of the concave portion 13 where the conductive resins 10c and 11c of the first conductive via 10d and the second conductive via 11d are cured and contracted. Is preferred. Furthermore, it is preferable that the height of the convex portion 52b is longer than the depth of the concave portion 13 of the conductive resins 10c and 11c.

  Next, as shown in FIG. 7 (d), the conductive connection body 52 of the first semiconductor chip 10 and the second conductive via of the second semiconductor chip 11 manufactured in the same process as in FIG. 7 (a). Positioning is performed so that 11d faces each other, and pressure is applied from the direction of the arrow in the drawing, for example.

  Next, as shown in FIG. 7E, the conductive resins 10c and 11c are heated at a temperature higher than the temperature at the time of semi-curing (for example, 150 ° C.) while pressurizing the first semiconductor chip 10 and the second semiconductor chip 11. Heat cured, laminated and fixed. As a result, the semiconductor multilayer structure 2 having an MCP structure in which at least the first semiconductor chip 10 and the second semiconductor chip 11 are laminated via the conductive connection body 52 is manufactured. At this time, the convex portion 52b of the conductive connecting body 52 formed on the surface of the conductive resin 10c is pushed into the opposing conductive resin 11c, and at least the first conductive via 10d and the second conductive via 11d are at least the conductive connecting body. Electrical connection is made via 52.

  The heating step is performed when the semiconductor multilayer structure is a finished product. For example, when mounting on a wiring board, the conductive resin proceeds to the following step in a semi-cured state.

  Next, as shown in FIG. 8A, a wiring board 110 is prepared in which a connection electrode 113 is formed at a predetermined position of the wiring pattern 110a. At this time, the connection electrode 113 is, for example, a bump formed of solder, gold, conductive resin, or the like.

  Next, as shown in FIG. 8B, the first conductive via 10 d of the semiconductor multilayer structure 2 and the connection electrode 113 of the wiring board 110 are aligned and pressed, and the convex portion of the conductive connection body 52. 52b is press-fitted into the first conductive via 10d.

  Then, as illustrated in FIG. 8C, the semiconductor device 200 is manufactured by curing the conductive resins 10 c and 11 c in a state of being press-fitted and connected.

  According to the present embodiment, the semiconductor laminated structure is efficiently obtained by a simple method of connecting the conductive resin between the conductive vias through the convex portions of the conductive connecting body formed at the positions facing each other by stereolithography. Bodies and semiconductor devices can be manufactured.

(Third embodiment)
The semiconductor laminated structure and semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG.

  FIG. 9A is a plan view showing the configuration of the semiconductor multilayer structure 3 according to the third embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along line AA of FIG. 9A. FIG. 9C is a cross-sectional view showing the configuration of the semiconductor device 300 on which the semiconductor multilayer structure 3 according to the third embodiment of the present invention is mounted.

  The semiconductor laminated structure 3 shown in FIG. 9 has a configuration in which a conductive resin and a conductive connection body for connecting the first semiconductor chip 10 and the second semiconductor chip 11 are integrally formed by an optical modeling method. This is different from the semiconductor multilayer structures of the above embodiments.

  That is, the semiconductor multilayer structure 3 includes the conductive resin 70c of the first conductive via 10d of the first semiconductor chip 10, the conductive resin 71c of the second conductive via 11d of the second semiconductor chip 11, and the conductive connection that connects them. The body 72 is integrally formed of the same photocurable conductive resin by an optical modeling method.

  As a result, as shown in FIG. 9B, the conductive resins 70c and 71c of the first conductive via 10d and the second conductive via 11d facing each other are electrically connected via the conductive connector 72. The semiconductor laminated structure 3 is obtained.

  According to the present embodiment, since the conductive resin of each conductive via and the conductive connection body interposed therebetween are integrally formed of the same material by stereolithography, a configuration in which no connection interface exists can be achieved. As a result, it is possible to realize a semiconductor laminated structure and a semiconductor device that have a low connection resistance value and that do not cause poor connection.

  Further, as shown in FIG. 9C, the semiconductor multilayer structure 3 having the above-described configuration is mounted on a wiring substrate 110 such as a glass epoxy substrate or a ceramic substrate having a wiring pattern 110a, for example. Composed. Then, the connection electrode 113 made of, for example, a conductive resin formed in a part of the wiring pattern 110a of the wiring substrate 110 is pushed in, and the first conductive via 10d of the first semiconductor chip 10 of the semiconductor multilayer structure 3 is pressed. Are electrically connected.

  Thereby, it is possible to realize a thin semiconductor device 300 excellent in connection reliability, in which the semiconductor multilayer structure 3 is mounted at a high density.

  Below, the manufacturing method of the semiconductor laminated structure and semiconductor device of the 3rd Embodiment of this invention is demonstrated using FIG.

  FIG. 10 is a cross-sectional view illustrating a method for manufacturing the semiconductor multilayer structure 3 and the semiconductor device 300 according to the third embodiment of the present invention.

  First, as shown in FIG. 10A, the first semiconductor provided with the first through hole 10b not filled with the conductive resin manufactured by the same method as in FIGS. 3A and 3B. The chip 10 is prepared.

  Next, as shown in FIG. 10B, the first semiconductor chip 10 placed on the stage 64 that can move at least up and down in the container 60 filled with the photocurable conductive resin liquid 62 is photocurable. The conductive resin liquid 62 is immersed in a position at a predetermined depth from the liquid surface. Then, for example, ultraviolet light or visible light is irradiated from the opening 61 a of the liquid crystal mask 61 to photocur the photocurable conductive resin liquid 62 between the stages 64. At this time, the exposure is preferably performed while changing the depth of focus, for example. Thus, the first conductive via 10d and the conductive connector 72 can be formed by sequentially curing the photocurable conductive resin sequentially from the vicinity of the stage 64 of the first through hole 10b of the first semiconductor chip 10.

  Next, as shown in FIG. 10C, the first semiconductor chip 10 in which the conductive resin 70 c and the conductive connection body 72 are integrally formed in the first through hole 10 b is further submerged by the stage 64, The second semiconductor chip 11 is immersed in the photocurable conductive resin liquid 62 while being aligned with the conductive connector 72. Then, the photocurable conductive resin liquid 62 filled in the second through hole 11b of the second semiconductor chip 11 is photocured to form the second conductive via 11d made of the conductive resin 71c. Thereby, the conductive connection body 72 and the conductive resin 71c are connected.

  Next, as shown in FIG. 10D, the first semiconductor chip 10 is taken out of the container 60, and the surrounding uncured photocurable conductive resin liquid 62 is removed. As a result, the conductive connectors 70c and 71c of the first conductive via 10d of the first semiconductor chip 10 and the second conductive via 11d of the second semiconductor chip 11 are formed by the conductive connection body 72 integrally formed of the same material. The semiconductor laminated structure 3 is produced by connection. At this time, it is preferable to form the conductive connection body 72 so as to cover the electrode pads of the first semiconductor chip 10. In this case, the conductive connection body is formed with a diameter slightly larger than the diameter of the first conductive via or the second conductive via. These can be easily manufactured by controlling the shape of the opening 61 a of the liquid crystal mask 61.

  Next, as shown in FIG. 10E, a wiring board 110 is prepared in which a connection electrode 113 is formed at a predetermined position of the wiring pattern 110a. At this time, the connection electrode 113 is, for example, a bump formed of solder, gold, conductive resin, or the like. Then, the first conductive via 10d of the semiconductor multilayer structure 3 and the connection electrode 113 of the wiring substrate 110 are aligned and pressed, and the connection electrode 113 is press-fitted into the first conductive via 10d.

  Then, as shown in FIG. 10F, the semiconductor device 300 is manufactured by heating while being press-fitted and connected to electrically connect the conductive resin and the connection electrode.

  According to the present embodiment, since the conductive resin of the conductive via and the conductive connection body are integrally formed of the same material, the connection interface does not exist. A semiconductor multilayer structure and a semiconductor device that do not occur can be manufactured with high productivity.

(Fourth embodiment)
The semiconductor device according to the fourth embodiment of the present invention will be described below with reference to FIG.

  FIG. 11A is a plan view showing a configuration of a semiconductor device 400 according to the fourth embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along line AA of FIG. In FIG. 11A, a plan view of the semiconductor multilayer structure 4 constituting the semiconductor device 400 is shown, and other components are omitted.

  That is, the semiconductor stacked structure 4 is provided in such a manner that a part of the second conductive via of the second semiconductor chip is provided at a position not facing the first conductive via of the first semiconductor chip and they are connected by the conductive connection body. It is different from the semiconductor laminated structure 3 of the third embodiment. Further, the semiconductor stacked structure 4 is directly mounted on the wiring substrate 810 to form the semiconductor device 400, which is different from the semiconductor devices of the above embodiments.

  As shown in FIG. 11, the semiconductor device 400 has a configuration in which the semiconductor multilayer structure 4 is mounted directly on a connection portion (not shown) of the wiring pattern 810 a of the wiring substrate 810 using an optical modeling method. At this time, the semiconductor multilayer structure 4 has a configuration in which at least a first semiconductor chip 80 having a first wiring electrode (not shown) and a second semiconductor chip 81 having a second wiring electrode (not shown) are laminated. Become. In the second semiconductor chip 81, at least a portion of the second conductive via 81 d is provided at a position that does not face the first conductive via 80 d of the first semiconductor chip 80. At this time, the conductive resin 80c of the first conductive vias 80d and 801d of the first semiconductor chip 80, the conductive resin 81c of the second conductive vias 81d and 811d of the second semiconductor chip 81, and the conductive connector 82 connecting them. , 821 are integrally formed of the same photocurable conductive resin by an optical modeling method.

  Further, as shown in FIG. 11B, the semiconductor device 400 transmits the semiconductor laminated structure 4 through the connection portion of the wiring pattern 810a of the wiring substrate 810 and the first conductive vias 80d and 801d of the first semiconductor chip 80. It consists of the structure electrically connected through the curable conductive resin.

  According to this embodiment, the same effects as those of the third embodiment can be obtained, and the conductive vias of the respective semiconductor chips can be arranged at arbitrary positions, so that the degree of freedom in design is improved.

  Moreover, according to this Embodiment, since a wiring board and a semiconductor laminated structure can be connected with a photocurable conductive resin, mounting with a low load is realizable. As a result, a highly reliable semiconductor device with little damage to the semiconductor chip can be obtained.

  A method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described below with reference to FIG.

  FIG. 12 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 400 according to the fourth embodiment of the present invention. The method of forming the first through hole in the first semiconductor chip 80 and the second through hole in the second semiconductor chip 81 is the same as that in the first embodiment, and thus the description thereof is omitted.

  First, as shown in FIG. 12A, the first through holes 80b and 801b of the first semiconductor chip 80 and the connection portion of the wiring pattern 810a formed at a predetermined position of the wiring substrate 810 are aligned and mounted. To do. Here, the wiring pattern 810a is formed, for example, by screen printing of a conductive paste or etching of a copper foil.

  Next, as shown in FIG. 12B, a wiring board and a first semiconductor mounted on a stage (not shown) in a photocurable conductive resin liquid 92 filled in a container (not shown). The chip 80 is immersed. At this time, the photocurable conductive resin liquid 92 is immersed so that the liquid level of the first semiconductor chip 80 is about one surface 800a, and the photocurable conductive resin liquid 92 is placed in the first through holes 80b and 801b. Fill. Then, the opening 91a of the liquid crystal mask 91 is arranged to face the first through holes 80b and 801b.

  Next, as shown in FIG. 12C, the photocurable conductive resin in the first through holes 80b and 801b is irradiated with, for example, ultraviolet light or visible light through the opening 91a of the liquid crystal mask 91. The liquid 92 is photocured to form first conductive vias 80d and 801d having conductive resins 80c and 801c. As a result, the first semiconductor chip 80 and the wiring substrate 810 are mounted, and the connecting portions of the first conductive vias 80d and 801d and the wiring pattern 810a are electrically connected.

  Next, as shown in FIG. 12D, the stage is moved downward, and the first semiconductor chip 80 is further immersed from the liquid surface of the photocurable conductive resin liquid 92 to a predetermined depth. Here, the predetermined depth is about the thickness of the conductive connector.

  Next, as shown in FIG. 12E, the shape of the opening 91a of the liquid crystal mask 91 is controlled to expose the photocurable conductive resin liquid 92 in a predetermined shape and a predetermined region. As a result, the conductive connection bodies 82 and 821 are formed integrally with the first conductive vias 80d and 801d, respectively.

  Next, as shown in FIG. 12 (f), the stage is further moved downward, and the second semiconductor chip 81 mounted in alignment with the first semiconductor chip 80 is immersed in the photocurable conductive resin liquid 92. To do. At this time, the second through hole 81b is aligned with the conductive connecting body 82, and the second through hole 811b is aligned with the conductive connecting body 821.

  Then, the photocurable conductive resin filled in the second through holes 81b and 811b through the openings 91a of the liquid crystal mask 91 opened corresponding to the second through holes 81b and 811b of the second semiconductor chip 81. The liquid 92 is exposed.

  Next, as shown in FIG. 12G, the photocurable conductive resin liquid is photocured to form second conductive vias 81d and 811d. Thereby, the conductive connection bodies 82 and 821 formed on the first semiconductor chip 80 and the second conductive vias 81d and 811d of the second semiconductor chip 81 are electrically connected, and a semiconductor device is manufactured.

  Then, the produced semiconductor device is taken out from the container, and the surrounding uncured photocurable conductive resin is removed. Thereby, the semiconductor device 400 in which the first semiconductor chip 80 and the second semiconductor chip 81 are formed on the wiring substrate 810 is manufactured.

  According to the present embodiment, since the wiring board and the semiconductor laminated structure can be connected with the photocurable conductive resin, a semiconductor device having excellent reliability with less damage to the semiconductor chip or the like by mounting under a low load. Easy to produce.

  In the above-described embodiment, the example in which the wiring pattern of the wiring board is formed by screen printing of the conductive paste has been described. However, the present invention is not limited to this. For example, it may be formed on a glass epoxy substrate using an optical modeling method. Thereby, since integrated production by stereolithography is possible, productivity can be improved. In addition, since the wiring pattern and the conductive via can be made of the same material, a semiconductor device having no connection interface and excellent adhesion strength can be realized.

  In the above embodiment, the example in which the conductive via is directly formed in the connection portion of the wiring pattern has been described. However, the present invention is not limited to this, and a connection electrode such as a bump may be formed. Thereby, the contact area of the conductive via can be enlarged by the connection electrode, and the adhesion strength can be improved.

(Fifth embodiment)
Below, the manufacturing method of the semiconductor laminated structure and semiconductor device in the 5th Embodiment of this invention is demonstrated using FIG.

  FIG. 13 is a cross-sectional view for explaining the method for manufacturing the semiconductor multilayer structure 950 and the semiconductor device 960 in the fifth embodiment of the present invention.

  In the present embodiment, each of the above embodiments is provided in that the wiring substrate having the connection electrodes, the first semiconductor chip member, and the second semiconductor chip member are individually manufactured, and the semiconductor multilayer structure and the semiconductor device are collectively formed. Different from form.

  First, as shown in FIG. 13A, a wiring pattern 900b is formed by bonding and etching, for example, a copper foil or the like on one surface of a substrate 900a made of, for example, a glass epoxy substrate. Further, the connection substrate 901 is formed at a predetermined position of the wiring pattern 900b by using, for example, solder or conductive resin, so that the wiring substrate 900 is manufactured. Note that the wiring pattern 900b and the connection electrode 901 may be formed by screen printing of a conductive paste or may be formed by using the optical modeling method described in each of the above embodiments.

  Then, as shown in FIG. 13B, a first conductive via 916 is formed by filling the first through hole 912 of the first semiconductor chip 910 with a conductive resin 914. Thereafter, in a state where the conductive resin 914 is semi-cured, the conductive connecting body 918 having the sharp convex portion 918a is formed by using an optical modeling method, and the first semiconductor chip member 920 is manufactured.

  Further, as shown in FIG. 13C, the second through hole 932 of the second semiconductor chip 930 is filled with the conductive resin 934 to form the second conductive via 936. Thereafter, the conductive resin 914 is semi-cured to form the second semiconductor chip member 940.

  The wiring board 900, the first semiconductor chip member 920, and the second semiconductor chip member 940 are individually prepared according to FIGS.

  Next, as shown in FIG. 13 (d), the connection electrode 901 of the wiring substrate 900, the first conductive via 916 of the first semiconductor chip member 920, and the convex portion 918 a of the conductive connection body 918 of the first semiconductor chip member 920. And the second conductive via 936 of the second semiconductor chip member 940 are aligned and arranged. And it laminates, pressing and heating from the arrow direction in drawing.

  As described above, a semiconductor device 960 in which each semiconductor chip as shown in FIG. In this case, a semiconductor multilayer structure 950 can be obtained by stacking without the wiring substrate 900.

  According to the present embodiment, since individually manufactured members can be configured in an optimal combination, a semiconductor multilayer structure and a semiconductor device with a high degree of design freedom can be manufactured with high productivity.

  In addition, according to the present embodiment, since the concave portion due to the curing shrinkage of the conductive resin can be reliably connected by embedding or pushing in the conductive connection body, the semiconductor laminated structure having low connection resistance and excellent connection reliability. And a semiconductor device is obtained.

  In each of the above embodiments, an example in which two semiconductor chips are stacked as the semiconductor stacked structure has been described. However, the present invention is not limited to this. For example, a semiconductor stacked structure may be manufactured by stacking three or more semiconductor chips. As a result, it is possible to realize a semiconductor stacked structure and a semiconductor device with a further increased mounting density.

  In each of the above-described embodiments, an example in which the gap between the stacked semiconductor chips and the wiring board is a space is described. However, the present invention is not limited to this, and sealing may be performed with an insulating adhesive. As a result, the mechanical strength of the semiconductor laminated structure and the semiconductor device can be increased, and the connection reliability between the connection electrodes and the breakage due to deformation can be prevented.

  According to the semiconductor laminated structure of the present invention, the semiconductor device using the same, and the manufacturing method thereof, thin and high-density mounting can be easily performed through the conductive resin. Therefore, it is useful in technical fields such as portable digital devices such as mobile phones and digital cameras, notebook personal computers, and digital home appliances, which are small and require high storage capacity and high reliability.

(A) Plan view showing the configuration of the semiconductor multilayer structure according to the first embodiment of the present invention (b) AA line sectional view of FIG. 1 (a) (c) First embodiment of the present invention Sectional drawing which shows the structure of the semiconductor device which mounted the semiconductor laminated structure in Sectional conceptual diagram which shows another example of the electroconductive connection body used for the semiconductor laminated structure in the 1st Embodiment of this invention Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device of the 1st Embodiment of this invention Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device of the 1st Embodiment of this invention Sectional drawing explaining the manufacturing method of the electroconductive connection body used for the 1st Embodiment of this invention (A) Plan view showing the configuration of the semiconductor multilayer structure according to the second embodiment of the present invention (b) Cross-sectional view taken along the line AA in FIG. 6 (a) (c) Second embodiment of the present invention Sectional drawing which shows the structure of the semiconductor device which mounted the semiconductor laminated structure in Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device of the 2nd Embodiment of this invention Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device of the 2nd Embodiment of this invention (A) Plan view showing a configuration of a semiconductor laminated structure according to the third embodiment of the present invention (b) AA line sectional view of FIG. 9 (a) (c) Third embodiment of the present invention Sectional drawing which shows the structure of the semiconductor device which mounted the semiconductor laminated structure in Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device of the 3rd Embodiment of this invention (A) Plan view showing a configuration of a semiconductor device according to the fourth embodiment of the present invention (b) AA line sectional view of FIG. 11 (a) Sectional drawing explaining the manufacturing method of the semiconductor device of the 4th Embodiment of this invention Sectional drawing explaining the manufacturing method of the semiconductor laminated structure and semiconductor device in the 5th Embodiment of this invention

Explanation of symbols

1, 2, 3, 4, 950 Semiconductor multilayer structure 10, 80, 910 First semiconductor chip 10a Silicon substrate 10b, 80b, 801b, 912 First through hole 10c, 11c, 70c, 71c, 80c, 81c, 801c, 914, 934 Conductive resin 10d, 80d, 801d, 916 First conductive via 11, 81, 930 Second semiconductor chip 11b, 81b, 811b, 932 Second through hole 11d, 81d, 811d, 936 Second conductive via 12, 52, 72, 82, 121, 122, 123, 821, 918 Conductive connector 12a, 121a, 122a, 123a Individual member 12b, 121b, 122b, 123b Protrusion 13 Recess 41, 61, 91 Liquid crystal mask 41a, 61a, 91a, 102 opening 42,62,92 photocurable conductive resin liquid 3, 60 Container 44, 64 Stage 52b, 918a Protrusion 100, 200, 300, 400, 960 Semiconductor device 100a, 800a One surface 100b The other surface 101 Etching pattern mask 103 Conductive resin paste 104 Squeegee 110, 810, 900 Wiring substrate 110a, 810a, 900b Wiring pattern 113,901 Connection electrode 900a Substrate 920 First semiconductor chip member 940 Second semiconductor chip member

Claims (15)

A semiconductor laminated structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are laminated,
A first semiconductor chip having a first conductive via which is connected to the second semiconductor chip in a stacking direction and filled with a conductive resin connected to the predetermined first wiring electrode;
A second semiconductor chip having a second conductive via connected to the first semiconductor chip in the stacking direction and filled with a conductive resin connected to the predetermined second wiring electrode;
The semiconductor laminated structure, wherein the opposing first conductive via and the second conductive via are electrically connected via a conductive connector. The semiconductor laminated structure according to claim 1, wherein the conductive connection body is made of an individual member having a plurality of protrusions. 3. The semiconductor multilayer structure according to claim 2, wherein the individual member is configured by metal plating the outer periphery of a cured conductive resin or a cured insulating resin. The said individual member is comprised by metal-plating the outer periphery to the photocurable conductive resin hardened | cured material or photocurable insulating resin hardened | cured material formed by the stereolithography. The semiconductor laminated structure. 3. The semiconductor according to claim 1, wherein a volume of the conductive connection body is larger than a space volume of the first conductive via and the second conductive via that is hardened and contracted by the conductive resin. Laminated structure. The semiconductor laminated structure according to claim 1, wherein the conductive connection body is made of a photocurable conductive resin cured product formed by an optical modeling method having at least one convex portion. 7. The semiconductor according to claim 6, wherein the volume of at least the convex portion of the conductive connection body is larger than a space volume of the first conductive via and the second conductive via that is cured and contracted by the conductive resin. Laminated structure. The semiconductor laminated structure according to claim 1, wherein the conductive resin and the conductive connector are made of a photocurable conductive resin integrally formed by an optical modeling method. The semiconductor multilayer structure according to claim 1 is mounted on a wiring board, and is electrically connected to a connection electrode of the wiring board via the first conductive via. A featured semiconductor device. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
Forming a first through-hole in the first semiconductor chip connected to the second semiconductor chip in the stacking direction and connected to the predetermined first wiring electrode;
Forming a second through hole connected to the second semiconductor chip in a stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode;
A conductive via forming step of filling the first through hole and the second through hole with a conductive resin paste to form a first conductive via in the first semiconductor chip and a second conductive via in the second semiconductor chip;
A conductive connector forming step for forming a conductive connector;
A conductive connector arrangement step of arranging the conductive connector in the first conductive via or the second conductive via on at least one surface of the first semiconductor chip or the second semiconductor chip;
The first conductive vias of the predetermined first semiconductor chip and the second conductive vias of the second semiconductor chip are aligned, and the first conductive vias and the second conductive vias are attached to each other. A semiconductor chip stacking step for electrically connecting two conductive vias;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. In the conductive connector forming step, a photocurable conductive resin liquid or a photocurable insulating resin liquid is exposed and developed into a predetermined shape by an optical modeling method using a liquid crystal mask or a laser beam, and an unexposed portion is formed. The method includes a step of removing and forming a conductive connection body of a cured photocurable conductive resin or a conductive connection body in which the outer periphery of the formed cured photocurable insulating resin is metal-plated. 10. A method for producing a semiconductor laminated structure according to 10. The steps after the conductive via forming step are:
The conductive connection body having at least one protrusion is formed by stereolithography at a position connected to the first conductive via of the first semiconductor chip and facing the second conductive via of the second semiconductor chip. A conductive connecting body forming step,
The convex portion of the predetermined conductive connection body and the second conductive via of the second semiconductor chip are aligned, and the first conductive via and the second conductive via are electrically connected via the conductive connection body. Semiconductor chip stacking process to be connected to each other,
The manufacturing method of the semiconductor laminated structure of Claim 10 characterized by the above-mentioned. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
Forming a first through-hole in the first semiconductor chip connected to the second semiconductor chip in the stacking direction and connected to the predetermined first wiring electrode;
Forming a second through hole connected to the second semiconductor chip in a stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode;
The first semiconductor chip is immersed in a photocurable conductive resin liquid, the photocurable conductive resin in the first through hole is photocured to form a first conductive via, and the first conductive Forming a conductive connection connected to the via;
Further, the second semiconductor chip is immersed in the photocurable conductive resin liquid, aligned with the second through hole corresponding to the conductive connector, and the photocurable property in the second through hole. A semiconductor chip stacking step in which a conductive resin is photocured to form a second conductive via, and the first conductive via and the second conductive via are electrically connected via a conductive connector;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
The first semiconductor chip is filled with a conductive resin paste in a first through-hole connected to the first semiconductor chip in the stacking direction with the second semiconductor chip and connected to the predetermined first wiring electrode. A first semiconductor chip forming step of forming a via and forming a conductive connection body having at least one convex portion connected to the first conductive via by an optical modeling method;
The second semiconductor chip is filled with a conductive resin paste in a second through-hole connected to the second semiconductor chip in the stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode. A second semiconductor chip forming step of forming vias;
The convex portion of the conductive connection body of the first semiconductor chip is aligned with the second conductive via of the second semiconductor chip, and the first conductive via and the second are interposed via the conductive connection body. A semiconductor chip stacking step for electrically connecting conductive vias;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. 15. A semiconductor device, wherein the semiconductor multilayer structure formed by the method for manufacturing a semiconductor multilayer structure according to claim 10 is mounted in connection with a connection electrode of a wiring board. Manufacturing method.

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