JP2009004593A5 - - Google Patents

Claims (14)

A semiconductor laminated structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are laminated,
A first semiconductor chip having a first conductive via which is connected to the second semiconductor chip in a stacking direction and filled with a conductive resin connected to the predetermined first wiring electrode;
A second semiconductor chip having a second conductive via connected to the first semiconductor chip in the stacking direction and filled with a conductive resin connected to the predetermined second wiring electrode;
The semiconductor laminated structure, wherein the first conductive via and the second conductive via facing each other are electrically connected via a conductive connecting member made of an individual member having a plurality of protrusions . 2. The semiconductor multilayer structure according to claim 1 , wherein the individual member is configured by metal plating the outer periphery of a cured conductive resin or a cured cured resin. The individual members, according to claim 1, characterized in that it is constituted by metal plating the outer peripheral photocurable conductive resin cured product or photocurable insulating resin cured product formed by stereolithography The semiconductor laminated structure. The volume of the said electroconductive connection body is larger than the space volume which the said conductive resin of the said 1st conductive via and the said 2nd conductive via shrinkage | contracted , It is any one of Claim 1 to 3 characterized by the above-mentioned. The semiconductor laminated structure as described. The semiconductor laminated structure according to claim 1, wherein the conductive connection body is made of a cured photocurable conductive resin formed by an optical modeling method. Body volume of the conductive connection member is any one of claims 1-5, wherein greater than pore volume cured shrinkage of the conductive resin of the first conductive via and the second conductive via A semiconductor multilayer structure according to 1. The semiconductor laminate according to any one of claims 1 to 6, wherein the conductive resin and the conductive connector are made of a photocurable conductive resin integrally formed by an optical modeling method. Structure. The semiconductor multilayer structure as claimed in any one of claims 7 mounted on the wiring board, that are electrically connected via the connection electrode of the wiring substrate first conductive via A featured semiconductor device. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
Forming a first through-hole in the first semiconductor chip connected to the second semiconductor chip in the stacking direction and connected to the predetermined first wiring electrode;
Forming a second through hole connected to the second semiconductor chip in a stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode;
A conductive via forming step of filling the first through hole and the second through hole with a conductive resin paste to form a first conductive via in the first semiconductor chip and a second conductive via in the second semiconductor chip;
A conductive connector forming step of forming a conductive connector composed of individual members having a plurality of protrusions ;
A conductive connector arrangement step of arranging the conductive connector in the first conductive via or the second conductive via on at least one surface of the first semiconductor chip or the second semiconductor chip; and the predetermined first The first conductive via of the first semiconductor chip is aligned with the second conductive via of the second semiconductor chip, and the first conductive via and the second conductive via are connected via the conductive connection body attached thereto. A semiconductor chip stacking process for electrical connection;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. In the conductive connector forming step, a photocurable conductive resin liquid or a photocurable insulating resin liquid is exposed and developed into a predetermined shape by an optical modeling method using a liquid crystal mask or a laser beam, and an unexposed portion is formed. The method includes a step of removing and forming a conductive connection body of a cured photocurable conductive resin or a conductive connection body in which the outer periphery of the formed cured photocurable insulating resin is metal-plated. A method for producing a semiconductor laminated structure according to claim 9 . The steps after the conductive via forming step are:
The conductive connection body having at least one protrusion is formed by stereolithography at a position connected to the first conductive via of the first semiconductor chip and facing the second conductive via of the second semiconductor chip. A conductive connecting body forming step,
The convex portion of the predetermined conductive connection body and the second conductive via of the second semiconductor chip are aligned, and the first conductive via and the second conductive via are electrically connected via the conductive connection body. Semiconductor chip stacking process to be connected to each other,
The method of manufacturing a semiconductor stacked structure according to claim 9, characterized in that it comprises a. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
Forming a first through-hole in the first semiconductor chip connected to the second semiconductor chip in the stacking direction and connected to the predetermined first wiring electrode;
Forming a second through hole connected to the second semiconductor chip in a stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode;
The first semiconductor chip is immersed in a photocurable conductive resin liquid, the photocurable conductive resin in the first through hole is photocured to form a first conductive via, and the first conductive forming a conductive connecting member comprising a discrete member having a plurality of projections which are connected to the via,
Further, the second semiconductor chip is immersed in the photocurable conductive resin liquid, aligned with the second through hole corresponding to the conductive connector, and the photocurable property in the second through hole. A semiconductor chip stacking step in which a conductive resin is photocured to form a second conductive via, and the first conductive via and the second conductive via are electrically connected via a conductive connector;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. A method for manufacturing a semiconductor stacked structure in which a first semiconductor chip having at least a first wiring electrode and a second semiconductor chip having a second wiring electrode are stacked,
The first semiconductor chip is filled with a conductive resin paste in a first through-hole connected to the first semiconductor chip in the stacking direction with the second semiconductor chip and connected to the predetermined first wiring electrode. A first semiconductor chip forming step of forming a via and forming a conductive connection body made of an individual member having a plurality of protrusions connected to the first conductive via by an optical modeling method;
The second semiconductor chip is filled with a conductive resin paste in a second through-hole connected to the second semiconductor chip in the stacking direction with the first semiconductor chip and connected to the predetermined second wiring electrode. A second semiconductor chip forming step of forming vias;
The convex portion of the conductive connection body of the first semiconductor chip is aligned with the second conductive via of the second semiconductor chip, and the first conductive via and the second are interposed via the conductive connection body. A semiconductor chip stacking step for electrically connecting conductive vias;
The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. The semiconductor device characterized by claim 9 of the semiconductor layered structure formed by the method of manufacturing a semiconductor stacked structure according to any one of claims 13, implemented by connecting the connection electrodes of the wiring substrate Manufacturing method.