JP2006165073A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily realize the stacking of semiconductor chips in a semiconductor device. <P>SOLUTION: Each of two silicon chips includes pluralities of surface and rear surface electrodes connected via conductive paste 8 disposed in through holes 1c, 2c. The plurality of the surface 1a, 2a electrodes include electrodes connected, via coupling wirings 1g, 2g, to a plurality of adjacent electrodes. Fuse elements 1k, 2k capable of cutting the coupling wirings 1g, 2g are connected to the coupling wirings 1g, 2g. Further, in a plurality of signal wirings 1h, 2h possessed by each silicon chip, paths of the wirings 1h, 2h are selected by cutting the fuse elements 1k, 2k of the coupling wirings 1g, 2g connected with the wirings 1h, 2h. It is hereby possible to select connections for every superimposed silicon chip layers and hence to facilitate stacking of silicon chips (semiconductor chips) upon stacking and packaging a plurality of silicon chips. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to a high-density mounting technique by chip stacking.

Grooves are formed in the sidewalls of each semiconductor chip, conductive films connected to the electrode pads are formed in the respective grooves via insulating films, and wire bonding is performed on the grooves in each semiconductor chip. The land of the substrate and each conductive film are connected by wires (see, for example, Patent Document 1).
Japanese Patent Laying-Open No. 2004-281819 (FIG. 3)

  A through-hole is formed in the surface electrode of a silicon substrate (semiconductor wafer or semiconductor chip), plating or conductive resin is disposed in the through-hole, and the surface electrode and the back electrode are electrically connected. A technique called a silicon interposer that is used as an interposer has been studied.

  That is, in the silicon interposer, electrodes are provided on the front and back surfaces of the chip, and the silicon chips can be stacked by electrically connecting the electrodes on the front and back surfaces.

  As a result of studying the lamination of the silicon interposer, the present inventor has found the following problems.

  For example, when a large-capacity memory is formed by stacking a plurality of the same memory chips such as a DRAM (Dynamic Random Access Memory), a connection portion using a through hole in the bonding pad is provided on the front and back surfaces. The common portion can be connected by a connection portion at the same position between the upper and lower chips, but it is not easy to connect between pads that are desired to be divided for each chip, such as a signal pad.

  In this case, if the pad position of a signal to be taken out is changed for each chip to be stacked, the problem is that the cost increases from the viewpoint of wiring routing and also from the viewpoint of manufacturing a semiconductor wafer.

  An object of the present invention is to provide a technique capable of easily realizing stacking of semiconductor chips.

  Another object of the present invention is to provide a technique capable of reducing the cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connection wirings. A first silicon chip including an electrically connected electrode, and a fuse element electrically connected to the connecting wire connected to the connecting wire; and on the first silicon chip. It has a plurality of electrodes on the front and back surfaces that are stacked and electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connecting wires A second silicon chip including an electrically connected electrode, and a fuse element capable of electrically disconnecting the connecting wire connected to the connecting wire, and electrically connected to the first silicon chip Wiring board to be used and before The connection wiring having a plurality of external terminals provided on the wiring substrate and connected to the wiring in at least one of the plurality of signal wirings formed on the first or second silicon chip The fuse element is electrically cut to select the wiring path.

  Furthermore, the present invention has a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connection wirings. And a fuse element that is capable of electrically disconnecting the connection wiring is connected to the connection wiring, and at least one of the plurality of signal wirings is connected to the connection wiring. In the wiring, a step of preparing the first and second silicon chips in which the fuse element of the connection wiring connected to the wiring is electrically cut to select the wiring path; and wiring the first silicon chip A step of electrically connecting and mounting on the substrate; and a step of electrically connecting and laminating the second silicon chip on the first silicon chip.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Each of the plurality of silicon chips has a plurality of electrodes on the front and back surfaces that are electrically connected to each other via a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes And a fuse element that can cut the connection wiring is connected to the connection wiring, and at least one of a plurality of signal wirings included in the silicon chip is connected to the connection wiring. In one wiring, the fuse element of the connection wiring connected to the wiring is cut and the path of the wiring is selected. The connection can be selected after chip separation, and stacking of silicon chips can be facilitated.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a plan view showing an example of the structure of a silicon interposer incorporated in a semiconductor device according to an embodiment of the present invention, FIG. 2 is a partially enlarged plan view showing an A portion shown in FIG. 1, and FIG. 4 is a cross-sectional view showing an example of the structure of the silicon interposer shown in FIG. 4, FIG. 4 is a cross-sectional view showing an example of the structure in which bump electrodes are attached to the silicon interposer shown in FIG. 3, and FIG. 5 is a structure in which the silicon interposer shown in FIG. FIG. 6 is a sectional view showing an example of the structure of the semiconductor device according to the embodiment of the present invention. FIG. 7 is an enlarged partial plan view showing an example of the structure of the electrode on the surface of the silicon interposer shown in FIG. 8 is an enlarged partial cross-sectional view showing an example of the detailed structure of the silicon interposer shown in FIG. 4, and FIG. 9 is an enlarged view showing an example of the assembly procedure of the structure in which the interposers shown in FIG. FIG. 10 is an enlarged partial plan view showing an example of the structure of the electrode on the surface of the silicon interposer laminated in four stages shown in FIG. 11, and FIG. 11 shows an example of the structure in which the interposer shown in FIG. 8 is laminated in four stages. FIG. 12 and FIG. 13 are enlarged partial plan views showing modifications of the structure of the electrodes on the surface of the silicon interposer incorporated in the semiconductor device according to the embodiment of the present invention. FIG. FIG. 15 and FIG. 16 are enlarged partial cross-sectional views showing modifications of the structure of the silicon interposer incorporated in the semiconductor device according to the embodiment of the present invention, respectively. FIG. 17, FIG. 17 and FIG. 18 each show a modification of the structure of the silicon interposer incorporated in the semiconductor device according to the embodiment of the present invention. It is a partial cross-sectional view and enlarged partial cross-sectional view illustrating.

  In the semiconductor device of this embodiment, a plurality of through holes are formed in a silicon substrate, a plating film or a conductive resin is disposed in the through holes, and a plurality of wiring portions for connecting electrodes on both the front and back surfaces are formed. A structure in which a plurality of silicon chips formed in this way are stacked as interposers (also referred to as silicon interposers).

  1 to 3 show the structure of a first silicon chip 1 which is an example of the silicon interposer. The first silicon chip 1 has a plurality of electrodes electrically connected to each other on the front surface (main surface) 1a and the back surface 1b through a conductive paste 8 which is a conductor portion disposed in a through hole (through hole) 1c. is doing. Among the plurality of electrodes, the plurality of electrodes on the surface 1a include a laminating pad 1e, which is an electrode electrically connected to a plurality of adjacent electrodes via a connection wiring 1g, as shown in FIG. It is out. The plurality of electrodes on the surface 1a include a main pad 1j as shown in FIG. 7 which is an electrode connected to an I / O buffer or the like via a wiring 1h in addition to the lamination pad 1e.

  For example, FIG. 7 and FIG. 8 show the main part of the structure in which the signal main pad 1j is connected to both sides of the stacking pad 1e on the surface 1a of the first silicon chip 1 via the connecting wiring 1g. ing. Here, the main pad 1j is connected to the I / O buffer via the wiring 1h.

  Further, in the silicon interposer (first silicon chip 1) incorporated in the semiconductor device of the present embodiment, as shown in FIG. 8 as a cutting means capable of electrically cutting the connection wiring 1g. A fuse element 1k is connected. That is, the fuse element 1k is connected to the connecting wiring 1g connecting the stacking pads 1e or between the stacking pads 1e and the main pad 1j as a cutting means capable of electrically disconnecting the connecting wiring 1g.

  Furthermore, a plurality of metal electrodes 1f are formed on the back surface 1b of the first silicon chip 1 and electrically connected to the stacking pad 1e on the front surface 1a through the conductive paste 8 in the through hole 1c. An SiO2 film 1d is formed as an insulating film on the inner wall of the through hole 1c, and a conductive paste 8 is buried in a hole surrounded by the SiO2 film 1d.

  Further, the surface 1a of the first silicon chip 1 is covered with a protective film 1i called a passivation film except for the main pad 1j and the lamination pad 1e.

  The through-hole 1c in which the conductive paste 8 is embedded, the fuse element 1k connected to the connection wiring 1g, the stacking pad 1e and the metal electrode 1f are the wiring 1h, the connection wiring 1g, the main pad 1j, and the protective film 1i. In the same manner as described above, it is formed in a wiring forming process, that is, a pre-process in a semiconductor wafer which is a silicon substrate.

  The semiconductor device of the present embodiment is formed by stacking the silicon interposers formed as described above. Here, as an example, a BGA (Ball Grid Array) 13 shown in FIG. 6 will be described.

  The BGA 13 shown in FIG. 6 has a first silicon chip 1, a second silicon chip 2, a third silicon chip 3, and a fourth silicon chip 4 that are silicon interposers stacked on a surface 5a of a package substrate 5 that is a wiring substrate. It is a thing.

  That is, the first silicon chip 1 electrically connected to the surface 5 a of the package substrate 5 via the solder bumps (bump electrodes) 6 shown in FIG. 4 and the solder bumps 6 on the first silicon chip 1 Second silicon chip 2 electrically connected to each other, third silicon chip 3 electrically connected to second silicon chip 2 via solder bump 6, and solder bump 6 on third silicon chip 3. The fourth silicon chip 4 is electrically connected through the first and second electrodes.

  Further, as shown in FIG. 5, ball electrodes 7, which are a plurality of external terminals made of solder or the like, are attached to the back surface 5 b of the package substrate 5, for example, arranged in a lattice pattern. The package substrate 5 is formed with wiring portions for transmitting signals from the respective silicon chips to a plurality of ball electrodes 7 which are external terminals arranged in a lattice pattern. The package substrate 5 may be a resin substrate such as an epoxy substrate, or a flexible wiring substrate. Alternatively, a silicon substrate or the like may be used.

  In the BGA 13, the fuse element 1k of the connecting wiring 1g connected to the wiring 1h in any of the wirings 1h of the plurality of signal wirings 1h formed on the first silicon chip 1 is shown in FIG. As shown, the path of the wiring 1h is selected by being electrically cut. The same applies to the second silicon chip 2, the third silicon chip 3, and the fourth silicon chip 4.

  The fuse element 1k is electrically cut in this way after the manufacturing process of the previous process on the semiconductor wafer is completed, after the semiconductor chip is separated into pieces by dicing, and the assembly of the BGA 13 is started. It is preferable to be performed in the meantime.

  Thereby, in the BGA 13, by selectively cutting the fuse element 1k in advance in each silicon chip, the connection wiring 1g connected to the lamination pad 1e is cut according to each design specification to be laminated. Since the silicon chips are stacked in a state where the path of the wiring 1h connected to the pad 1e has been selected, it is possible to easily stack the chips.

  Note that, on the surface 5 a of the package substrate 5, as shown in FIG. 6, each silicon chip is resin-sealed with a sealing body 10. The sealing body 10 is made of a sealing resin such as an epoxy resin, for example.

  Further, the size of the silicon chip (silicon interposer) mounted on the BGA 13 is such that one side of the main surface (surface 1a) is, for example, a square having a size of about 2 to 5 mm, and further, the laminating pad 1e and the main pad The pad size such as 1j is a square having a side of, for example, about 110 to 130 μm, and the bump electrode such as the solder bump 6 has a diameter of, for example, about several tens to 100 μm. However, the size of these members is not limited to the numerical values described here.

  Next, a method for manufacturing the semiconductor device (BGA 13) of the present embodiment will be described.

  Here, as shown in FIG. 9, a case where silicon chips as silicon interposers are stacked in two stages will be described.

  First, a first silicon chip 1 and a second silicon chip 2 that are silicon interposers are prepared. The first silicon chip 1 and the second silicon chip 2 may be the same chip or different chips. However, fuse elements 1k and 2k are connected in advance to the connection wirings 1g and 2g of the first silicon chip 1 and the second silicon chip 2, respectively.

  Thereafter, in each of the first silicon chip 1 and the second silicon chip 2, connection wirings 1g and 2g connected to the wirings 1h and 2h, respectively, with respect to the plurality of signal wirings 1h and 2h formed on the respective silicon chips. The fuse elements 1k and 2k are electrically cut according to the design specifications, and the paths of the wirings 1h and 2h are selected and determined.

  The second silicon chip 2 has the same structure as the first silicon chip 1. In other words, the second silicon chip 2 has a plurality of electrodes electrically connected via the conductive paste 8 which is a conductor portion disposed in the through hole (through hole) 2c, on the front surface (main surface) 2a and the back surface 2b. Have. Further, among the plurality of electrodes, the plurality of electrodes on the surface 2a include a stacking pad 2e which is an electrode electrically connected to a plurality of adjacent electrodes via a connection wiring 2g. The plurality of electrodes on the surface 2a include a main pad 2j which is an electrode connected to an I / O buffer or the like via the wiring 2h in addition to the lamination pad 2e.

  A plurality of metal electrodes 2f are formed on the back surface 2b of the second silicon chip 2 and electrically connected to the lamination pads 2e on the front surface 2a through the conductive paste 8 in the through hole 2c. Further, an SiO2 film 2d is formed as an insulating film on the inner wall of the through hole 2c, and the conductive paste 8 is embedded in the hole surrounded by the SiO2 film 2d. Further, the surface 2a of the second silicon chip 2 is covered with a protective film 2i called a passivation film except for the main pad 2j and the lamination pad 2e.

  In addition, as means for electrically disconnecting the connection wirings 1g and 2g, the fuse elements 1k and 2k may be disconnected without using the fuse elements 1k and 2k. In that case, it is not necessary to connect the fuse elements 1k and 2k to the connecting wires 1g and 2g in advance.

  Also, the first silicon chip 1 and the second silicon chip 2 in which the fuse elements 1k and 2k are electrically cut in accordance with the design specifications and the paths of the wirings 1h and 2h are selected are prepared in advance. The assembly of the BGA 13 may be started using the silicon chip 1 and the second silicon chip 2.

  Thereafter, solder bumps 6 as bump electrodes are attached to the metal electrode 1f on the back surface 1b of the first silicon chip 1 and the metal electrode 2f on the back surface 2b of the second silicon chip 2, respectively.

  Thereafter, a resin material for the underfill 9 is applied on the surface 5a of the package substrate 5, the first silicon chip 1 is disposed thereon, and heat treatment is performed to bond the package substrate 5 and the first silicon chip 1 to the solder bumps 6. Electrical connection through

  Thereafter, a resin material for the underfill 9 is applied on the first silicon chip 1, the second silicon chip 2 is disposed on the first silicon chip 1, and heat treatment is performed to solder the first silicon chip 1 and the second silicon chip 2 to solder bumps. 6 is electrically connected.

  That is, the second silicon chip 2 is electrically connected and stacked on the first silicon chip 1 via the solder bumps 6.

  Thereafter, the ball electrode 7 as a plurality of external terminals is attached to the back surface 5b of the package substrate 5, and the assembly of the BGA 13 is completed.

  Note that the final signal transmission path between the desired I / O buffer and the ball electrode 7 as the external terminal is the path indicated by the arrow indicated by the signal T.

  Next, FIGS. 10 and 11 show the BGA 14 in the case where the silicon chips (first silicon chip 1, second silicon chip 2, third silicon chip 3 and fourth silicon chip 4) which are four silicon interposers are stacked. The structure is shown.

  FIG. 10 shows the connection state of the lamination pads 4e on the surface 4a of the uppermost fourth silicon chip 4 by the connection wiring 4g. Each lamination pad 4e is formed with a through hole 4c in which a conductive paste 8 is embedded. Further, a metal electrode 4f electrically connected to the lamination pad 4e is formed on the back surface 4b side of each lamination pad 4e.

  In the BGA 14 shown in FIG. 11, the input signal A corresponds to the output signal A, the input signal B corresponds to the output signal B, the input signal C corresponds to the output signal C, and the input signal D corresponds to the output signal D, respectively. Yes. Each input signal is connected to an I / O buffer.

  Also in the BGA 14, each desired connection wiring 1g, 2g, 3g is cut according to the design specification, and the signal wiring is selected.

  The presence or absence of electrical connection between the layers of each silicon chip is selected depending on whether or not the solder bumps 6 as bump electrodes are disposed between the layers. That is, in a case where electrical connection between layers is not performed at a predetermined electrode of the silicon chip, only the resin of the underfill 9 is embedded between the mutual electrodes. The electrodes can be insulated.

  Next, FIG. 12 and FIG. 13 each show a modified example of the connection state of the pads. As shown in FIG. 12, three main pads 1j are arranged around the lamination pad 1e via the connection wiring 1g. Alternatively, as shown in FIG. 13, four main pads 1j may be connected to the periphery of the lamination pad 1e via connection wirings 1g. That is, the number of main pads 1j connected to one stacking pad 1e may be any number.

  14 and FIG. 15, the laminated conductors 1 e that were originally not connected in advance are arranged with the plate-like conductor member 15 on the adjacent laminated pad 1 e and applied by the probe 11. Then, both pads are connected.

  Further, in the modification shown in FIG. 16, the connection wiring 1g that has been cut once is repaired and reconnected, and the laminated pads 1e that have been cut once are similarly plate-like on the lamination pad 1e. By arranging the conductor member 15 and applying the probe 11, both pads can be connected by repair.

  In the modification shown in FIG. 17, the conductive paste 8 is not embedded in the through hole 1c, but a metal film 1m is formed on the SiO2 film 1d on the inner wall of the through hole 1c, as shown in FIG. The lamination pad 1e and the metal electrode 1f are connected.

  At this time, as shown in FIG. 18, the mask 12 is disposed on the pad and the photolithography process is performed only on the through hole 1c that is not desired to be electrically connected, as shown in FIG. It is also possible to prevent the formation of the metal film 1m and form the through hole 1c that does not electrically connect the front and back.

  Further, in the case of the structure shown in FIG. 8, as the conductive paste 8 embedded in the through hole 1c, for example, an epoxy resin-based paste material may be used, or an Ag filler-based paste material, etc. May be used. By adopting an Ag filler-based paste material as the conductive paste 8, the thermal conductivity of the conductive paste 8 can be increased, so that heat generated at the connecting portion can be diffused to improve heat dissipation. .

  According to the semiconductor device and the manufacturing method thereof of the present embodiment, a plurality of front and back surfaces in which a plurality of silicon chips (silicon interposers) are electrically connected via the conductive paste 8 disposed in the through hole 1c. The plurality of electrodes on the front surface include electrodes electrically connected to a plurality of adjacent electrodes via a connection wiring 1g, and the connection wiring 1g includes the connection wiring 1g. The fuse element 1k that can be cut is connected, and in the plurality of signal lines 1h that the silicon chip has, the fuse element 1k of the connection line 1g that is connected to the line 1h is cut to select the path of the line 1h. Therefore, when stacking and mounting multiple silicon chips, select the connection for each layer of silicon chips to be stacked after chip separation. It can, can facilitate lamination of the silicon chip (semiconductor chip).

  Therefore, it is not necessary to divide silicon chips to be stacked in the wafer manufacturing process, and chip stacking can be easily realized.

  As a result, the reliability of the semiconductor devices such as the BGA 13 and the BGA 14 can be increased, and the cost of the semiconductor device can be reduced.

  In addition, high-density mounting in the semiconductor device is possible, and application to portable electronic devices and the like can be facilitated.

  Although the invention made by the present inventor has been specifically described based on the embodiments of the invention, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the number of stacked silicon chips as the silicon interposer is two layers and the case where the number of stacked silicon chips is four has been described. .

  The present invention is suitable for an electronic device and a semiconductor manufacturing method.

It is a top view which shows an example of the structure of the silicon interposer integrated in the semiconductor device of embodiment of this invention. FIG. 2 is a partially enlarged plan view showing an A portion shown in FIG. 1 in an enlarged manner. It is sectional drawing which shows an example of the structure of the silicon interposer shown in FIG. It is sectional drawing which shows an example of the structure which attached the bump electrode to the silicon interposer shown in FIG. It is sectional drawing which shows an example of the structure which laminated | stacked the silicon interposer shown in FIG. It is sectional drawing which shows an example of the structure of the semiconductor device of embodiment of this invention. FIG. 9 is an enlarged partial plan view showing an example of a structure of electrodes on the surface of the silicon interposer shown in FIG. 8. FIG. 5 is an enlarged partial sectional view showing an example of a detailed structure of the silicon interposer shown in FIG. 4. FIG. 9 is an enlarged partial cross-sectional view showing an example of an assembly procedure of a structure in which the interposer shown in FIG. 8 is stacked in two stages. FIG. 12 is an enlarged partial plan view showing an example of a structure of electrodes on the surface of the silicon interposer stacked in four stages shown in FIG. 11. It is an expanded partial sectional view which shows an example of the structure which laminated | stacked the interposer shown in FIG. 8 in four steps. It is an enlarged partial top view which shows the modification of the structure of the electrode of the surface of the silicon interposer integrated in the semiconductor device of embodiment of this invention. It is an enlarged partial top view which shows the modification of the structure of the electrode of the surface of the silicon interposer integrated in the semiconductor device of embodiment of this invention. FIG. 16 is an enlarged partial plan view showing a structure of an electrode on the surface of the silicon interposer of the modification shown in FIG. 15. It is an expanded partial sectional view which shows the modification of the structure of the silicon interposer integrated in the semiconductor device of embodiment of this invention. It is an expanded partial sectional view which shows the modification of the structure of the silicon interposer integrated in the semiconductor device of embodiment of this invention. It is the fragmentary sectional view and enlarged partial sectional view which show the modification of the structure of the silicon interposer integrated in the semiconductor device of embodiment of this invention. It is the fragmentary sectional view and enlarged partial sectional view which show the modification of the structure of the silicon interposer integrated in the semiconductor device of embodiment of this invention.

Explanation of symbols

1 1st silicon chip 1a Front surface 1b Back surface 1c Through hole (through hole)
1d SiO2 film 1e Stacking pad (electrode)
1f metal electrode 1g connection wiring 1h wiring 1i protective film 1j main pad 1k fuse element 1m metal film 2 second silicon chip 2a front surface 2b back surface 2c through hole (through hole)
2d SiO2 film 2e Stack pad (electrode)
2f Metal electrode 2g Connection wiring 2h Wiring 2i Protective film 2j Main pad 2k Fuse element 3 Third silicon chip 3g Connection wiring 4 Fourth silicon chip 4a Front surface 4b Back surface 4c Through hole (through hole)
4e Stacking pad (electrode)
4f Metal electrode 4g Connection wiring 5 Package substrate (wiring substrate)
5a surface 5b back surface 6 solder bump (bump electrode)
7 Ball electrode (external terminal)
8 Conductive paste (conductor part)
9 Underfill 10 Encapsulant 11 Probe 12 Mask 13, 14 BGA (Semiconductor Device)
15 Plate-shaped conductor member

Claims (5)

Each has a plurality of electrodes on the front and back surfaces that are electrically connected via conductors arranged in the through-holes, and the plurality of electrodes on the front surface are electrically connected to adjacent electrodes through connection wirings. A first silicon chip including a connected electrode, and further connected to the connecting wiring is a fuse element capable of electrically disconnecting the connecting wiring;
It has a plurality of electrodes on the front and back surfaces that are stacked on the first silicon chip and are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are adjacent to each other. A second silicon chip including an electrode electrically connected to the electrode through a connection wiring, and further connected to the connection wiring by a fuse element capable of electrically disconnecting the connection wiring;
A wiring board electrically connected to the first silicon chip;
A plurality of external terminals provided on the wiring board;
At least one of the plurality of signal wirings formed on the first or second silicon chip, the fuse element of the connection wiring connected to the wiring is electrically cut to route the wiring A semiconductor device characterized in that is selected. (A) It has a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connecting wires. An electrically connected electrode; and a fuse element capable of electrically disconnecting the connection wiring is connected to the connection wiring, and at least one of the plurality of signal wirings, Preparing the first and second silicon chips in which the fuse element of the connection wiring connected to the wiring is electrically cut and the path of the wiring is selected;
(B) electrically connecting and mounting the first silicon chip on a wiring board;
(C) a step of electrically connecting and laminating the second silicon chip on the first silicon chip. (A) It has a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connecting wires. The electrode includes an electrically connected electrode, and in at least one of the plurality of signal lines, the connection line connected to the line is electrically disconnected by a laser so that the path of the line is Providing the selected first and second silicon chips;
(B) electrically connecting and mounting the first silicon chip on a wiring board;
(C) a step of electrically connecting and laminating the second silicon chip on the first silicon chip. (A) It has a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connecting wires. A step of preparing first and second silicon chips, each of which includes an electrically connected electrode, and wherein the connection wiring is connected to a fuse element capable of electrically disconnecting the connection wiring;
(B) At least one of a plurality of signal wirings formed on the first or second silicon chip, the fuse element of the connection wiring connected to the wiring is electrically cut to form the wiring Selecting a route for
(C) electrically connecting and mounting the first silicon chip on the wiring board;
(D) A method of manufacturing a semiconductor device, comprising: electrically connecting and stacking the second silicon chip on the first silicon chip. (A) It has a plurality of electrodes on the front and back surfaces that are electrically connected to each other through a conductor portion disposed in the through hole, and the plurality of electrodes on the front surface are connected to adjacent electrodes and connecting wires. A step of preparing a plurality of silicon chips, each of which includes an electrically connected electrode, and wherein the connection wiring is connected to a fuse element capable of electrically disconnecting the connection wiring;
(B) Among the plurality of signal lines formed on each of the plurality of silicon chips, in at least one line, the fuse element of the connection line connected to the line is electrically cut to route the line A process of selecting
(C) After electrically connecting and mounting any one of the plurality of silicon chips on the wiring substrate via bump electrodes, another silicon chip is connected to the silicon chip connected to the wiring substrate. And a step of electrically connecting and stacking silicon chips for each layer through bump electrodes.