JP2008118075A - Electronic component mounting method, electronic substrate, and electronic apparatus - Google Patents

Electronic component mounting method, electronic substrate, and electronic apparatus Download PDF

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Publication number
JP2008118075A
JP2008118075A JP2006302483A JP2006302483A JP2008118075A JP 2008118075 A JP2008118075 A JP 2008118075A JP 2006302483 A JP2006302483 A JP 2006302483A JP 2006302483 A JP2006302483 A JP 2006302483A JP 2008118075 A JP2008118075 A JP 2008118075A
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substrate
insulating
wiring
electronic component
forming
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JP2006302483A
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JP5018024B2 (en
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Takeshi Niidate
剛 新舘
Masaru Yajima
勝 矢島
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component mounting method that can efficiently form a mounting structure excellent in reliability. <P>SOLUTION: This mounting method comprises: a process to mount an IC chip 10 on a circuit substrate 20 (a); a process to arrange an insulating material using a drop discharge method on the circuit substrate 20 that lies between a connecting lug 14 and a terminal 22 on the side of the substrate, and form an insulating layer 30a by hardening at least part of the insulating material (b); a process to arrange the insulating material on the plane region narrower than the insulating layer 30a located on the insulating layer 30a and form an insulating layer 30b by hardening at least part of the insulating material (c); a process to form a slope material 30 which is a laminated layer film composed of insulating layers 30a to 30d by repeating the formation of the insulating layer by applying the insulating material (d); and a process to form connecting wiring 34 using the drop discharge method on the slope surface of the slope material 30 (e). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子部品の実装方法、電子基板、及び電子機器に関するものである。   The present invention relates to an electronic component mounting method, an electronic substrate, and an electronic apparatus.

近年、電子基板（電子基板）上に実装される電子部品の小型化が進んでおり、電子基板の細密化が要求されている。このような、細密な配線構造を形成する方法として、液滴吐出法を用いて、導電性パターンを絶縁膜中に埋め込んだ状態に形成する技術がある（例えば、特許文献１参照）。
特開２００５−３２７９８５号公報 In recent years, electronic components mounted on an electronic substrate (electronic substrate) have been downsized, and the electronic substrate has been required to be finer. As a method for forming such a fine wiring structure, there is a technique in which a conductive pattern is embedded in an insulating film by using a droplet discharge method (see, for example, Patent Document 1).
JP 2005-327985 A

ところで、上記電子基板が搭載される電子機器（例えば携帯電話等）についても、近年、小型化が進行しており、電子部品をより高密度で実装する方法の提供が望まれている。そこで、基板上にＩＣチップを固定し、該ＩＣチップの周囲に、液滴吐出法を用いて絶縁材料を塗布し、絶縁膜中にＩＣチップを埋め込み、該ＩＣチップに接続する配線を形成することで、ＩＣチップが高密度で実装された電子基板を構成することが考えられる。しかし電子部品の厚さが大きい場合には、液滴吐出法による絶縁膜形成に長時間を要するために効率が低下する。またその一方で、液滴吐出法による配線形成では、チップと基板面との間に段差があると、断線を生じてしまう。   Incidentally, electronic devices (for example, cellular phones) on which the electronic substrate is mounted have been downsized in recent years, and it is desired to provide a method for mounting electronic components at a higher density. Therefore, an IC chip is fixed on the substrate, an insulating material is applied around the IC chip using a droplet discharge method, the IC chip is embedded in an insulating film, and a wiring connected to the IC chip is formed. Thus, it is conceivable to constitute an electronic substrate on which IC chips are mounted at a high density. However, when the thickness of the electronic component is large, the efficiency is lowered because it takes a long time to form the insulating film by the droplet discharge method. On the other hand, in the wiring formation by the droplet discharge method, if there is a step between the chip and the substrate surface, disconnection occurs.

本発明は上記事情に鑑みてなされたもので、液滴吐出法を用いた絶縁膜形成工程を含む電子部品の実装方法において、信頼性に優れた実装構造を効率よく形成できる電子部品の実装方法を提供することを目的としている。また本発明は、電子部品の実装信頼性に優れる電子基板を提供することを目的としている。   The present invention has been made in view of the above circumstances, and in an electronic component mounting method including an insulating film forming step using a droplet discharge method, an electronic component mounting method capable of efficiently forming a highly reliable mounting structure The purpose is to provide. Another object of the present invention is to provide an electronic substrate that is excellent in mounting reliability of electronic components.

本発明の電子部品の実装方法は、上記課題を解決するために、基板側端子が配列された基板上に、接続端子が配列形成された端子形成面を有する電子部品を実装する方法であって、前記端子形成面を基板と反対側を向けた状態で前記電子部品を前記基板上に載置する工程と、前記電子部品の接続端子と、該接続端子に対応する前記基板側端子との間の前記基板上の領域に、前記基板側端子から前記端子形成面につながる斜面を形成する工程と、前記斜面上に、液滴吐出法を用いて、前記基板側端子と前記接続端子とを接続する配線を形成する工程と、を有し、前記斜面を形成する工程が、前記電子部品の接続端子と前記基板側端子との間の前記基板上の領域に、液滴吐出法を用いて絶縁材料を配置し、該絶縁材料の少なくとも一部を硬化させて第１の絶縁層を形成する工程と、前記第１の絶縁層上であって該第１の絶縁層より狭い平面領域に前記絶縁材料を配置し、該絶縁材料の少なくとも一部を硬化させて第２の絶縁層を形成する工程と、を繰り返すことで、前記電子部品の側方に前記絶縁層の積層膜を形成する工程であることを特徴とする。
この実装方法によれば、電子部品の側方に絶縁層の積層膜を形成することで、電子部品の端子形成面と基板との段差を緩和することができ、前記積層膜の斜面上に液滴吐出法を用いて配線を形成することができる。絶縁層を電子部品の側方にのみ形成するので、液滴吐出法による絶縁膜形成を部分的に行えばよく、電子部品と基板面との間に大きな段差がある場合にも極めて効率よく電子部品の実装を行うことができる。
またこの方法では、ワイヤボンディングのように配線を引き回す空間が必要ないことから、薄型の電子基板を簡便な工程で得ることができる。 An electronic component mounting method according to the present invention is a method for mounting an electronic component having a terminal formation surface on which connection terminals are arranged on a substrate on which board-side terminals are arranged, in order to solve the above-described problem. A step of placing the electronic component on the substrate with the terminal formation surface facing away from the substrate, and between the connection terminal of the electronic component and the substrate-side terminal corresponding to the connection terminal Forming a slope leading from the board-side terminal to the terminal-forming surface in a region on the board, and connecting the board-side terminal and the connection terminal on the slope using a droplet discharge method Forming a wiring line, and forming the inclined surface in a region on the substrate between the connection terminal of the electronic component and the substrate-side terminal using a droplet discharge method. Place the material and cure at least part of the insulating material Forming a first insulating layer; disposing the insulating material on a planar area narrower than the first insulating layer on the first insulating layer; and curing at least a part of the insulating material; And a step of forming a second insulating layer, and a step of forming a laminated film of the insulating layer on the side of the electronic component.
According to this mounting method, by forming the laminated film of the insulating layer on the side of the electronic component, the step between the terminal forming surface of the electronic component and the substrate can be relaxed, and the liquid is formed on the slope of the laminated film. Wiring can be formed using a droplet discharge method. Since the insulating layer is formed only on the side of the electronic component, it is only necessary to partially form the insulating film by the droplet discharge method. Even when there is a large step between the electronic component and the substrate surface, the electronic component is extremely efficient. Components can be mounted.
In addition, this method does not require a space for wiring as in wire bonding, and thus a thin electronic substrate can be obtained by a simple process.

前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる溝部を形成する工程を有し、前記配線を形成する工程では前記溝部内に前記配線を形成する実装方法とすることもできる。このような実装方法とすれば、溝部によって配線の形成領域が規定されるので、配線を正確かつ容易に形成することができる。   A mounting method may be provided in which a groove portion connected from the substrate-side terminal to the connection terminal is formed on the slope of the laminated film, and the wiring is formed in the groove portion in the step of forming the wiring. it can. With such a mounting method, since the formation region of the wiring is defined by the groove, the wiring can be formed accurately and easily.

また前記溝部を形成する工程が、前記積層膜の前記斜面上でレーザ光を走査する工程である実装方法とすることが好ましい。レーザ光を照射して積層膜の一部を除去するようにすれば、極めて容易に溝部を形成することができる。   Moreover, it is preferable to set it as the mounting method whose process of forming the said groove part is a process of scanning a laser beam on the said slope of the said laminated film. If a part of the laminated film is removed by irradiation with laser light, the groove can be formed very easily.

前記積層膜の前記斜面上に、絶縁材料を液滴吐出法を用いて配置し、当該絶縁材料の少なくとも一部を硬化することで、前記基板側端子から前記接続端子につながる絶縁下地膜を形成する工程を有し、前記配線を形成する工程では前記絶縁下地膜上に前記配線を形成する実装方法としてもよい。このような実装方法とすれば、配線形成領域を絶縁下地膜によって規定できるので、断線等を防ぎつつ正確に配線を形成できる。また、積層膜を構成する絶縁層間の段差を、絶縁下地膜により緩和することができるので、より確実に断線等を防止することができる。さらに、積層膜表面が液滴吐出法による配線形成に不適な表面状態となっていたとしても、絶縁下地膜によって配線形成領域の表面状態を配線形成に好適な状態に制御することができる。   An insulating base film connected from the substrate-side terminal to the connection terminal is formed by disposing an insulating material on the inclined surface of the laminated film using a droplet discharge method and curing at least a part of the insulating material. In the step of forming the wiring, the wiring may be formed on the insulating base film. With such a mounting method, since the wiring formation region can be defined by the insulating base film, wiring can be accurately formed while preventing disconnection and the like. Further, since the step between the insulating layers constituting the laminated film can be relaxed by the insulating base film, disconnection or the like can be prevented more reliably. Furthermore, even if the surface of the laminated film is in a surface state unsuitable for wiring formation by the droplet discharge method, the surface state of the wiring formation region can be controlled to a state suitable for wiring formation by the insulating base film.

また前記絶縁下地膜を形成する前記絶縁材料と、前記積層膜を形成する前記絶縁材料とが同一の絶縁材料である実装方法とすることもできる。このような実装方法とすれば、絶縁下地膜と積層膜との密着性を良好なものとすることができる。また、絶縁下地膜と積層膜との物理的特性の差異が無くなるので温度変化や応力に対する耐久性に優れる絶縁層を形成することができる。   In addition, a mounting method in which the insulating material for forming the insulating base film and the insulating material for forming the laminated film are the same insulating material may be employed. With such a mounting method, the adhesion between the insulating base film and the laminated film can be improved. In addition, since there is no difference in physical characteristics between the insulating base film and the laminated film, it is possible to form an insulating layer having excellent durability against temperature change and stress.

前記斜面を形成する工程において、前記積層膜を構成する前記各絶縁層を、外側に向かって突出する複数の突出部を有する形状に形成するとともに、前記各絶縁層の突出部が前記基板側端子から前記接続端子に向かって平面的に配列されるように前記各絶縁層を積層することで、前記各絶縁層内で隣接する前記突出部を側壁として前記基板側端子から前記接続端子につながる溝部を前記斜面上に形成し、前記配線を形成する工程では前記溝部内に前記配線を形成する実装方法とすることもできる。
この実装方法によれば、溝部により配線形成領域が規定されるので、配線を正確かつ安定に形成できるようになる。またかかる方法によれば、絶縁層の形状を利用して溝部を形成するので、レーザ光照射等の溝部形成のための工程が不要になり、電子基板の製造コストや製造効率の点で有利な実装方法となる。 In the step of forming the slope, the insulating layers constituting the laminated film are formed in a shape having a plurality of protruding portions protruding outward, and the protruding portions of the insulating layers are formed on the substrate-side terminals. By laminating each of the insulating layers so as to be arranged in a plane from the connection terminal to the connection terminal, the groove portion connected to the connection terminal from the substrate-side terminal using the adjacent protruding portion in each insulation layer as a side wall In the step of forming the wiring on the slope and forming the wiring, a mounting method may be used in which the wiring is formed in the groove.
According to this mounting method, since the wiring formation region is defined by the groove, the wiring can be formed accurately and stably. Further, according to such a method, since the groove portion is formed by utilizing the shape of the insulating layer, a step for forming the groove portion such as laser light irradiation becomes unnecessary, which is advantageous in terms of manufacturing cost and manufacturing efficiency of the electronic substrate. Implementation method.

また、前記各絶縁層に３カ所上の前記突出部を形成し、前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる複数の前記溝部を形成する実装方法とすることもできる。本発明の実装方法では、液滴吐出法を用いて絶縁層を形成するので、このように複数の溝部を有するよう各絶縁層を形成することも容易である。   Further, the mounting method may be such that the protruding portions at three places are formed in each insulating layer, and a plurality of the groove portions connected from the substrate-side terminal to the connection terminal are formed on the inclined surface of the laminated film. it can. In the mounting method of the present invention, since the insulating layer is formed by using a droplet discharge method, it is easy to form each insulating layer so as to have a plurality of groove portions.

前記電子部品を取り囲むように前記積層膜を形成する実装方法としてもよい。このような実装方法とすれば、電子部品の複数の辺縁から配線を引き出して実装することができる。   It is good also as a mounting method which forms the laminated film so as to surround the electronic component. With such a mounting method, wiring can be drawn out from a plurality of edges of the electronic component and mounted.

前記絶縁材料を基板上に配置した後、当該絶縁材料に光を照射することで、前記絶縁材料を部分的に硬化させる実装方法とすることが好ましい。光照射工程は極めて短時間に容易に実行できるので、絶縁層を部分的に硬化させる方法として好適である。   It is preferable that a mounting method in which the insulating material is partially cured by irradiating the insulating material with light after the insulating material is disposed on the substrate. Since the light irradiation step can be easily performed in a very short time, it is suitable as a method for partially curing the insulating layer.

前記配線を形成した後、前記電子部品、前記配線、及び前記絶縁層の積層膜を覆うように前記絶縁材料を塗布する工程と、前記絶縁材料に光を照射して部分的に硬化させて被覆絶縁層を形成する工程と、前記基板上に形成された前記絶縁層を加熱して硬化させる工程と、を有する実装方法とすることもできる。この実装方法によれば、光照射によって半硬化状態とした絶縁層と、半硬化状態の被覆絶縁層とを、加熱により一体的に硬化させるので、前記絶縁層と被覆絶縁層との間に応力が残留しないように硬化させることができる。したがって本実装方法によれば、電子部品の実装信頼性に優れた電子基板を得ることができる。   After forming the wiring, a step of applying the insulating material so as to cover the electronic component, the wiring, and the laminated film of the insulating layer, and the insulating material is irradiated with light and partially cured to cover It can also be set as the mounting method which has the process of forming an insulating layer, and the process of heating and hardening the said insulating layer formed on the said board | substrate. According to this mounting method, the insulating layer that has been semi-cured by light irradiation and the semi-cured covering insulating layer are integrally cured by heating, so stress is applied between the insulating layer and the covering insulating layer. Can be cured so as not to remain. Therefore, according to this mounting method, it is possible to obtain an electronic substrate having excellent mounting reliability of electronic components.

本発明の電子基板は、基板側端子が配列された基板上に、接続端子が配列形成された端子形成面を有する電子部品が実装された電子基板であって、前記電子部品の側方に、複数の絶縁層を積層してなり、前記基板側端子から該基板側端子に対応する前記接続端子につながる斜面を有する積層膜が形成されており、前記積層膜の前記斜面上に、前記基板側端子と前記接続端子とを接続する配線が形成されていることを特徴とする。
この電子基板によれば、電子部品と基板との段差を緩和する積層膜の斜面上に配線を形成しているので、ワイヤボンディングのように配線を引き回す空間を設ける必要が無く、薄型の電子基板を実現できる。 The electronic board of the present invention is an electronic board on which an electronic component having a terminal forming surface on which connection terminals are arranged is mounted on a board on which board-side terminals are arranged, on the side of the electronic component, A laminated film is formed by laminating a plurality of insulating layers, and a sloped film connected to the connection terminal corresponding to the board-side terminal from the board-side terminal is formed, and on the slope side of the laminated film, the substrate side A wiring for connecting the terminal and the connection terminal is formed.
According to this electronic substrate, since the wiring is formed on the slope of the laminated film that relaxes the step between the electronic component and the substrate, there is no need to provide a space for routing the wiring as in wire bonding, and the thin electronic substrate Can be realized.

前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる溝部が形成されており、当該溝部内に前記配線が形成されている構成としてもよい。この構成によれば、溝部によって配線の形成領域が規定されているので、配線間の短絡が生じにくく、優れた信頼性を得ることができる。   A groove portion connected from the substrate-side terminal to the connection terminal may be formed on the slope of the laminated film, and the wiring may be formed in the groove portion. According to this configuration, since the formation region of the wiring is defined by the groove, a short circuit between the wirings hardly occurs, and excellent reliability can be obtained.

前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる絶縁下地膜が形成され、当該絶縁下地膜上に前記配線が形成されている構成としてもよい。この構成によれば、絶縁下地膜によって積層膜の斜面上の段差がさらに緩和されているので、配線の断線等が生じにくく、信頼性に優れた電子基板となる。   An insulating base film connected from the substrate-side terminal to the connection terminal may be formed on the slope of the laminated film, and the wiring may be formed on the insulating base film. According to this configuration, the step on the inclined surface of the multilayer film is further relaxed by the insulating base film, so that the disconnection of the wiring hardly occurs and the electronic substrate is excellent in reliability.

前記積層膜を構成する前記各絶縁層に、当該絶縁層の一部を外側に突出させてなる複数の突出部が形成され、前記積層膜の前記斜面上で前記各絶縁層の突出部が平面的に配列されて、当該配列された前記突出部を側壁として前記基板側端子から前記接続端子につながる溝部が前記斜面上に形成されており、前記溝部内に前記配線が形成されている構成としてもよい。この構成によれば、溝部によって配線の形成領域が規定されているので、配線間の短絡が生じにくく、優れた信頼性を得ることができる。   Each insulating layer constituting the laminated film is formed with a plurality of protruding parts formed by projecting a part of the insulating layer to the outside, and the protruding parts of the insulating layers are flat on the slope of the laminated film. The groove portion connected to the connection terminal from the board-side terminal is formed on the inclined surface with the arranged protruding portion as a side wall, and the wiring is formed in the groove portion. Also good. According to this configuration, since the formation region of the wiring is defined by the groove, a short circuit between the wirings hardly occurs, and excellent reliability can be obtained.

本発明の電子機器は、先に記載の電子基板を備えたことを特徴とする。この構成によれば、信頼性に優れた高集積の電子基板を具備し、小型で高性能の電子機器を提供することができる。   An electronic apparatus according to the present invention includes the electronic substrate described above. According to this configuration, it is possible to provide a small and high-performance electronic device that includes a highly integrated electronic substrate with excellent reliability.

以下、本発明の実施の形態について図面を参照して説明するが、本発明の技術範囲は以下の実施の形態に限定されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to the following embodiments.

（第１の実施形態）
図１（ａ）は、本発明に係る電子部品の実装方法を用いて製造できる電子部品実装体である電子基板の平面構成図であり、図１（ｂ）は、（ａ）に示すＡ−Ａ’線に沿う断面構成図である。 (First embodiment)
Fig.1 (a) is a plane block diagram of the electronic substrate which is an electronic component mounting body which can be manufactured using the mounting method of the electronic component which concerns on this invention, FIG.1 (b) is A- shown to (a). It is a section lineblock diagram which meets an A 'line.

図１に示す電子基板１００は、回路基板２０の一面側（（ｂ）図上面側）に、ＩＣチップ（電子部品）１０をフェースアップボンディングし、ＩＣチップ１０の接続端子と回路基板２０上の配線パターンとを電気的に接続した構成である。本実施形態の場合、半導体集積回路を含むＩＣチップ１０の回路基板２０と反対側面に半導体集積回路１２ａが形成され、当該面がＩＣチップ１０の能動面となっている。   An electronic substrate 100 shown in FIG. 1 has an IC chip (electronic component) 10 face-up bonded to one surface side ((b) upper surface side) of the circuit board 20, and the connection terminals of the IC chip 10 and the circuit board 20 In this configuration, the wiring pattern is electrically connected. In the case of the present embodiment, the semiconductor integrated circuit 12a is formed on the side surface opposite to the circuit board 20 of the IC chip 10 including the semiconductor integrated circuit, and this surface is the active surface of the IC chip 10.

なお、本発明の実装方法を適用して実装できるＩＣチップ１０としては、図１に示したものに限らず、一面側に外部接続端子を具備した電子部品（電子デバイス）を広く用いることができる。すなわち、ＩＣチップ１０に代えて、集積回路を具備しない半導体部品等の能動部品を用いることもでき、受動部品（抵抗器、キャパシタ、インダクタ等）を用いてもよい。   Note that the IC chip 10 that can be mounted by applying the mounting method of the present invention is not limited to the one shown in FIG. 1, and an electronic component (electronic device) having an external connection terminal on one side can be widely used. . That is, instead of the IC chip 10, active components such as semiconductor components that do not include an integrated circuit can be used, and passive components (resistors, capacitors, inductors, etc.) can be used.

ＩＣチップ１０の能動面１２には、各辺端部に沿って複数の接続端子１４が配列形成されており、これらの接続端子１４…は、半導体集積回路１２ａから引き出された図示略の配線と電気的に接続されている。本実施形態では平面視矩形状のチップの周縁部に接続端子１４…が配列されている場合を示しているが、例えば、複数の接続端子１４は、能動面の二辺端部に沿う位置にのみ形成されていてもよく、能動面１２の中央部に１又は複数の接続端子１４が配置されていてもよい。   On the active surface 12 of the IC chip 10, a plurality of connection terminals 14 are arranged along each side edge, and these connection terminals 14... Are connected to unillustrated wiring drawn from the semiconductor integrated circuit 12 a. Electrically connected. In the present embodiment, a case is shown in which the connection terminals 14 are arranged on the peripheral edge of the rectangular chip in plan view. For example, the plurality of connection terminals 14 are located at positions along the two side edges of the active surface. Only one or a plurality of connection terminals 14 may be arranged in the central portion of the active surface 12.

図１（ｂ）に示すようにＩＣチップ１０の能動面１２を覆うようにパッシベーション膜１６が形成されている。パッシベーション膜１６は絶縁材料からなる薄膜であり、例えばＳｉＯ２やＳｉＮ等の無機絶縁材料を用いて形成される。あるいは、無機絶縁材料を用いて形成した絶縁膜上に、さらにポリイミド等の有機絶縁材料（樹脂材料）を用いた絶縁膜を積層してもよい。パッシベーション膜１６には、接続端子１４の少なくとも一部（例えば中央部）を露出させる開口が形成されている。すなわち、パッシベーション膜１６は、接続端子１４の少なくとも中央部を避けて形成されている。接続端子１４の端部にパッシベーション膜１６が乗り上げていてもよい。またパッシベーション膜１６は、前記接続端子１４上の領域を避けて能動面１２の表面を覆うように形成することが好ましい。さらにパッシべーション膜１６は、ＩＣチップ１０の側面ないし裏面側まで延設されていてもよい。また本実施形態の場合、ＩＣチップ１０の裏面（能動面１２と反対側のチップ面）には接続端子は形成されていないが、裏面にも接続端子等の電極が設けられていても構わない。さらに能動面１２と反対側に接続端子を有する場合には、図１とは反対に、能動面１２を回路基板１２側に向けて実装してもよい。 As shown in FIG. 1B, a passivation film 16 is formed so as to cover the active surface 12 of the IC chip 10. The passivation film 16 is a thin film made of an insulating material, and is formed using, for example, an inorganic insulating material such as SiO 2 or SiN. Alternatively, an insulating film using an organic insulating material (resin material) such as polyimide may be stacked on the insulating film formed using an inorganic insulating material. The passivation film 16 is formed with an opening that exposes at least a part (for example, a central portion) of the connection terminal 14. That is, the passivation film 16 is formed so as to avoid at least the central portion of the connection terminal 14. A passivation film 16 may run on the end of the connection terminal 14. The passivation film 16 is preferably formed so as to cover the surface of the active surface 12 while avoiding the region on the connection terminal 14. Further, the passivation film 16 may be extended to the side surface or the back surface side of the IC chip 10. In the present embodiment, the connection terminal is not formed on the back surface (chip surface opposite to the active surface 12) of the IC chip 10, but electrodes such as connection terminals may be provided on the back surface. . Further, when the connection terminal is provided on the side opposite to the active surface 12, the active surface 12 may be mounted toward the circuit board 12, contrary to FIG. 1.

上記構成を具備したＩＣチップ１０は、実装面（図１（ｂ）上側面）に基板側端子２２が形成された回路基板２０上に実装されている。基板側端子２２は、回路基板２０に設けられた図示略の配線と電気的に接続されており、例えばＩＣチップ１０の近傍に形成された配線の拡幅部（ランド）として設けられている。そして、ＩＣチップ１０の接続端子１４と回路基板２０の基板側端子２２とは、接続配線３４を介して電気的に接続されている。   The IC chip 10 having the above configuration is mounted on a circuit board 20 in which board-side terminals 22 are formed on a mounting surface (upper side surface in FIG. 1B). The board-side terminal 22 is electrically connected to a wiring (not shown) provided on the circuit board 20, and is provided, for example, as a widened portion (land) of the wiring formed in the vicinity of the IC chip 10. The connection terminal 14 of the IC chip 10 and the board-side terminal 22 of the circuit board 20 are electrically connected via the connection wiring 34.

回路基板２０は、図１（ｂ）では基板側端子２２のみを有するように示されているが、絶縁層を介して複数層の配線層が積層された多層基板であってもよく、その裏面側（図１（ｂ）下側面）に露出する配線を具備した両面基板であってもよい。さらに回路基板２０としては、内部に延在する導電パターンを含んだ部品内蔵型の配線基板を用いることもでき、この場合、回路基板２０の内部に抵抗器、キャパシタ、インダクタ等の受動部品又は集積回路部品等の能動部品が埋め込まれ、内蔵の導電パターンに電気的に接続されている構成が採用できる。   Although the circuit board 20 is shown in FIG. 1B as having only the board-side terminals 22, it may be a multilayer board in which a plurality of wiring layers are laminated via an insulating layer, and its back surface. It may be a double-sided board provided with wiring exposed on the side (the lower side in FIG. 1B). Further, as the circuit board 20, a component-embedded wiring board including a conductive pattern extending inside can be used. In this case, passive components such as resistors, capacitors, and inductors, or integrated circuits are provided inside the circuit board 20. A configuration in which active components such as circuit components are embedded and electrically connected to a built-in conductive pattern can be employed.

ＩＣチップ１０は、回路基板２０に対して、その裏面（能動面と反対側）を向けた状態で載置されており、ＩＣチップ１０と回路基板２０との間には、接着層２９が介在している。接着層２９としては、導電性の接着剤と、絶縁性の接着剤のいずれも用いることができ、導電性の接着剤を用いれば、チップ実装領域の配線パターンとＩＣチップ１０の裏面に設けられた電極との導電接続に利用することができる。絶縁性の接着剤としては、ＤＡＦ（ダイアタッチフィルム）を用いることができる。また、接着層２９には絶縁マトリクス中に導電粒子が分散された異方性導電ペースト（ＡＣＰ）や、異方性導電フィルム（ＡＣＦ）を用いることもでき、これらを用いることで、ＩＣチップ１０の接着層２９側に形成された接続端子と回路基板上の端子とを容易に接続することができる。   The IC chip 10 is placed with its back surface (opposite side of the active surface) facing the circuit board 20, and an adhesive layer 29 is interposed between the IC chip 10 and the circuit board 20. is doing. As the adhesive layer 29, either a conductive adhesive or an insulating adhesive can be used. If a conductive adhesive is used, the adhesive layer 29 is provided on the wiring pattern in the chip mounting area and the back surface of the IC chip 10. It can be used for conductive connection with other electrodes. As the insulating adhesive, DAF (die attach film) can be used. Further, the adhesive layer 29 can be made of an anisotropic conductive paste (ACP) in which conductive particles are dispersed in an insulating matrix or an anisotropic conductive film (ACF). By using these, the IC chip 10 can be used. The connection terminal formed on the adhesive layer 29 side and the terminal on the circuit board can be easily connected.

回路基板２０上に載置されたＩＣチップ１０を取り囲むように、ＩＣチップ１０の能動面１２と回路基板２０の実装面との段差を緩和する斜面を具備したスロープ材（積層膜）３０が設けられている。スロープ材３０は、絶縁材料（例えば樹脂）を用いて形成された複数の絶縁層３０ａ〜３０ｄを積層した構造を有する。絶縁層３０ａ〜３０ｄとしては、光硬化性の絶縁物質を含み、当該絶縁物質を含む液体の絶縁材料を基板上に配置した後、基板上の絶縁材料に光を照射することで、当該絶縁材料の少なくとも一部を硬化させることができるものを用いることが好ましい。   A slope material (laminated film) 30 having a slope for relaxing the step between the active surface 12 of the IC chip 10 and the mounting surface of the circuit board 20 is provided so as to surround the IC chip 10 placed on the circuit board 20. It has been. The slope material 30 has a structure in which a plurality of insulating layers 30a to 30d formed using an insulating material (for example, resin) are stacked. The insulating layers 30a to 30d include a photo-curable insulating material, and after a liquid insulating material including the insulating material is disposed on the substrate, the insulating material on the substrate is irradiated with light, thereby the insulating material It is preferable to use a material capable of curing at least a part of the material.

本実施形態の場合、絶縁層３０ａ〜３０ｄを形成するための絶縁材料として、アクリル樹脂（光硬化性絶縁物質）とエポキシ樹脂（熱硬化性絶縁物質）とを含む絶縁材料が用いられており、絶縁材料への光照射によってアクリル樹脂の硬化のみを進行させた半硬化状態の絶縁層を形成できるようになっている。このように半硬化状態を得られる絶縁材料を用いることで、絶縁層を積層した後に一括して完全硬化させることができるようになり、形成する絶縁層中に応力が残留するのを防止して、信頼性に優れた電子基板を得ることができる。また、硬化の進行度に伴う表面状態の変化を利用して製造時に絶縁層の表面状態（親液／撥液性）を制御することができる。   In the case of this embodiment, as an insulating material for forming the insulating layers 30a to 30d, an insulating material containing an acrylic resin (photo-curable insulating substance) and an epoxy resin (thermo-curable insulating substance) is used. It is possible to form a semi-cured insulating layer in which only the acrylic resin is cured by light irradiation to the insulating material. By using an insulating material that can obtain a semi-cured state in this way, it becomes possible to completely cure after laminating the insulating layers, and prevents stress from remaining in the insulating layer to be formed. An electronic substrate having excellent reliability can be obtained. In addition, the surface state (lyophilic / liquid repellency) of the insulating layer can be controlled at the time of manufacture by utilizing the change in the surface state accompanying the progress of curing.

スロープ材３０は、ＩＣチップ１０の側面に接触するようにして形成されており、スロープ材３０を構成する絶縁層３０ａ〜３０ｄがＩＣチップ１０を取り囲む枠状を成し、なおかつ上層側の絶縁層ほど狭い幅に形成されていることで、ＩＣチップ１０を取り囲む緩やかな階段状の斜面を形成している。このスロープ材３０の斜面により、ＩＣチップ１０の能動面１２と回路基板２０の実装面とがほぼ段差無く連続した表面を成している。スロープ材３０の高さは、ＩＣチップ１０の能動面１２と略同一の高さとすることが好ましいが、後述する接続配線３４の断線等を防止できる程度にＩＣチップ１０側方の段差を緩和できればよい。また、スロープ材３０は、接続端子１４を覆わない限度で能動面１２の周縁部に一部掛かるように形成されていてもよい。   The slope material 30 is formed so as to be in contact with the side surface of the IC chip 10, and the insulating layers 30 a to 30 d constituting the slope material 30 form a frame shape surrounding the IC chip 10, and the upper insulating layer. By being formed so narrow, a gentle step-like slope surrounding the IC chip 10 is formed. Due to the slope of the slope member 30, the active surface 12 of the IC chip 10 and the mounting surface of the circuit board 20 form a continuous surface with almost no step. The height of the slope member 30 is preferably substantially the same as that of the active surface 12 of the IC chip 10. However, if the step on the side of the IC chip 10 can be relaxed to such an extent that disconnection of the connection wiring 34 described later can be prevented. Good. Further, the slope member 30 may be formed so as to partially lie on the periphery of the active surface 12 as long as the connection terminal 14 is not covered.

ＩＣチップ１０の各接続端子１４は、液滴吐出法を用いて形成された接続配線３４を介して、対応する基板側端子２２と電気的に接続されている。具体的には、接続配線３４は、接続端子１４上からパッシベーション膜１６上及びスロープ材３０の斜面上を通って基板側端子２２に至るよう形成されている。このように、ＩＣチップ１０の側方に設けられたスロープ材３０の斜面部を介して異なる高さの端子と配線とを接続しているので、接続配線３４の断線を防止でき、またワイヤボンディングのようにワイヤを引き回す空間を要しないことから薄型の電子基板となっている。   Each connection terminal 14 of the IC chip 10 is electrically connected to the corresponding substrate side terminal 22 via a connection wiring 34 formed by using a droplet discharge method. Specifically, the connection wiring 34 is formed so as to reach the substrate-side terminal 22 from the connection terminal 14 through the passivation film 16 and the slope of the slope material 30. As described above, since the terminals and the wirings having different heights are connected via the slope portions of the slope member 30 provided on the side of the IC chip 10, the disconnection of the connection wiring 34 can be prevented, and the wire bonding is performed. Thus, a thin electronic substrate is obtained because a space for routing the wire is not required.

本実施形態の場合、ＩＣチップ１０を取り囲むように基板側端子２２が配置されているので、スロープ材３０がＩＣチップ１０を取り囲むように形成されているが、ＩＣチップ１０の一部の辺端部にのみ近接して基板側端子２２が形成されている場合には、その辺端部に隣接する部分にのみスロープ材３０を設ければよい。また、回路基板２０上に実装されたＩＣチップ１０は、これらの上層に形成された被覆絶縁層によって封止されていてもよい。被覆絶縁層は、スロープ材３０の絶縁層３０ａ〜３０ｄと同一の絶縁材料を用いて形成することが好ましい。このように同一の絶縁材料を用いて封止することで、接続配線３４の封止性をより良好なものとすることができ、また絶縁層における熱膨張係数や弾性係数の差異をなくせることから、信頼性に優れる電子基板を実現することができる。   In the case of this embodiment, since the board-side terminal 22 is disposed so as to surround the IC chip 10, the slope material 30 is formed so as to surround the IC chip 10. In the case where the board-side terminal 22 is formed close to only the portion, the slope material 30 may be provided only in the portion adjacent to the side edge portion. Further, the IC chip 10 mounted on the circuit board 20 may be sealed with a covering insulating layer formed on the upper layer. The covering insulating layer is preferably formed using the same insulating material as the insulating layers 30 a to 30 d of the slope member 30. By sealing with the same insulating material in this way, the sealing property of the connection wiring 34 can be improved, and the difference in thermal expansion coefficient and elastic coefficient in the insulating layer can be eliminated. Therefore, an electronic substrate with excellent reliability can be realized.

（電子部品の実装方法）
次に、本発明に係る電子デバイスの実装方法について説明する。
図２（ａ）〜（ｅ）は、上記実施形態の電子基板１００におけるＩＣチップ（電子部品）１０の実装工程を説明する図であって、図１（ｂ）に相当する断面構成図である。 (Electronic component mounting method)
Next, a method for mounting an electronic device according to the present invention will be described.
2A to 2E are views for explaining a mounting process of the IC chip (electronic component) 10 on the electronic substrate 100 of the embodiment, and are cross-sectional configuration diagrams corresponding to FIG. .

本実施形態の実装方法は、回路基板２０上にＩＣチップ１０を載置する載置工程（図２（ａ））と、ＩＣチップ１０の周囲にスロープ材３０を形成するスロープ材形成工程（図２（ｂ）〜図２（ｄ））と、接続配線３４を形成する接続配線形成工程（図２（ｅ））と、を有している。また接続配線工程では、液滴吐出法（液相法）を用いて接続配線３４を形成する。   The mounting method of this embodiment includes a mounting step (FIG. 2A) for mounting the IC chip 10 on the circuit board 20, and a slope material forming step (FIG. 2) for forming the slope material 30 around the IC chip 10. 2 (b) to FIG. 2 (d)) and a connection wiring formation step (FIG. 2 (e)) for forming the connection wiring 34. In the connection wiring process, the connection wiring 34 is formed using a droplet discharge method (liquid phase method).

＜載置工程＞
以下、図面を参照して実装方法の各工程について詳細に説明する。
まず、図２（ａ）に示すように、所定の基板側端子２２等が形成された回路基板２０上に、接着層２９を介してＩＣチップ１０を載置する。ＩＣチップ１０の基板上への載置は、真空チャック等によりＩＣチップ１０を吸着支持して搬送し、回路基板２０上の実装位置に配置する方法が採用できる。ＩＣチップ１０の裏面又は回路基板２０上に、図２（ａ）に示す接着層２９を形成するための接着剤を塗布した状態でＩＣチップ１０が回路基板２０上に載置される。接着層２９には、先に記載のように、ＤＡＦや樹脂製接着剤を用いることができる。接着層２９を介して回路基板２０にＩＣチップ１０を接着させた後でも、樹脂製接着剤を未硬化状態としておけば、ＩＣチップ１０の位置調整を容易に行うことができる。またこの場合において、ＩＣチップ１０の載置後にも真空チャックでＩＣチップ１０を保持しておき、真空チャックの水平移動によりＩＣチップ１０の位置調整を行ってもよい。 <Installation process>
Hereinafter, each step of the mounting method will be described in detail with reference to the drawings.
First, as shown in FIG. 2A, the IC chip 10 is placed on the circuit board 20 on which the predetermined board-side terminals 22 and the like are formed via the adhesive layer 29. For mounting the IC chip 10 on the substrate, a method can be employed in which the IC chip 10 is sucked and supported by a vacuum chuck or the like, and is disposed at a mounting position on the circuit board 20. The IC chip 10 is placed on the circuit board 20 in a state where an adhesive for forming the adhesive layer 29 shown in FIG. 2A is applied to the back surface of the IC chip 10 or the circuit board 20. As described above, DAF or resin adhesive can be used for the adhesive layer 29. Even after the IC chip 10 is adhered to the circuit board 20 via the adhesive layer 29, the position adjustment of the IC chip 10 can be easily performed if the resin adhesive is left in an uncured state. In this case, the IC chip 10 may be held by the vacuum chuck even after the IC chip 10 is placed, and the position of the IC chip 10 may be adjusted by the horizontal movement of the vacuum chuck.

ＩＣチップ１０を回路基板２０上に載置したならば、次に、図２（ｂ）〜図２（ｄ）に示すように、ＩＣチップ１０の側面部に当接するスロープ材３０を形成する。このスロープ材３０は、先に記載のように、光硬化性絶縁物質であるアクリル樹脂と、熱硬化性絶縁物質であるエポキシ樹脂とを含む絶縁材料を用いた液滴吐出法により形成される。本発明には、絶縁材料の塗布に用いられる公知の液滴吐出法が適用できる。
上記絶縁材料としては、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）等の樹脂材料を用いてもよい。 When the IC chip 10 is placed on the circuit board 20, next, as shown in FIGS. 2 (b) to 2 (d), a slope material 30 that contacts the side surface of the IC chip 10 is formed. As described above, the slope member 30 is formed by a droplet discharge method using an insulating material including an acrylic resin that is a photocurable insulating material and an epoxy resin that is a thermosetting insulating material. In the present invention, a known droplet discharge method used for applying an insulating material can be applied.
As the insulating material, a resin material such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like may be used.

スロープ材３０を形成するには、まず、図２（ｂ）及び図１（ａ）に示すように、液滴吐出法を用いて、ＩＣチップ１０を取り囲む枠状に、液体の絶縁材料を配置し、これに紫外線等の光を照射して絶縁材料の一部を硬化させることで絶縁材料を半硬化状態とした絶縁層３０ａを形成する。また、本実施形態では上記絶縁材料の表面状態が、半硬化状態と完全硬化状態との間で、硬化の程度に応じて親液性から撥液性に変化するものであるため、このように半硬化状態としておくことで、絶縁層３０ａ表面を、液相法による絶縁層や配線の形成に好適な状態に制御することができる。
次に、図２（ｃ）に示すように、絶縁層３０ａ上に、絶縁層３０ａよりも幅の狭い枠状に絶縁材料を配置し、これに紫外線等の光を照射することで、半硬化状態の絶縁材料からなる絶縁層３０ｂを形成する。
そして、図２（ｄ）に示すように、積層された絶縁層３０ａ〜３０ｄがＩＣチップ１０の高さに達するまで絶縁材料の塗布と光照射とを繰り返し、ＩＣチップ１０を取り囲む概略階段状のスロープ材３０を形成する。スロープ材３０の一部はＩＣチップ１０のパッシべーション膜１６に乗り上げていてもよい。 In order to form the slope member 30, first, as shown in FIGS. 2B and 1A, a liquid insulating material is disposed in a frame shape surrounding the IC chip 10 by using a droplet discharge method. Then, the insulating layer 30a in which the insulating material is semi-cured is formed by irradiating light such as ultraviolet rays to cure a part of the insulating material. Further, in this embodiment, the surface state of the insulating material is changed from a lyophilic property to a liquid repellency depending on the degree of curing between the semi-cured state and the fully cured state. By setting the semi-cured state, the surface of the insulating layer 30a can be controlled to be in a state suitable for forming an insulating layer or wiring by a liquid phase method.
Next, as shown in FIG. 2 (c), an insulating material is disposed on the insulating layer 30a in a frame shape narrower than the insulating layer 30a, and irradiated with light such as ultraviolet rays, thereby being semi-cured. An insulating layer 30b made of an insulating material in a state is formed.
Then, as shown in FIG. 2 (d), application of the insulating material and light irradiation are repeated until the laminated insulating layers 30 a to 30 d reach the height of the IC chip 10, and a substantially stepped shape surrounding the IC chip 10 is obtained. The slope material 30 is formed. A part of the slope material 30 may ride on the passivation film 16 of the IC chip 10.

上記積層形成される各絶縁層３０ａ〜３０ｄの厚さは、スロープ材３０の斜面上に形成される接続配線３４の断線等を回避できる程度の厚さであれば、特に限定されない。各絶縁層３０ａ〜３０ｄは液相法を用いて形成されているため、その端縁部は図２に示すように外側に向かって下降する傾斜面となっている。そのため、絶縁層を比較的厚く形成した場合であっても、接続配線３４に不具合は生じにくい。各絶縁層３０ａ〜３０ｄを接続配線３４の断線を回避できる限度で厚く形成すれば、スロープ材３０の形成工程に要する時間を短縮でき、効率よく電子部品の実装を行うことができる。   The thickness of each of the stacked insulating layers 30a to 30d is not particularly limited as long as the connection wiring 34 formed on the slope of the slope member 30 can be prevented from being disconnected. Since each of the insulating layers 30a to 30d is formed by using a liquid phase method, the end edge portion is an inclined surface that descends outward as shown in FIG. Therefore, even if the insulating layer is formed to be relatively thick, the connection wiring 34 is unlikely to be defective. If each of the insulating layers 30a to 30d is formed thick enough to avoid disconnection of the connection wiring 34, the time required for the step of forming the slope material 30 can be shortened and electronic components can be mounted efficiently.

次に、図２（ｅ）に示すように、接続配線３４を形成する。接続配線３４は、パッシべーション膜１６の開口部に露出された接続端子１４の上面からスロープ材３０の斜面上を通って基板側端子２２上に至るように形成する。本実施形態では、この接続配線３４の形成に際して、導電性微粒子を媒質に分散させた液体材料を吐出ヘッドにより選択配置する液滴吐出法を用いる。   Next, as shown in FIG. 2E, the connection wiring 34 is formed. The connection wiring 34 is formed so as to extend from the upper surface of the connection terminal 14 exposed at the opening of the passivation film 16 to the substrate side terminal 22 through the slope of the slope material 30. In the present embodiment, when the connection wiring 34 is formed, a droplet discharge method is used in which a liquid material in which conductive fine particles are dispersed in a medium is selectively arranged by an discharge head.

本実施形態で用いる接続配線形成用の液体材料は、導電性微粒子を分散媒に分散させた分散液、若しくはその前駆体からなるものである。導電性微粒子としては、例えば金、銀、銅、パラジウム、ニオブ及びニッケル等を含有する金属微粒子の他、これらの前駆体、合金、酸化物、並びに導電性ポリマーやインジウム錫酸化物等の微粒子などを用いることができる。導電性微粒子は、分散性を向上させるために表面に有機物などをコーティングして使うこともできる。導電性微粒子の粒径は１ｎｍ〜０．１μｍ程度であることが好ましい。かかる粒径のものを用いることで、吐出ヘッドのノズル目詰まりを防止しつつ、緻密な構造の配線を形成できる。分散媒としては、上記の導電性微粒子を分散できるもので、凝集を起こさないものであれば特に限定されない。例えば、水やアルコール類、炭化水素系化合物、エーテル系化合物、極性化合物等を用いることができる。   The liquid material for forming the connection wiring used in the present embodiment is made of a dispersion obtained by dispersing conductive fine particles in a dispersion medium, or a precursor thereof. Examples of the conductive fine particles include metal fine particles containing, for example, gold, silver, copper, palladium, niobium and nickel, as well as their precursors, alloys, oxides, and fine particles such as conductive polymers and indium tin oxide. Can be used. The conductive fine particles can be used by coating the surface with an organic substance or the like in order to improve dispersibility. The particle diameter of the conductive fine particles is preferably about 1 nm to 0.1 μm. By using a material having such a particle size, it is possible to form a densely structured wiring while preventing nozzle clogging of the ejection head. The dispersion medium is not particularly limited as long as it can disperse the conductive fine particles and does not cause aggregation. For example, water, alcohols, hydrocarbon compounds, ether compounds, polar compounds, and the like can be used.

図２（ｅ）に示すように、接続端子１４と基板側端子２２とを接続する線状に液体材料を配置する。液体材料の吐出を複数回繰り返して行うことで、所定厚さの導電層が積層された構造の接続配線３４を形成してもよい。液体材料を配置したならば、回路基板２０上に配された液体材料に含まれる分散媒の除去を目的として乾燥処理を行う。この乾燥処理は、真空乾燥や加熱処理により行うことができる。
ただし、接続配線３４を絶縁層中に封止した構成の電子基板を製造する場合には、かかる乾燥処理において加熱を行わず、接続配線３４上にさらに被覆絶縁層を形成した後に加熱を行うこととするのが好ましい。接続配線３４上の被覆絶縁層とともに硬化させることで、接続配線３４を取り囲む絶縁層内に応力が残留するのを防止でき、また封止状態をより良好なものとすることができるからである。 As shown in FIG. 2E, the liquid material is arranged in a line connecting the connection terminal 14 and the substrate side terminal 22. The connection wiring 34 having a structure in which a conductive layer having a predetermined thickness is stacked may be formed by repeatedly discharging the liquid material a plurality of times. When the liquid material is disposed, a drying process is performed for the purpose of removing the dispersion medium contained in the liquid material disposed on the circuit board 20. This drying process can be performed by vacuum drying or heat treatment.
However, in the case of manufacturing an electronic substrate having a configuration in which the connection wiring 34 is sealed in an insulating layer, heating is not performed in such a drying process, but heating is performed after a further covering insulating layer is formed on the connection wiring 34. Is preferable. This is because by hardening together with the covering insulating layer on the connection wiring 34, it is possible to prevent the stress from remaining in the insulating layer surrounding the connection wiring 34 and to improve the sealing state.

上記乾燥処理に続いて、回路基板２０上の乾燥膜（導電性微粒子の集合体）の導電性を向上させることを目的として、加熱処理又は光照射処理による焼成工程を実施する。
この焼成工程により、分散媒の除去がより確実に成される。また前記乾燥体に金属有機塩が含まれている場合、熱分解により金属に変成することができる。さらに、導電性微粒子がコーティング材に覆われている場合、その除去も行うことができる。
加熱処理や光照射処理は通常大気中で行われるが、必要に応じて、窒素、アルゴン、ヘリウムなどの不活性ガス雰囲気中で行うこともできる。この加熱工程についても、接続配線３４上にさらに絶縁層を積層する場合には、かかる絶縁層の硬化工程と一括して行うことが好ましい。 Subsequent to the drying treatment, a firing step by heat treatment or light irradiation treatment is performed for the purpose of improving the conductivity of the dry film (aggregate of conductive fine particles) on the circuit board 20.
By this firing step, the dispersion medium is more reliably removed. Further, when a metal organic salt is contained in the dried body, it can be transformed into a metal by thermal decomposition. Further, when the conductive fine particles are covered with the coating material, the removal can also be performed.
The heat treatment and light irradiation treatment are usually performed in the air, but can be performed in an inert gas atmosphere such as nitrogen, argon, helium or the like, if necessary. This heating process is preferably performed together with the curing process of the insulating layer when an insulating layer is further laminated on the connection wiring 34.

以上の工程により、ＩＣチップ１０を回路基板２０上に実装することができる。
なお、実装したＩＣチップ１０上に、さらに絶縁材料を塗布して被覆絶縁層を形成し、ＩＣチップ１０や接続配線３４を封止してもよく、封止後の被覆絶縁層上にさらに配線等を形成することもできる。
特に、この接続配線３４上に積層される被覆絶縁層を、絶縁層３０ａ〜３０ｄの形成に用いられる絶縁材料と同一の絶縁材料により形成すれば、極めて良好に配線を封止でき、優れた信頼性を得ることができる。
被覆絶縁層についてより詳細に説明すると、上述したようにスロープ材３０を構成する絶縁層３０ａ〜３０ｄは、光照射により半硬化状態とされた絶縁材料からなる状態で接続配線３４の形成工程に供される。その後、かかるスロープ材３０を加熱すれば、半硬化状態の絶縁材料を完全に硬化させることができるが、このとき、接続配線３４上にスロープ材３０と同一の絶縁材料からなり、光照射により半硬化状態とされた被覆絶縁層が配されていると、加熱によって接続配線３４下の絶縁層３０ａ〜３０ｄと被覆絶縁層とが、それらの間に界面を形成することなく一体となって硬化するために接続配線３４への水分の進入経路や、接続配線３４の構成材料のマイグレーション経路が形成されにくくなり、また絶縁層中に応力が残留するのも防止できるので、極めて優れた信頼性を得ることができる。 Through the above steps, the IC chip 10 can be mounted on the circuit board 20.
Note that an insulating material may be further applied to the mounted IC chip 10 to form a covering insulating layer, and the IC chip 10 and the connection wiring 34 may be sealed. Further wiring may be provided on the covering insulating layer after sealing. Etc. can also be formed.
In particular, if the covering insulating layer laminated on the connection wiring 34 is formed of the same insulating material as the insulating material used for forming the insulating layers 30a to 30d, the wiring can be sealed very well and excellent reliability can be obtained. Sex can be obtained.
The covering insulating layer will be described in more detail. As described above, the insulating layers 30a to 30d constituting the slope member 30 are used for the process of forming the connection wiring 34 in a state of being made of an insulating material that is semi-cured by light irradiation. Is done. Thereafter, if the slope material 30 is heated, the semi-cured insulating material can be completely cured, but at this time, the connection wiring 34 is made of the same insulating material as the slope material 30 and is half irradiated by light irradiation. When the coating insulating layer in a cured state is disposed, the insulating layers 30a to 30d under the connection wiring 34 and the coating insulating layer are cured by heating without forming an interface therebetween. For this reason, it becomes difficult to form a moisture ingress path to the connection wiring 34 and a migration path of the constituent material of the connection wiring 34, and it is possible to prevent the stress from remaining in the insulating layer, thereby obtaining extremely excellent reliability. be able to.

なお、上記被覆絶縁層の形成には、必ずしも液滴吐出法を用いなくてもよい。ディスペンサ等を用いて被覆絶縁層形成用の絶縁材料を塗布すれば、ＩＣチップ１０や接続配線３４を覆う被覆絶縁層を短時間に形成できる。このように本発明では、領域選択的な絶縁層（スロープ材３０）の形成にのみ液滴吐出法を用い、正確な液体配置が可能である一方で、吐出量が少ないという液滴吐出法の不利な点を補い、高効率に信頼性に優れた実装構造を得られるようにしている。   Note that the droplet discharge method is not necessarily used for forming the covering insulating layer. If the insulating material for forming the covering insulating layer is applied using a dispenser or the like, the covering insulating layer covering the IC chip 10 and the connection wiring 34 can be formed in a short time. As described above, according to the present invention, the droplet discharge method is used only for forming the region-selective insulating layer (slope material 30), and an accurate liquid arrangement is possible, while the droplet discharge method has a small discharge amount. To compensate for the disadvantages, we have achieved a highly efficient and highly reliable mounting structure.

また本実施形態によれば、接続端子１４と基板側端子２２とを電気的に接続する接続配線３４を、液滴吐出法を用いて形成しているので、ワイヤボンディングやフェースダウンボンディングで行われるような超音波振動の付与や加圧を避けることができる。したがって、基板２０に対する耐熱性の要求を減らし、ＩＣチップ１０のストレスの発生を減らすことができる。また、接続配線３４は、ＩＣチップ１０及びスロープ材３０の表面に密着した状態で形成されるので、ワイヤボンディングのようにワイヤを引き回す空間は不要であり、薄型の電子基板を得ることができ、かかる電子基板によれば、これを備える電子機器の薄型化、小型化に寄与し得るものとなる。また、基板２０として汎用基板を使用し、ＩＣチップ１０の構成（接続端子１４の配列等）に応じて接続配線３４を引き回すこともできる。   Further, according to the present embodiment, the connection wiring 34 that electrically connects the connection terminal 14 and the substrate side terminal 22 is formed by using the droplet discharge method, and therefore, it is performed by wire bonding or face-down bonding. Such application of ultrasonic vibration and pressurization can be avoided. Therefore, the heat resistance requirement for the substrate 20 can be reduced, and the occurrence of stress on the IC chip 10 can be reduced. In addition, since the connection wiring 34 is formed in close contact with the surfaces of the IC chip 10 and the slope member 30, a space for drawing the wire as in wire bonding is unnecessary, and a thin electronic substrate can be obtained. According to such an electronic substrate, it is possible to contribute to thinning and miniaturization of an electronic device including the electronic substrate. Further, a general-purpose substrate can be used as the substrate 20, and the connection wiring 34 can be routed according to the configuration of the IC chip 10 (such as the arrangement of the connection terminals 14).

（第２の実施形態）
図３（ａ）は、本発明に係る電子部品の実装方法の第２の実施形態を説明するための電子基板の部分断面構成図であり、図３（ｂ）は図３（ａ）に対応する平面構成図、図３（ｃ）は図３（ａ）に対応する斜視構成図である。
先の第１の実施形態では、ＩＣチップ１０の側方に概略階段状のスロープ材３０を形成し、スロープ材３０の斜面上に接続配線３４を形成することとしていた。これに対して本実施形態では、図３に示すように、スロープ材３０の斜面上に複数の溝部３０ｓを形成し、かかる溝部３０ｓ内に接続配線３４を形成するようになっている。 (Second Embodiment)
FIG. 3A is a partial cross-sectional configuration diagram of an electronic board for explaining a second embodiment of the electronic component mounting method according to the present invention, and FIG. 3B corresponds to FIG. FIG. 3 (c) is a perspective configuration diagram corresponding to FIG. 3 (a).
In the first embodiment, the slope material 30 having a substantially step shape is formed on the side of the IC chip 10, and the connection wiring 34 is formed on the slope of the slope material 30. On the other hand, in this embodiment, as shown in FIG. 3, a plurality of groove portions 30s are formed on the slope of the slope member 30, and the connection wirings 34 are formed in the groove portions 30s.

本実施形態の電子部品の実装方法において、スロープ材３０を構成する絶縁層３０ａ〜３０ｅの形成工程は、図２に示した第１実施形態の工程と同様である。そして、本実施形態では、スロープ材３０を形成した後、図３（ｂ）に示すように、基板側端子２２とこれに対応する接続端子１４とを結ぶ直線に沿って、スロープ材３０の斜面上に溝部３０ｓを形成する。溝部３０ｓは、例えばレーザ光で前記斜面上を走査して、かかる斜面の一部を除去することで形成することができる。このように基板側端子２２から接続端子１４につながる溝部３０ｓを形成することで、液滴吐出法による接続配線３４の形成を容易かつ正確に行えるようになる。また、溝部３０ｓの形成時において、絶縁層３０ａ〜３０ｅは光照射により半硬化状態としておけば、溝部３０ｓ内部においても液滴吐出法による接続配線３４の形成に好適な表面状態を得ることができ、さらに接続配線３４の形成後に被覆絶縁層による封止を行う際にも、良好な封止性を得ることができる。   In the electronic component mounting method of the present embodiment, the formation process of the insulating layers 30a to 30e constituting the slope member 30 is the same as the process of the first embodiment shown in FIG. And in this embodiment, after forming the slope material 30, as shown in FIG.3 (b), the slope of the slope material 30 along the straight line which connects the board | substrate side terminal 22 and the connecting terminal 14 corresponding to this. A groove 30s is formed on the top. The groove 30s can be formed by, for example, scanning the slope with a laser beam and removing a part of the slope. Thus, by forming the groove portion 30s connected from the substrate side terminal 22 to the connection terminal 14, the connection wiring 34 can be easily and accurately formed by the droplet discharge method. In addition, if the insulating layers 30a to 30e are in a semi-cured state by light irradiation when the groove 30s is formed, a surface state suitable for forming the connection wiring 34 by the droplet discharge method can be obtained also inside the groove 30s. Further, when sealing with a coating insulating layer is performed after the connection wiring 34 is formed, good sealing performance can be obtained.

（第３の実施形態）
図４（ａ）は、本発明に係る電子部品の実装方法の第３の実施形態を説明するための電子基板の部分断面構成図であり、図４（ｂ）は図４（ａ）に対応する平面構成図である。本実施形態では、上記第２実施形態の溝部３０ｓに代えて、スロープ材３０の斜面上に絶縁下地膜４０を形成する。 (Third embodiment)
FIG. 4A is a partial cross-sectional configuration diagram of an electronic substrate for explaining a third embodiment of the electronic component mounting method according to the present invention, and FIG. 4B corresponds to FIG. FIG. In the present embodiment, the insulating base film 40 is formed on the slope of the slope member 30 instead of the groove 30s of the second embodiment.

本実施形態の電子部品の実装方法において、スロープ材３０を構成する絶縁層３０ａ〜３０ｅの形成工程は、図２に示した第１実施形態の工程と同様である。そして、本実施形態では、スロープ材３０を形成した後、図３（ｂ）に示すように、基板側端子２２からこれに対応する接続端子１４につながる絶縁下地膜４０を液滴吐出法を用いた絶縁材料の塗布により形成する。絶縁下地膜４０の形成には、絶縁層３０ａ〜３０ｅと同一の絶縁材料を用いることが好ましく、かかる絶縁材料を用いることで、スロープ材３０との良好な密着性が得られ、また物理的特性も同一のものとなるので、温度変化や応力に対する耐久性に優れた絶縁層を形成できる。さらに、絶縁層３０ａ〜３０ｅと同一の絶縁材料を用いれば、光照射によって半硬化状態にすることで、液滴吐出法による配線形成に好適な表面状態を得られるので、スロープ材３０の絶縁層３０ａ〜３０ｅを完全硬化させた後でも接続配線３４の形成領域を選択的に所望の表面状態とすることができ、接続配線３４を正確な形状で形成することができる。   In the electronic component mounting method of the present embodiment, the formation process of the insulating layers 30a to 30e constituting the slope member 30 is the same as the process of the first embodiment shown in FIG. In the present embodiment, after forming the slope member 30, as shown in FIG. 3B, the insulating base film 40 connected from the substrate side terminal 22 to the corresponding connection terminal 14 is applied using a droplet discharge method. It is formed by applying the insulating material. For the formation of the insulating base film 40, it is preferable to use the same insulating material as that of the insulating layers 30a to 30e. By using such an insulating material, good adhesion to the slope material 30 can be obtained, and physical characteristics can be obtained. Therefore, it is possible to form an insulating layer having excellent durability against temperature change and stress. Furthermore, if the same insulating material as that of the insulating layers 30a to 30e is used, a surface state suitable for wiring formation by a droplet discharge method can be obtained by making the semi-cured state by light irradiation. Even after 30a to 30e are completely cured, the formation region of the connection wiring 34 can be selectively brought into a desired surface state, and the connection wiring 34 can be formed in an accurate shape.

本実施形態のように、スロープ材３０の斜面上に改めて絶縁下地膜４０を形成することで、図３（ａ）に示すように、概略階段状となっている斜面における絶縁層間の段差を緩和することができるので、絶縁下地膜４０上に形成される接続配線３４の断線等を効果的に防止することができ、信頼性に優れる実装構造を得ることができる。   By forming the insulating base film 40 on the slope of the slope member 30 as in the present embodiment, the step between the insulating layers on the slope having a substantially step shape is reduced as shown in FIG. Therefore, disconnection of the connection wiring 34 formed on the insulating base film 40 can be effectively prevented, and a mounting structure with excellent reliability can be obtained.

（第４の実施形態）
図５（ａ）は、本発明に係る電子部品の実装方法の第５の実施形態を説明するための電子基板の部分断面構成図であり、図５（ｂ）は図５（ａ）に対応する平面構成図、図５（ｃ）は図５（ａ）に対応する斜視構成図である。本実施形態は、第２実施形態と同様の機能を奏する溝部３０ｓを、絶縁層の形状を利用して形成する実装方法である。 (Fourth embodiment)
FIG. 5A is a partial sectional configuration diagram of an electronic board for explaining a fifth embodiment of the electronic component mounting method according to the present invention, and FIG. 5B corresponds to FIG. FIG. 5C is a perspective configuration diagram corresponding to FIG. The present embodiment is a mounting method in which the groove 30s having the same function as that of the second embodiment is formed using the shape of the insulating layer.

本実施形態の電子部品の実装方法において、スロープ材３０を構成する絶縁層３０ａ〜３０ｅの形成工程は、図２に示した第１実施形態の工程と同様であるが、回路基板２０上に積層する各絶縁層３０ａ〜３０ｅについて、それぞれ図５（ｂ）に示すような複数の突出部４１ａ〜４１ｅを有する形状としている。さらに、各絶縁層３０ａ〜３０ｅの突出部４１ａ〜４１ｅを、図示のように、基板側端子２２から接続端子１４に向かって一列に配列することで、同じ絶縁層内で隣接する突出部４１ａ（４１ｂ〜４１ｅ）、４１ａ（４１ｂ〜４１ｅ）間の凹部が基板側端子２２から接続端子１４につながるように配列された溝部３０ｓをスロープ材３０の斜面上に形成している。   In the electronic component mounting method of the present embodiment, the formation process of the insulating layers 30a to 30e constituting the slope member 30 is the same as the process of the first embodiment shown in FIG. Each of the insulating layers 30a to 30e to be formed has a plurality of protruding portions 41a to 41e as shown in FIG. Furthermore, the protrusions 41a to 41e of the insulating layers 30a to 30e are arranged in a line from the substrate side terminal 22 toward the connection terminal 14 as shown in the figure, so that the protrusions 41a ( 41 b-41 e) and 41 a (41 b-41 e) are formed on the slope of the slope member 30 with a groove 30 s arranged so that the recesses between the board-side terminal 22 and the connection terminal 14 are connected.

上記構成を備えたスロープ材３０を形成することで、図５（ｃ）に示すように突出部４１ａ〜４１ｅに囲まれた溝部３０ｓ内に接続配線３４を形成できるので、液滴吐出法による接続配線３４の形成を容易かつ正確に行えるようになる。また、第２実施形態に比しても、溝部を形成するためのレーザ光走査が不要であるから、製造コストや製造効率の点で有利な実装方法である。   By forming the slope member 30 having the above-described configuration, the connection wiring 34 can be formed in the groove 30s surrounded by the protrusions 41a to 41e as shown in FIG. The wiring 34 can be formed easily and accurately. Further, compared with the second embodiment, since the laser beam scanning for forming the groove is unnecessary, this is a mounting method advantageous in terms of manufacturing cost and manufacturing efficiency.

なお、図５では、図面を見やすくするために隣接する絶縁層の突出部（例えば絶縁層３０ａの突出部４１ａと、かかる突出部４１ａの接続端子１４側に隣接する絶縁層３０ｂの突出部４１ｂ）が平面視で重ならないように配置されているが、１つの溝部３０ｓを構成する突出部４１ａ〜４１ｅのうち隣接する突出部どうし（例えば突出部４１ａ、４１ｂ）とが、一部平面的に重なるように配置されていてもよい。このような構成とすれば、隣接する突出部４１ａ〜４１ｅの間で溝部３０ｓの側壁を途切れることなく形成できるので、溝部３０ｓへの接続配線３４の形成をより正確にかつ安定に行えるようになる。   In FIG. 5, in order to make the drawing easy to see, adjacent protrusions of the insulating layer (for example, the protrusion 41 a of the insulating layer 30 a and the protrusion 41 b of the insulating layer 30 b adjacent to the connection terminal 14 side of the protrusion 41 a). Are arranged so as not to overlap with each other in plan view, but adjacent protrusions (for example, protrusions 41a and 41b) among the protrusions 41a to 41e constituting one groove 30s partially overlap in plan view. It may be arranged as follows. With such a configuration, the side wall of the groove 30s can be formed between the adjacent protrusions 41a to 41e without interruption, so that the connection wiring 34 can be more accurately and stably formed in the groove 30s. .

また、本実施形態において、接続配線３４の形成に先立って、溝部３０ｓ内に第３実施形態と同様の絶縁下地膜４０を形成してもよい。このようにすれば、概略階段状の溝部３０ｓ内の段差を絶縁下地膜により緩和することができるので、接続配線３４の信頼性をさらに優れたものとすることができる。また、スロープ材３０を加熱により完全硬化させた後でも、絶縁下地膜を形成することで溝部３０ｓ内に接続配線３４の形成に好適な表面状態を形成することができる。   In this embodiment, prior to the formation of the connection wiring 34, the insulating base film 40 similar to that of the third embodiment may be formed in the groove 30s. In this way, the step in the approximately step-like groove 30s can be relaxed by the insulating base film, and the reliability of the connection wiring 34 can be further improved. Further, even after the slope member 30 is completely cured by heating, a surface state suitable for forming the connection wiring 34 can be formed in the groove 30s by forming the insulating base film.

（電子基板の他の構成）
本実施形態の電子部品の実装方法によれば、図６に示すような構成の電子基板２００を得ることができる。図６に示す電子基板２００は、多層配線構造を備えた回路基板２０上に、ＩＣチップ１０等を実装したものである。 (Other configurations of electronic substrate)
According to the electronic component mounting method of the present embodiment, an electronic substrate 200 having a configuration as shown in FIG. 6 can be obtained. An electronic substrate 200 shown in FIG. 6 is obtained by mounting an IC chip 10 or the like on a circuit substrate 20 having a multilayer wiring structure.

本例の回路基板２０は、基板２０Ａ上に２個の回路チップ１２０，１２１を実装し、さらに多層の配線構造を備えた回路基板である。具体的には、基板２０Ａ上に配置された回路チップ１２０，１２１を取り囲むように形成された第１の絶縁層１１３が形成されており、第１層間絶縁膜１１３上に露出した回路チップ１２０，１２０のバンプ電極１４０に対して、第１層間絶縁膜１１３上に形成された配線パターン１１５が接続されている。
配線パターン１１５上を含む第１層間絶縁膜１１３上に第２層間絶縁膜１６０が形成されており、第２層間絶縁膜１６０上に形成された配線パターン１２５は、第２層間絶縁膜１６０を貫通して形成されたコンタクトホールＨ１，Ｈ２を介して下層側の配線パターン１１５と電気的に接続されている。
配線パターン１２５上を含む第２層間絶縁膜１６０上に、第３層間絶縁膜１６２が形成されており、第３層間絶縁膜１６２を貫通してコンタクトホールＨ３〜Ｈ５が形成されている。コンタクトホールＨ３を介して第３層間絶縁膜１６２上に形成された配線パターン１３５と下層側の配線パターン１１５とが接続されている。コンタクトホールＨ４，Ｈ５を介して第３層間絶縁膜１６３上に形成された基板側端子２２と下層側の配線パターン１２５とが接続されている。
そして、第３層間絶縁膜１６２上に実装されたＩＣチップ１０は、スロープ材３０上に形成された接続配線３４を介して基板側端子２２と電気的に接続され、さらにコンタクトホールＨ４、Ｈ５を介して配線パターン１２５と接続されている。配線パターン１２５と接続された配線パターン１１５を介して回路チップ１２０，１２１と電気的に接続されている。
さらに、ＩＣチップ１０と配線パターン１３５とを覆って被覆絶縁膜１６３が形成されている。被覆絶縁膜１６３を貫通するコンタクトホールＨ６が形成されており、コンタクトホールＨ６を介して被覆絶縁膜１６３上に配置された回路チップ１２４と配線パターン１３５とが電気的に接続されている。 The circuit board 20 of this example is a circuit board in which two circuit chips 120 and 121 are mounted on a board 20A and a multilayer wiring structure is provided. Specifically, a first insulating layer 113 formed so as to surround the circuit chips 120 and 121 disposed on the substrate 20A is formed, and the circuit chips 120 and 120 exposed on the first interlayer insulating film 113 are formed. A wiring pattern 115 formed on the first interlayer insulating film 113 is connected to the 120 bump electrodes 140.
A second interlayer insulating film 160 is formed on the first interlayer insulating film 113 including the wiring pattern 115, and the wiring pattern 125 formed on the second interlayer insulating film 160 penetrates the second interlayer insulating film 160. The wiring pattern 115 on the lower layer side is electrically connected through the contact holes H1 and H2 formed in this manner.
A third interlayer insulating film 162 is formed on the second interlayer insulating film 160 including the wiring pattern 125, and contact holes H3 to H5 are formed through the third interlayer insulating film 162. The wiring pattern 135 formed on the third interlayer insulating film 162 and the lower wiring pattern 115 are connected via the contact hole H3. The substrate-side terminal 22 formed on the third interlayer insulating film 163 and the lower-layer-side wiring pattern 125 are connected via the contact holes H4 and H5.
Then, the IC chip 10 mounted on the third interlayer insulating film 162 is electrically connected to the substrate side terminal 22 through the connection wiring 34 formed on the slope material 30, and further, contact holes H4 and H5 are connected. It is connected to the wiring pattern 125 via. The circuit chips 120 and 121 are electrically connected via the wiring pattern 115 connected to the wiring pattern 125.
Further, a covering insulating film 163 is formed so as to cover the IC chip 10 and the wiring pattern 135. A contact hole H6 penetrating the coating insulating film 163 is formed, and the circuit chip 124 and the wiring pattern 135 disposed on the coating insulating film 163 are electrically connected via the contact hole H6.

このように、本発明の電子部品の実装方法は、任意の構成の回路基板への部品実装に適用することができ、また本発明の実装方法を採用することで、信頼性に優れた薄型の実装構造を得られるので、電子基板の小型化、薄型化が容易になる。
なお、本実施形態では、ＩＣチップ１０の実装にのみ本発明に係る実装方法を適用しているが、同様に接続端子（バンプ電極４０）を基板２０Ａと反対側に向けて配置されている回路チップ１２０，１２１の実装について、本発明に係る実装方法を採用してもよいのは勿論である。 Thus, the electronic component mounting method of the present invention can be applied to component mounting on a circuit board having an arbitrary configuration, and by adopting the mounting method of the present invention, a thin and excellent in reliability. Since a mounting structure can be obtained, the electronic substrate can be easily reduced in size and thickness.
In the present embodiment, the mounting method according to the present invention is applied only to the mounting of the IC chip 10. Similarly, a circuit in which the connection terminals (bump electrodes 40) are arranged facing away from the substrate 20 </ b> A. Of course, the mounting method according to the present invention may be adopted for mounting the chips 120 and 121.

（電子機器）
図７は、本発明に係る電子機器の一例を示す斜視図である。この図に示す携帯電話１３００は、筐体の内部あるいは表示部１３０１に、前述の方法を用いて得られる電子基板を備えている。図中、符号１３０２は操作ボタン１３０２、符号１３０３は受話口、符号１３０４は送話口を示している。上記電子基板には、本発明の実装方法を用いて電子部品を実装された電子基板が用いられており、小型で高性能でありかつ信頼性に優れた電子基板により、携帯電話１３００の信頼性を確保しつつその薄型化や小型化、高機能化を実現することができる。 (Electronics)
FIG. 7 is a perspective view showing an example of an electronic apparatus according to the present invention. A cellular phone 1300 shown in this figure is provided with an electronic substrate obtained by using the above-described method in the housing or in the display portion 1301. In the figure, reference numeral 1302 denotes an operation button 1302, reference numeral 1303 denotes a mouthpiece, and reference numeral 1304 denotes a mouthpiece. As the electronic board, an electronic board on which electronic components are mounted using the mounting method of the present invention is used, and the reliability of the mobile phone 1300 is reduced by the small, high-performance and highly reliable electronic board. It is possible to achieve a reduction in thickness, size, and enhancement of functionality while securing the above.

上記実施形態の電子基板は、携帯電話に限らず、電子ブック、パーソナルコンピュータ、ディジタルスチルカメラ、液晶テレビ、ビューファインダ型あるいはモニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャ、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、ＰＯＳ端末、タッチパネルを備えた機器等々、種々の電子機器に適用することができる。いずれの電子機器においても、本発明の電子基板を適用することで、薄型、小型であり信頼性に優れた電子機器を実現することができる。   The electronic board of the above embodiment is not limited to a mobile phone, but an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, The present invention can be applied to various electronic devices such as a word processor, a workstation, a video phone, a POS terminal, and a device having a touch panel. In any electronic device, by applying the electronic substrate of the present invention, it is possible to realize an electronic device that is thin, small, and excellent in reliability.

図１は、第１実施形態に係る電子基板を示す図。FIG. 1 is a view showing an electronic substrate according to the first embodiment. 図２は、第１実施形態の実装方法を示す工程図。FIG. 2 is a process diagram illustrating the mounting method according to the first embodiment. 図３は、第２実施形態に係る電子基板を示す図。FIG. 3 is a view showing an electronic substrate according to the second embodiment. 図４は、第３実施形態に係る電子基板を示す図。FIG. 4 is a view showing an electronic substrate according to a third embodiment. 図５は、第４実施形態に係る電子基板を示す図。FIG. 5 is a view showing an electronic substrate according to a fourth embodiment. 図６は、電子基板の一例を示す部分断面構成図。FIG. 6 is a partial cross-sectional configuration diagram illustrating an example of an electronic substrate. 図７は、電子機器の一例を示す斜視構成図。FIG. 7 is a perspective configuration diagram illustrating an example of an electronic apparatus.

符号の説明Explanation of symbols

１０ ＩＣチップ（電子部品）、１４ 接続端子、２０ 回路基板、３０ スロープ材、３０ａ〜３０ｅ 絶縁層、３０ｓ 溝部、３４ 基板側端子、４０ 絶縁下地膜、４１ａ〜４１ｅ 突出部、１００，２００ 電子基板   DESCRIPTION OF SYMBOLS 10 IC chip (electronic component), 14 Connection terminal, 20 Circuit board, 30 Slope material, 30a-30e Insulating layer, 30s Groove part, 34 Substrate side terminal, 40 Insulating base film, 41a-41e Protruding part, 100, 200 Electronic board

Claims (15)

基板側端子が配列された基板上に、接続端子が配列形成された端子形成面を有する電子部品を実装する方法であって、
前記端子形成面を基板と反対側を向けた状態で前記電子部品を前記基板上に載置する工程と、
前記電子部品の接続端子と、該接続端子に対応する前記基板側端子との間の前記基板上の領域に、前記基板側端子から前記端子形成面につながる斜面を形成する工程と、
前記斜面上に、液滴吐出法を用いて、前記基板側端子と前記接続端子とを接続する配線を形成する工程と、を有し、
前記斜面を形成する工程が、
前記電子部品の接続端子と前記基板側端子との間の前記基板上の領域に、液滴吐出法を用いて絶縁材料を配置し、該絶縁材料の少なくとも一部を硬化させて第１の絶縁層を形成する工程と、前記第１の絶縁層上であって該第１の絶縁層より狭い平面領域に前記絶縁材料を配置し、該絶縁材料の少なくとも一部を硬化させて第２の絶縁層を形成する工程と、を繰り返すことで、前記電子部品の側方に前記絶縁層の積層膜を形成する工程であることを特徴とする電子部品の実装方法。 A method of mounting an electronic component having a terminal formation surface on which connection terminals are arranged on a substrate on which board-side terminals are arranged,
Placing the electronic component on the substrate with the terminal forming surface facing away from the substrate;
Forming a slope leading from the substrate side terminal to the terminal forming surface in a region on the substrate between the connection terminal of the electronic component and the substrate side terminal corresponding to the connection terminal;
Forming a wiring for connecting the substrate side terminal and the connection terminal on the slope using a droplet discharge method,
Forming the slope includes:
An insulating material is disposed in a region on the substrate between the connection terminal of the electronic component and the substrate-side terminal by using a droplet discharge method, and at least a part of the insulating material is cured to provide a first insulation. Forming a layer; and disposing the insulating material on a planar area narrower than the first insulating layer on the first insulating layer, and curing at least a part of the insulating material to form a second insulating material. And a step of forming a layer to repeat the step of forming a laminated film of the insulating layer on the side of the electronic component. 前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる溝部を形成する工程を有し、
前記配線を形成する工程では前記溝部内に前記配線を形成することを特徴とする請求項１に記載の電子部品の実装方法。 Forming a groove connected to the connection terminal from the substrate-side terminal on the slope of the laminated film;
The method for mounting an electronic component according to claim 1, wherein the wiring is formed in the groove in the step of forming the wiring. 前記溝部を形成する工程が、前記積層膜の前記斜面上でレーザ光を走査する工程であることを特徴とする請求項２に記載の電子部品の実装方法。   3. The electronic component mounting method according to claim 2, wherein the step of forming the groove is a step of scanning a laser beam on the inclined surface of the laminated film. 前記積層膜の前記斜面上に、絶縁材料を液滴吐出法を用いて配置し、当該絶縁材料の少なくとも一部を硬化することで、前記基板側端子から前記接続端子につながる絶縁下地膜を形成する工程を有し、
前記配線を形成する工程では前記絶縁下地膜上に前記配線を形成することを特徴とする請求項１に記載の電子部品の実装方法。 An insulating base film connected from the substrate-side terminal to the connection terminal is formed by disposing an insulating material on the inclined surface of the laminated film using a droplet discharge method and curing at least a part of the insulating material. And having a process of
2. The electronic component mounting method according to claim 1, wherein the wiring is formed on the insulating base film in the step of forming the wiring. 前記絶縁下地膜を形成する前記絶縁材料と、前記積層膜を形成する前記絶縁材料とが同一の絶縁材料であることを特徴とする請求項４に記載の電子部品の実装方法。   5. The electronic component mounting method according to claim 4, wherein the insulating material forming the insulating base film and the insulating material forming the laminated film are the same insulating material. 前記斜面を形成する工程において、前記積層膜を構成する前記各絶縁層を、外側に向かって突出する複数の突出部を有する形状に形成するとともに、前記各絶縁層の突出部が前記基板側端子から前記接続端子に向かって平面的に配列されるように前記各絶縁層を積層することで、前記各絶縁層内で隣接する前記突出部を側壁として前記基板側端子から前記接続端子につながる溝部を前記斜面上に形成し、
前記配線を形成する工程では前記溝部内に前記配線を形成することを特徴とする請求項１に記載の電子部品の実装方法。 In the step of forming the slope, the insulating layers constituting the laminated film are formed in a shape having a plurality of protruding portions protruding outward, and the protruding portions of the insulating layers are formed on the substrate-side terminals. By laminating each of the insulating layers so as to be arranged in a plane from the connection terminal to the connection terminal, the groove portion connected to the connection terminal from the substrate-side terminal using the adjacent protruding portion in each insulation layer as a side wall On the slope,
The method for mounting an electronic component according to claim 1, wherein the wiring is formed in the groove in the step of forming the wiring. 前記各絶縁層に３カ所上の前記突出部を形成し、前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる複数の前記溝部を形成することを特徴とする請求項６に記載の電子部品の実装方法。   7. The protrusions at three places are formed in each of the insulating layers, and a plurality of the groove portions connected from the substrate-side terminals to the connection terminals are formed on the slope of the laminated film. The electronic component mounting method described in 1. 前記電子部品を取り囲むように前記積層膜を形成することを特徴とする請求項１から７のいずれか１項に記載の電子部品の実装方法。   8. The electronic component mounting method according to claim 1, wherein the laminated film is formed so as to surround the electronic component. 前記絶縁材料を基板上に配置した後、当該絶縁材料に光を照射することで、前記絶縁材料を部分的に硬化させることを特徴とする請求項１から８のいずれか１項に記載の電子部品の実装方法。   9. The electron according to claim 1, wherein the insulating material is partially cured by irradiating the insulating material with light after the insulating material is disposed on the substrate. Component mounting method. 前記配線を形成した後、
前記電子部品、前記配線、及び前記絶縁層の積層膜を覆うように前記絶縁材料を塗布する工程と、
前記絶縁材料に光を照射して部分的に硬化させて被覆絶縁層を形成する工程と、
前記基板上に形成された前記絶縁層を加熱して硬化させる工程と、
を有することを特徴とする請求項１から９のいずれか１項に記載の電子部品の実装方法。 After forming the wiring,
Applying the insulating material so as to cover the electronic component, the wiring, and the laminated film of the insulating layer;
Irradiating the insulating material with light and partially curing to form a covering insulating layer;
Heating and curing the insulating layer formed on the substrate;
The electronic component mounting method according to any one of claims 1 to 9, wherein the electronic component mounting method is provided. 基板側端子が配列された基板上に、接続端子が配列形成された端子形成面を有する電子部品が実装された電子基板であって、
前記電子部品の側方に、複数の絶縁層を積層してなり、前記基板側端子から該基板側端子に対応する前記接続端子につながる斜面を有する積層膜が形成されており、
前記積層膜の前記斜面上に、前記基板側端子と前記接続端子とを接続する配線が形成されていることを特徴とする電子基板。 An electronic board on which an electronic component having a terminal forming surface on which connection terminals are arranged is mounted on a board on which board-side terminals are arranged,
A plurality of insulating layers are laminated on the side of the electronic component, and a laminated film having a slope connecting from the substrate-side terminal to the connection terminal corresponding to the substrate-side terminal is formed,
An electronic substrate, wherein wiring for connecting the substrate-side terminal and the connection terminal is formed on the inclined surface of the laminated film. 前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる溝部が形成されており、当該溝部内に前記配線が形成されていることを特徴とする請求項１１に記載の電子基板。   12. The electronic substrate according to claim 11, wherein a groove portion connected from the substrate-side terminal to the connection terminal is formed on the slope of the laminated film, and the wiring is formed in the groove portion. . 前記積層膜の前記斜面上に、前記基板側端子から前記接続端子につながる絶縁下地膜が形成され、当該絶縁下地膜上に前記配線が形成されていることを特徴とする請求項１１に記載の電子基板。   The insulating base film connected from the substrate-side terminal to the connection terminal is formed on the slope of the laminated film, and the wiring is formed on the insulating base film. Electronic substrate. 前記積層膜を構成する前記各絶縁層に、当該絶縁層の一部を外側に突出させてなる複数の突出部が形成され、
前記積層膜の前記斜面上で前記各絶縁層の突出部が平面的に配列されて、当該配列された前記突出部を側壁として前記基板側端子から前記接続端子につながる溝部が前記斜面上に形成されており、
前記溝部内に前記配線が形成されていることを特徴とする請求項１１に記載の電子基板。 A plurality of projecting portions formed by projecting a part of the insulating layer outward is formed in each insulating layer constituting the laminated film,
Protrusions of the respective insulating layers are arranged in a plane on the slope of the laminated film, and grooves are formed on the slope from the substrate-side terminals to the connection terminals with the arranged protrusions serving as side walls. Has been
The electronic board according to claim 11, wherein the wiring is formed in the groove. 請求項１１から１４のいずれか１項に記載の電子基板を備えたことを特徴とする電子機器。   An electronic apparatus comprising the electronic substrate according to claim 11.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method
WO2010087336A1 (en) * 2009-01-27 2010-08-05 パナソニック電工株式会社 Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof
JP2012060322A (en) * 2010-09-07 2012-03-22 Toshiba Corp Television receiver and electronic apparatus
WO2012060091A1 (en) * 2010-11-05 2012-05-10 パナソニック株式会社 Method for forming wiring on surface of three-dimensional structure, intermediate structure for obtaining three-dimensional structure provided with wiring on surface thereof, and three-dimensional structure provided with wiring on surface thereof
JP2012511835A (en) * 2008-12-09 2012-05-24 ヴァーティカル・サーキツツ・インコーポレーテッド Semiconductor die interconnects formed by aerosol applications of electrically conductive materials
WO2012093548A1 (en) * 2011-01-06 2012-07-12 富士機械製造株式会社 Film making pattern forming method and film making pattern forming device
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation
JPWO2013168223A1 (en) * 2012-05-08 2015-12-24 富士機械製造株式会社 Semiconductor package and manufacturing method thereof
WO2024039228A1 (en) * 2022-08-18 2024-02-22 엘지이노텍 주식회사 Circuit board and semiconductor package comprising same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003526945A (en) * 2000-03-15 2003-09-09 シン フイルム エレクトロニクス エイエスエイ Electrical interconnection vertical in stacks
JP2005223067A (en) * 2004-02-04 2005-08-18 Seiko Epson Corp Electronic device and its manufacturing method
JP2005251910A (en) * 2004-03-03 2005-09-15 Seiko Epson Corp Circuit board, its manufacturing method, electrooptical device, and electronic apparatus
JP2006147647A (en) * 2004-11-16 2006-06-08 Seiko Epson Corp Packaging board and electronic equipment
JP2006147650A (en) * 2004-11-16 2006-06-08 Seiko Epson Corp Mounting method of electronic element, manufacturing method of electronic device, circuit board, and electronic equipment
JP2006303408A (en) * 2004-09-09 2006-11-02 Seiko Epson Corp Electronic device and its fabrication process
JP2008071902A (en) * 2006-09-13 2008-03-27 Fujifilm Corp Wiring method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003526945A (en) * 2000-03-15 2003-09-09 シン フイルム エレクトロニクス エイエスエイ Electrical interconnection vertical in stacks
JP2005223067A (en) * 2004-02-04 2005-08-18 Seiko Epson Corp Electronic device and its manufacturing method
JP2005251910A (en) * 2004-03-03 2005-09-15 Seiko Epson Corp Circuit board, its manufacturing method, electrooptical device, and electronic apparatus
JP2006303408A (en) * 2004-09-09 2006-11-02 Seiko Epson Corp Electronic device and its fabrication process
JP2006147647A (en) * 2004-11-16 2006-06-08 Seiko Epson Corp Packaging board and electronic equipment
JP2006147650A (en) * 2004-11-16 2006-06-08 Seiko Epson Corp Mounting method of electronic element, manufacturing method of electronic device, circuit board, and electronic equipment
JP2008071902A (en) * 2006-09-13 2008-03-27 Fujifilm Corp Wiring method

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation
JP2012511835A (en) * 2008-12-09 2012-05-24 ヴァーティカル・サーキツツ・インコーポレーテッド Semiconductor die interconnects formed by aerosol applications of electrically conductive materials
US8482137B2 (en) 2009-01-27 2013-07-09 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
KR101359117B1 (en) * 2009-01-27 2014-02-05 파나소닉 주식회사 Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof
US9795033B2 (en) 2009-01-27 2017-10-17 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
WO2010087336A1 (en) * 2009-01-27 2010-08-05 パナソニック電工株式会社 Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
JPWO2010087336A1 (en) * 2009-01-27 2012-08-02 パナソニック株式会社 Semiconductor chip mounting method, semiconductor device obtained by using the method, semiconductor chip connection method, three-dimensional structure provided with wiring on the surface, and manufacturing method thereof
US8901728B2 (en) 2009-01-27 2014-12-02 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
CN102282661A (en) * 2009-01-27 2011-12-14 松下电工株式会社 Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof
KR101284376B1 (en) * 2009-01-27 2013-07-09 파나소닉 주식회사 Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof
TWI452641B (en) * 2009-01-27 2014-09-11 Panasonic Corp Semiconductor wafer packaging method, semiconductor wafer connection method and three-dimensional structure of the system method
US8759148B2 (en) 2009-01-27 2014-06-24 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US8451613B2 (en) 2010-09-07 2013-05-28 Kabushiki Kaisha Toshiba Television and electronic apparatus
JP2012060322A (en) * 2010-09-07 2012-03-22 Toshiba Corp Television receiver and electronic apparatus
WO2012060091A1 (en) * 2010-11-05 2012-05-10 パナソニック株式会社 Method for forming wiring on surface of three-dimensional structure, intermediate structure for obtaining three-dimensional structure provided with wiring on surface thereof, and three-dimensional structure provided with wiring on surface thereof
JP2012142525A (en) * 2011-01-06 2012-07-26 Fuji Mach Mfg Co Ltd Film formation pattern forming method and film formation pattern forming device
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