JP2007281116A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2007281116A
JP2007281116A JP2006103818A JP2006103818A JP2007281116A JP 2007281116 A JP2007281116 A JP 2007281116A JP 2006103818 A JP2006103818 A JP 2006103818A JP 2006103818 A JP2006103818 A JP 2006103818A JP 2007281116 A JP2007281116 A JP 2007281116A
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semiconductor
semiconductor structure
base plate
liquid adhesive
adhesive
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Takeshi Wakabayashi
猛 若林
Osamu Okada
修 岡田
Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means to adhere a semiconductor construct called CSP on a base plate via an adhesive layer so that it may not likely to be inclined. <P>SOLUTION: In each of a plurality of semiconductor construct arrangement regions 31 on top face of the base plate 1, a liquid adhesive 33 is applied in a distributed manner at a plurality of places using a jet type dispenser. Then, using a die bonder, semiconductor constructs 2 are arranged being away from each other on the liquid adhesive 33 applied in the semiconductor construct arrangement regions 31 on top face of the base plate 1, with one semiconductor construct 2 on each semiconductor construct arrangement region 31. Under heat and pressure, the bottom faces of silicon substrates 4 of the semiconductor constructs 2 are pushed against the liquid adhesive 33 to half-cure the liquid adhesive 33. In this case, the swelling-out of the liquid adhesive 33 applied in a distributed manner at a plurality of places in each semiconductor construct arrangement region 31 can be made relatively small and can be uniformed and thereby the semiconductor constructs 2 are not like to be inclined. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

従来の半導体装置には、シリコン基板のサイズ外にも外部接続用接続端子としての半田ボールを備えるため、シリコン基板上に複数の柱状電極を有する半導体構成体をそれよりも平面サイズの大きいベース板の上面に接着層を介して接着し、半導体構成体の周囲におけるベース板の上面に絶縁層を設け、半導体構成体および絶縁層上に上層絶縁膜を設け、上層絶縁膜の上面に上層配線を半導体構成体の柱状電極に接続させて設け、上層配線の接続パッド部を除く部分を最上層絶縁膜で覆い、上層配線の接続パッド部上に半田ボールを設けたものがある（例えば、特許文献１参照）。   Since conventional semiconductor devices include solder balls as connection terminals for external connection in addition to the size of the silicon substrate, a semiconductor substrate having a plurality of columnar electrodes on the silicon substrate is a base plate having a larger planar size than that. Is bonded to the upper surface of the semiconductor substrate through an adhesive layer, an insulating layer is provided on the upper surface of the base plate around the semiconductor structure, an upper insulating film is provided on the semiconductor structure and the insulating layer, and an upper wiring is provided on the upper surface of the upper insulating film. Some are provided by connecting to the columnar electrode of the semiconductor structure, covering the upper layer wiring except for the connection pad portion with the uppermost insulating film, and providing the solder ball on the connection pad portion of the upper layer wiring (for example, Patent Documents) 1).

特開２００４−２２０４１７号公報JP 2004-220417 A

ところで、上記従来の半導体装置の製造方法では、接着層の形成方法として（第２７段落参照）、ウエハ状態のシリコン基板の下面に接着層を接着する（接着層は、エポキシ系樹脂等のダイボンド材からなるものであり、加熱加圧により、仮硬化した状態でシリコン基板に固着する）と記載され、具体的な形成方法は記載されていないが、例えば、接着シートをウエハ状態のシリコン基板の下面に貼り付ける方法が一般的である。   By the way, in the above conventional method for manufacturing a semiconductor device, as an adhesive layer forming method (see paragraph 27), an adhesive layer is bonded to the lower surface of a silicon substrate in a wafer state (the adhesive layer is a die bond material such as an epoxy resin). And is fixed to the silicon substrate in a pre-cured state by heating and pressing), and a specific formation method is not described. For example, an adhesive sheet is attached to the lower surface of a silicon substrate in a wafer state. The method of pasting to is common.

しかるに、このような接着シート貼り付け方法では、接着シートをウエハ状態のシリコン基板の下面に貼り付ける際に、接着シートとウエハ状態のシリコン基板との間に空気が侵入し易く、均一な接着が困難であり、しかも半導体構成体をベース板の上面に接着シートを介して配置した後の加熱工程において侵入した空気が膨張し、半導体構成体が傾き、それ以後の工程に支障を来すことがあるという問題がある。   However, in such an adhesive sheet attaching method, when the adhesive sheet is attached to the lower surface of the wafer-state silicon substrate, air easily enters between the adhesive sheet and the wafer-state silicon substrate, and uniform adhesion is achieved. It is difficult, and the air that has entered in the heating process after the semiconductor structure is placed on the upper surface of the base plate via the adhesive sheet expands, the semiconductor structure tilts, and the subsequent processes may be hindered. There is a problem that there is.

一方、最近では、圧縮空気でピストンを移動させるタイプのディスペンサを用いて、ベース板の上面の各半導体構成体配置領域に液状接着剤を塗布し、この塗布された液状接着剤上に半導体構成体を配置して接着する方法が検討されている。この場合、ベース板をＸ、Ｙ、θ方向に移動可能なテーブルの上面に真空吸着させて配置し、テーブルを移動させながら、ディスペンサのニードルから液状接着剤を１回ずつ吐出させてベース板の上面の各半導体構成体配置領域の１箇所に点状または線状に塗布し、この塗布された液状接着剤上に半導体構成体を接着させて配置することになる。   On the other hand, recently, using a dispenser that moves the piston with compressed air, a liquid adhesive is applied to each semiconductor component arrangement region on the upper surface of the base plate, and the semiconductor component is applied on the applied liquid adhesive. A method of arranging and adhering is being studied. In this case, the base plate is placed on the upper surface of the table movable in the X, Y, and θ directions by vacuum suction, and while moving the table, the liquid adhesive is discharged from the needle of the dispenser once by one time. It is applied in a dotted or linear manner to one location of each semiconductor constituent arrangement region on the upper surface, and the semiconductor constituent is adhered and arranged on the applied liquid adhesive.

しかしながら、このような接着剤塗布方法では、ディスペンサのニードルから液状接着剤を１回ずつ吐出させてベース板の上面の各半導体構成体配置領域の１箇所に点状または線状に塗布しているので、この塗布された液状接着剤の盛り上がりが比較的大きくなり、ひいてはベース板の上面に接着層を介して接着された半導体構成体が傾くため、やはり、それ以後の工程に完全に支障がないまでには至っていない。   However, in such an adhesive application method, the liquid adhesive is discharged once from the needle of the dispenser and applied in a dotted or linear manner to one location of each semiconductor component arrangement region on the upper surface of the base plate. Therefore, the swell of the applied liquid adhesive becomes relatively large, and as a result, the semiconductor structure bonded to the upper surface of the base plate via the adhesive layer is inclined, so that the subsequent processes are not completely hindered. It has not yet reached.

そこで、この発明は、ベース板の上面に接着層を介して接着された半導体構成体が傾きにくいようにすることができる半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a semiconductor structure bonded to the upper surface of a base plate via an adhesive layer can be made difficult to tilt.

この発明は、上記目的を達成するため、ベース板上の複数の半導体構成体配置領域の各々の複数の箇所に液状接着剤を分散させて塗布する工程と、前記ベース板上の各半導体構成体配置領域に、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を前記塗布された液状接着剤からなる接着層により固定する工程と、前記半導体構成体の上部側に少なくとも１層の上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、前記半導体構成体間における前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、を有することを特徴とするものである。   In order to achieve the above object, the present invention includes a step of dispersing and applying a liquid adhesive to a plurality of locations in each of a plurality of semiconductor structure arrangement regions on a base plate, and each semiconductor structure on the base plate Fixing a plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate to an arrangement region with an adhesive layer made of the applied liquid adhesive; and the semiconductor Forming at least one upper layer wiring on the upper side of the structure by connecting to an external connection electrode of the semiconductor structure; cutting the base plate between the semiconductor structures; And a step of obtaining a plurality of semiconductor devices included in at least one.

この発明によれば、ベース板上の複数の半導体構成体配置領域の各々の複数の箇所に液状接着剤を分散させて塗布しているので、１つの半導体構成体配置領域の複数の箇所に分散して塗布された液状接着剤の盛り上がりを比較的小さく且つほぼ均一にすることができ、ひいてはベース板の上面に接着層を介して接着された半導体構成体が傾きにくいようにすることができる。   According to the present invention, since the liquid adhesive is dispersed and applied to each of the plurality of locations of the plurality of semiconductor structure arrangement regions on the base plate, the liquid adhesive is distributed to the plurality of locations of one semiconductor structure placement region. Thus, the swell of the applied liquid adhesive can be made relatively small and almost uniform, and as a result, the semiconductor structure bonded to the upper surface of the base plate via the adhesive layer can be made difficult to tilt.

図１はこの発明の製造方法により製造された半導体装置の第１の例の断面部を示す。この半導体装置は、ガラス布基材エポキシ樹脂等からなる平面方形状のベース板１を備えている。ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面がエポキシ系樹脂等からなる接着層３を介して接着されている。   FIG. 1 shows a cross section of a first example of a semiconductor device manufactured by the manufacturing method of the present invention. This semiconductor device includes a planar rectangular base plate 1 made of glass cloth base epoxy resin or the like. On the upper surface of the base plate 1, the lower surface of the planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded via an adhesive layer 3 made of epoxy resin or the like.

半導体構成体２は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、シリコン基板（半導体基板）４を備えている。シリコン基板４の下面は接着層３を介してベース板１の上面に接着されている。シリコン基板４の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。   The semiconductor structure 2 is generally called a CSP (chip size package) and includes a silicon substrate (semiconductor substrate) 4. The lower surface of the silicon substrate 4 is bonded to the upper surface of the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。絶縁膜６の上面にはポリイミド系樹脂等からなる保護膜８が設けられている。絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。   An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes. A protective film 8 made of polyimide resin or the like is provided on the upper surface of the insulating film 6. An opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6.

保護膜８の上面には銅等からなる下地金属層１０が設けられている。下地金属層１０の上面全体には銅からなる配線１１が設けられている。下地金属層１０を含む配線１１の一端部は、絶縁膜６および保護膜８の開口部７、９を介して接続パッド５に接続されている。配線１１の接続パッド部上面には銅からなる柱状電極（外部接続用電極）１２が設けられている。配線１１を含む保護膜８の上面にはエポキシ系樹脂等からなる封止膜１３がその上面が柱状電極１２の上面と面一となるように設けられている。   A base metal layer 10 made of copper or the like is provided on the upper surface of the protective film 8. A wiring 11 made of copper is provided on the entire upper surface of the base metal layer 10. One end of the wiring 11 including the base metal layer 10 is connected to the connection pad 5 through the openings 7 and 9 of the insulating film 6 and the protective film 8. A columnar electrode (external connection electrode) 12 made of copper is provided on the upper surface of the connection pad portion of the wiring 11. A sealing film 13 made of an epoxy resin or the like is provided on the upper surface of the protective film 8 including the wiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 12.

ここで、上面に集積回路を有するシリコン基板４、接続パッド５、絶縁膜６、保護膜８、下地金属層１０、配線１１、柱状電極１２および封止膜１３により、一般的にはＣＳＰと呼ばれる半導体構成体２が構成されている。   Here, the silicon substrate 4 having an integrated circuit on the upper surface, the connection pad 5, the insulating film 6, the protective film 8, the base metal layer 10, the wiring 11, the columnar electrode 12, and the sealing film 13 are generally called CSP. A semiconductor structure 2 is configured.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の絶縁層２１が設けられている。絶縁層２１は、例えば、エポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂中にシリカフィラー等の無機材料からなる補強材を分散されたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   A rectangular frame-shaped insulating layer 21 is provided on the upper surface of the base plate 1 around the semiconductor structure 2. The insulating layer 21 is, for example, a material in which a reinforcing material made of an inorganic material such as silica filler is dispersed in a thermosetting resin such as an epoxy resin or a polyimide resin, or only a thermosetting resin such as an epoxy resin. It is made up of.

半導体構成体２および絶縁層２１の上面には上層絶縁膜２２がその上面を平坦とされて設けられている。上層絶縁膜２２は、例えば、ガラス布やガラス繊維等からなる基材にエポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂を含浸されたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   An upper insulating film 22 is provided on the upper surface of the semiconductor structure 2 and the insulating layer 21 so that the upper surface is flat. The upper insulating film 22 is, for example, a substrate made of glass cloth or glass fiber impregnated with a thermosetting resin such as an epoxy resin or a polyimide resin, or only a thermosetting resin such as an epoxy resin. It is made up of.

半導体構成体２の柱状電極１２の上面中央部に対応する部分における上層絶縁膜２２には開口部２３が設けられている。上層絶縁膜２２の上面には銅等からなる上層下地金属層２４が設けられている。上層下地金属層２４の上面全体には銅からなる上層配線２５が設けられている。上層下地金属層２４を含む上層配線２５の一端部は、上層絶縁膜２２の開口部２３を介して半導体構成体２の柱状電極１２の上面に接続されている。   An opening 23 is provided in the upper insulating film 22 in a portion corresponding to the central portion of the upper surface of the columnar electrode 12 of the semiconductor structure 2. An upper base metal layer 24 made of copper or the like is provided on the upper surface of the upper insulating film 22. An upper layer wiring 25 made of copper is provided on the entire upper surface of the upper base metal layer 24. One end of the upper wiring 25 including the upper base metal layer 24 is connected to the upper surface of the columnar electrode 12 of the semiconductor structure 2 through the opening 23 of the upper insulating film 22.

上層配線２５を含む上層絶縁膜２２の上面にはソルダーレジスト等からなる最上層絶縁膜２６が設けられている。上層配線２５の接続パッド部に対応する部分における最上層絶縁膜２６には開口部２７が設けられている。最上層絶縁膜２６の開口部２７内およびその上方には半田ボール２８が上層配線２５の接続パッド部に接続されて設けられている。   An uppermost insulating film 26 made of solder resist or the like is provided on the upper surface of the upper insulating film 22 including the upper wiring 25. An opening 27 is provided in the uppermost insulating film 26 in a portion corresponding to the connection pad portion of the upper layer wiring 25. Solder balls 28 are provided connected to the connection pad portions of the upper wiring 25 in and above the opening 27 of the uppermost insulating film 26.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、図１に示す完成された半導体装置を複数個形成することが可能な面積を有するベース板１を用意する。ベース板１は、限定する意味ではないが、例えば、平面方形状である。ベース板１は、ガラス布等からなる基材にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を硬化させてシート状となしたものである。なお、図２において、符号３１で示す領域は、ベース板１の上面の半導体構成体配置領域である。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a base plate 1 having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 1 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape. The base plate 1 is a sheet formed by impregnating a base material made of glass cloth or the like with a thermosetting resin such as an epoxy resin and curing the thermosetting resin. In FIG. 2, a region indicated by reference numeral 31 is a semiconductor structure arrangement region on the upper surface of the base plate 1.

次に、ベース板１の上面の複数の半導体構成体配置領域３１の各々の複数の箇所に液状接着剤３２を分散させて塗布する。この場合、塗布された液状接着剤３２はその表面張力によりドーム状となる。液状接着剤３２の塗布方法としては、ジェットタイプのディスペンサのジェットヘッド３をベース板１の上面の各半導体構成体配置領域３１の複数の箇所に順次移動させ、ジェットヘッド３２からエポキシ系樹脂等からなる液状接着剤を噴射させてベース板１の上面の各半導体構成体配置領域３１の複数の箇所に分散させて塗布することができる。   Next, the liquid adhesive 32 is dispersed and applied to a plurality of locations in each of the plurality of semiconductor structure arrangement regions 31 on the upper surface of the base plate 1. In this case, the applied liquid adhesive 32 has a dome shape due to its surface tension. As a method for applying the liquid adhesive 32, the jet head 3 of the jet type dispenser is sequentially moved to a plurality of locations in each semiconductor component arrangement region 31 on the upper surface of the base plate 1. The liquid adhesive to be formed can be sprayed and dispersed and applied to a plurality of locations in each semiconductor component arrangement region 31 on the upper surface of the base plate 1.

ここで、ジェットタイプのディスペンサは、簡単に説明すると、ジェットヘッド３のノズルの上方に配置されたチャンバ内に供給された液状接着剤をシャフトの急速な下降により下方に向かって打ち出し、ノズルから液状接着剤を下方に向かって噴射させるようにしたものである。このタイプのディスペンサの場合、１回の噴射量は、チャンバ内に１回で供給される液状接着剤の量等で調整可能であり、最低噴射量は例えば３．６ナノリッター程度と極めて少量とすることが可能である。   Here, the jet type dispenser is simply described. The liquid adhesive supplied into the chamber disposed above the nozzle of the jet head 3 is ejected downward by the rapid lowering of the shaft, and the liquid is discharged from the nozzle. The adhesive is jetted downward. In the case of this type of dispenser, the amount of injection at one time can be adjusted by the amount of liquid adhesive supplied into the chamber at one time, and the minimum injection amount is, for example, about 3.6 nanoliters and a very small amount. Is possible.

ベース板１への塗布は、ベース板１に対してディスペンサを移動しながら１つの半導体構成体配置領域３１の複数の箇所に、例えば、ドットマトリクス状に液状接着剤３２を分散させて塗布する。半導体構成体配置領域３１の平面サイズは０．７５ｍｍ□〜１０ｍｍ□以上と種々あるが、最低でも各辺または各角に対応して１ドット、換言すれば、４ドットの塗布を行うことが望ましい。但し、半導体構成体配置領域３１が極めて細い長方形状であるような場合には、長手方向に沿って２ドット以上、好ましくは３ドット以上塗布するようにしても差し支えは無い。   Application to the base plate 1 is performed by dispersing the liquid adhesive 32 in a dot matrix, for example, at a plurality of locations in one semiconductor component arrangement region 31 while moving the dispenser relative to the base plate 1. There are various plane sizes of the semiconductor structure arrangement region 31 of 0.75 mm □ to 10 mm □ or more, but it is desirable to apply at least one dot corresponding to each side or each corner, in other words, four dots. . However, in the case where the semiconductor component arrangement region 31 has a very thin rectangular shape, there is no problem even if it is applied in the longitudinal direction by 2 dots or more, preferably 3 dots or more.

次に、図３に示すように、半導体構成体２を用意する。この場合、半導体構成体２は、ウエハ状態のシリコン基板７上に集積回路（図示せず）、接続パッド５、絶縁膜６、保護膜８、下地金属層１０、配線１１、柱状電極１２および封止膜１３を形成した後、ダイシングにより個片化することにより得られる。上述の特許文献１には、半導体構成体２の製造方法が詳述されている。   Next, as shown in FIG. 3, a semiconductor structure 2 is prepared. In this case, the semiconductor structure 2 has an integrated circuit (not shown), a connection pad 5, an insulating film 6, a protective film 8, a base metal layer 10, a wiring 11, a columnar electrode 12, and a seal on a silicon substrate 7 in a wafer state. After forming the stop film 13, it is obtained by dividing into pieces by dicing. Patent Document 1 described above details the method for manufacturing the semiconductor structure 2.

次に、ダイボンダー（図示せず）を用いて、ベース板１の上面の各半導体構成体配置領域３１に塗布された液状接着剤３３上に半導体構成体２を相互に離間させて１つずつ配置し、且つ、加熱加圧により、半導体構成体２のシリコン基板４の下面を液状接着剤３３に押し付けながら液状接着剤３３を半硬化させる。したがって、この状態では、図４に示すように、ベース板１の上面の各半導体構成体配置領域３１に半導体構成体２のシリコン基板４の下面が接着層３を介して仮接着される。   Next, using a die bonder (not shown), the semiconductor components 2 are arranged one by one on the liquid adhesive 33 applied to each semiconductor component arrangement region 31 on the upper surface of the base plate 1. In addition, the liquid adhesive 33 is semi-cured by pressing the lower surface of the silicon substrate 4 of the semiconductor structure 2 against the liquid adhesive 33 by heating and pressing. Therefore, in this state, as shown in FIG. 4, the lower surface of the silicon substrate 4 of the semiconductor structure 2 is temporarily bonded via the adhesive layer 3 to each semiconductor structure arrangement region 31 on the upper surface of the base plate 1.

次に、オーブン（図示せず）を用いた加熱加圧により、接着層３を本硬化させる。この状態では、接着層３は、半導体構成体２の外側に食み出さず、ベース板１の上面の半導体構成体配置領域３１のほぼ全域に一様の厚さで形成される方が望ましい。この状態における接着層３の厚さは、膜厚の均一性および接着力を確保するうえで、２５μｍ未満とすることが望ましく、より好ましくは５〜２０μｍとすることが適切である。   Next, the adhesive layer 3 is fully cured by heat and pressure using an oven (not shown). In this state, it is desirable that the adhesive layer 3 does not protrude to the outside of the semiconductor structure 2 and is formed with a uniform thickness over almost the entire semiconductor structure arrangement region 31 on the upper surface of the base plate 1. The thickness of the adhesive layer 3 in this state is desirably less than 25 μm, more preferably 5 to 20 μm, in order to ensure the uniformity of the film thickness and the adhesive force.

このように、ベース板１の上面の複数の半導体構成体配置領域３１の各々の複数の箇所に液状接着剤３３を分散させて塗布しているので、１つの半導体構成体配置領域３１の複数の箇所に分散して塗布された液状接着剤３３の盛り上がりを比較的小さく且つほぼ均一にすることができ、ひいてはベース板１の上面に接着層３を介して接着された半導体構成体２が傾きにくいようにすることができ、これ以後の工程に支障を来さないようにすることができる。   Thus, since the liquid adhesive 33 is dispersed and applied to a plurality of locations of each of the plurality of semiconductor structure arrangement regions 31 on the upper surface of the base plate 1, the plurality of semiconductor structure arrangement regions 31 of the one semiconductor structure arrangement region 31 are applied. The swell of the liquid adhesive 33 applied in a dispersed manner can be made relatively small and substantially uniform, and as a result, the semiconductor structure 2 bonded to the upper surface of the base plate 1 via the adhesive layer 3 is difficult to tilt. Thus, the subsequent processes can be prevented from being hindered.

次に、図５に示すように、半導体構成体２の周囲におけるベース板１の上面に格子状の絶縁層形成用シート２１ａをピン等で位置決めしながら配置する。格子状の絶縁層形成用シート２１ａは、熱硬化性樹脂中に補強材を分散させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。次に、半導体構成体２および絶縁層形成用層２１ａの上面に上層絶縁膜形成用シート２２ａを配置する。上層絶縁膜形成用シート２２ａは、ガラス布等にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。   Next, as shown in FIG. 5, a lattice-shaped insulating layer forming sheet 21 a is arranged on the upper surface of the base plate 1 around the semiconductor structure 2 while being positioned with pins or the like. The lattice-shaped insulating layer forming sheet 21a is a sheet in which a reinforcing material is dispersed in a thermosetting resin and the thermosetting resin is semi-cured. Next, the upper insulating film forming sheet 22a is disposed on the upper surfaces of the semiconductor structure 2 and the insulating layer forming layer 21a. The upper insulating film forming sheet 22a is formed by impregnating a glass cloth or the like with a thermosetting resin such as an epoxy resin to make the thermosetting resin into a semi-cured state into a sheet shape.

次に、一対の加熱加圧板３４、３５を用いて上下から絶縁層形成用層２１ａおよび上層絶縁膜形成用シート２２ａを加熱加圧する。そして、その後の冷却により、半導体構成体２の周囲におけるベース板１の上面に絶縁層２１が形成され、また、半導体構成体２および絶縁層２１の上面に上層絶縁膜２２が形成される。この場合、上層絶縁膜２２の上面は、上側の加熱加圧板３４の下面によって押さえ付けられるため、平坦面となる。したがって、上層絶縁膜２２の上面を平坦化するための研磨工程は不要である。   Next, the insulating layer forming layer 21a and the upper insulating film forming sheet 22a are heated and pressed from above and below using a pair of heating and pressing plates 34 and 35. Then, by subsequent cooling, an insulating layer 21 is formed on the upper surface of the base plate 1 around the semiconductor structure 2, and an upper insulating film 22 is formed on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. In this case, since the upper surface of the upper insulating film 22 is pressed by the lower surface of the upper heating / pressing plate 34, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the upper insulating film 22 is not necessary.

次に、図６に示すように、レーザビームを照射するレーザ加工により、半導体構成体２の柱状電極１２の上面中央部に対応する部分における上層絶縁膜２２に開口部２３を形成する。次に、必要に応じて、開口部２３内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 6, an opening 23 is formed in the upper insulating film 22 in a portion corresponding to the central portion of the upper surface of the columnar electrode 12 of the semiconductor structure 2 by laser processing with laser beam irradiation. Next, the epoxy smear etc. which generate | occur | produced in the opening part 23 etc. are removed by a desmear process as needed.

次に、図７に示すように、上層絶縁膜２２の開口部２３を介して露出された柱状電極１２の上面を含む上層絶縁膜２２の上面全体に、銅の無電解メッキ等により、上層下地金属層２４を形成する。次に、上層下地金属層２４の上面にメッキレジスト膜３６をパターン形成る。この場合、上層配線２５形成領域に対応する部分におけるメッキレジスト膜３６には開口部３７が形成されている。   Next, as shown in FIG. 7, the entire upper surface of the upper insulating film 22 including the upper surface of the columnar electrode 12 exposed through the opening 23 of the upper insulating film 22 is coated with an upper layer base by electroless plating of copper or the like. A metal layer 24 is formed. Next, a plating resist film 36 is patterned on the upper surface of the upper base metal layer 24. In this case, an opening 37 is formed in the plating resist film 36 in a portion corresponding to the upper layer wiring 25 formation region.

次に、下地金属層２４をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３６の開口部３７内の上層下地金属層２４の上面に上層配線２５を形成する。次に、メッキレジスト膜３６を剥離し、次いで、上層配線２５をマスクとして下地金属層２４の不要な部分をエッチングして除去すると、図８に示すように、上層配線２５下にのみ上層下地金属層２４が残存される。   Next, by performing electrolytic plating of copper using the base metal layer 24 as a plating current path, the upper wiring 25 is formed on the upper surface of the upper base metal layer 24 in the opening 37 of the plating resist film 36. Next, the plating resist film 36 is peeled off, and then unnecessary portions of the base metal layer 24 are removed by etching using the upper layer wiring 25 as a mask. As shown in FIG. Layer 24 remains.

次に、図９に示すように、スクリーン印刷法やスピンコーティング法等により、上層配線２５を含む上層絶縁膜２２の上面にソルダーレジスト等からなる最上層絶縁膜２６を形成する。この場合、上層配線２５の接続パッド部に対応する部分における最上層絶縁膜２６には開口部２７が形成されている。   Next, as shown in FIG. 9, an uppermost insulating film 26 made of a solder resist or the like is formed on the upper surface of the upper insulating film 22 including the upper wiring 25 by a screen printing method, a spin coating method, or the like. In this case, an opening 27 is formed in the uppermost insulating film 26 in a portion corresponding to the connection pad portion of the upper layer wiring 25.

次に、最上層絶縁膜２６の開口部２７内およびその上方に半田ボール２８を上層配線２５の接続パッド部に接続させて形成する。次に、図１０に示すように、互いに隣接する半導体構成体２間において、最上層絶縁膜２６、上層絶縁膜２２、絶縁層２１およびベース板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, solder balls 28 are formed in and above the opening 27 of the uppermost insulating film 26 so as to be connected to the connection pad portion of the upper wiring 25. Next, as shown in FIG. 10, when the uppermost insulating film 26, the upper insulating film 22, the insulating layer 21, and the base plate 1 are cut between adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 1 are obtained. Can be obtained.

なお、上記では、図２〜図４に示すように、ジェットヘッド３２を用いて、ベース板１の上面の各半導体構成体配置領域３１の複数の箇所に液状接着剤３２を分散させて塗布し、次いで、ダイボンダーを用いて、ベース板１の上面の各半導体構成体配置領域３１に塗布された液状接着剤３３上に半導体構成体２を相互に離間させて１つずつ配置し、且つ、加熱加圧により、半導体構成体２のシリコン基板４の下面を液状接着剤３３に押し付けながら液状接着剤３３を半硬化させて接着層３を形成し、次いで、オーブンを用いた加熱加圧により接着層３を本硬化させる場合について説明したが、これに限定されるものではない。   In the above, as shown in FIG. 2 to FIG. 4, the liquid adhesive 32 is dispersed and applied to a plurality of locations of each semiconductor component arrangement region 31 on the upper surface of the base plate 1 using the jet head 32. Then, using the die bonder, the semiconductor structures 2 are arranged one by one on the liquid adhesive 33 applied to each semiconductor structure arrangement region 31 on the upper surface of the base plate 1 and heated. By pressing, the liquid adhesive 33 is semi-cured while pressing the lower surface of the silicon substrate 4 of the semiconductor structure 2 against the liquid adhesive 33 to form the adhesive layer 3, and then the adhesive layer is heated and pressed using an oven. Although the case where 3 was fully hardened was demonstrated, it is not limited to this.

例えば、ジェットヘッド３２を用いて、ベース板１の上面の各半導体構成体配置領域３１の複数の箇所に液状接着剤３２を分散させて塗布し、次いで、この塗布された液状接着剤３２を半硬化させ、次いで、ダイボンダーを用いて、ベース板１の上面の各半導体構成体配置領域３１に設けられた液状接着剤３３上に半導体構成体２を相互に離間させて１つずつ配置し、且つ、加熱加圧により、半導体構成体２のシリコン基板４の下面を液状接着剤３３に押し付けながら液状接着剤３３を本硬化させて接着層３を形成するようにしてもよい。   For example, by using the jet head 32, the liquid adhesive 32 is dispersed and applied to a plurality of locations of each semiconductor component arrangement region 31 on the upper surface of the base plate 1, and then the applied liquid adhesive 32 is semi-finished. And then, using a die bonder, the semiconductor structures 2 are arranged one by one on the liquid adhesive 33 provided in each semiconductor structure arrangement area 31 on the upper surface of the base plate 1, and The adhesive layer 3 may be formed by main curing the liquid adhesive 33 while pressing the lower surface of the silicon substrate 4 of the semiconductor structure 2 against the liquid adhesive 33 by heat and pressure.

また、ジェットヘッド３２を用いて、ベース板１の上面の１つの半導体構成体配置領域３１の複数の箇所に液状接着剤３２を分散させて塗布し、次いで、ダイボンダーを用いて、ベース板１の上面の当該半導体構成体配置領域３１に塗布された液状接着剤３３上に半導体構成体２を配置し、且つ、加熱加圧により、半導体構成体２のシリコン基板４の下面を液状接着剤３３に押し付けながら液状接着剤３３を半硬化させて接着層３を形成し、これを繰り返した後に、オーブンを用いた加熱加圧により接着層３を本硬化させるようにしてもよい。   Further, using the jet head 32, the liquid adhesive 32 is dispersed and applied to a plurality of locations in one semiconductor component arrangement region 31 on the upper surface of the base plate 1, and then the base plate 1 is coated using a die bonder. The semiconductor structure 2 is disposed on the liquid adhesive 33 applied to the semiconductor structure arrangement region 31 on the upper surface, and the lower surface of the silicon substrate 4 of the semiconductor structure 2 is applied to the liquid adhesive 33 by heating and pressing. The liquid adhesive 33 may be semi-cured while being pressed to form the adhesive layer 3, and after repeating this, the adhesive layer 3 may be fully cured by heating and pressing using an oven.

このようにした場合には、ベース板１の上面の１つの半導体構成体配置領域３１の複数の箇所に塗布された液状接着剤３２の乾燥または硬化が開始する前に、当該半導体構成体配置領域３１上に接着層３を介して半導体構成体２を搭載するため、安定した接着力および搭載状態（接着層３の平面形状、厚さ、半導体構成体３の外側への食み出し等）を得ることができる。   In such a case, before the drying or curing of the liquid adhesive 32 applied to a plurality of locations of one semiconductor structure arrangement area 31 on the upper surface of the base plate 1 starts, the semiconductor structure arrangement area 31. Since the semiconductor structure 2 is mounted on the adhesive layer 3 on the surface 31, stable adhesive force and mounting state (planar shape and thickness of the adhesive layer 3, protrusion of the semiconductor structure 3 to the outside, etc.) Obtainable.

次に、図１１はこの発明の製造方法により製造された半導体装置の第２の例の断面部を示す。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板１の上面に銅箔等からなるべた状の金属層２９を設け、金属層２９の上面に導電性接着層３ａを介して半導体構成体２を設けた点である。この場合の製造方法は、図２に示すような工程において、ベース板１の上面にパターン形成された金属層２９の上面の複数の箇所に銀ペースト、銅ペースト等からなる導電性ペースト（液状導電性接着剤）を分散させて塗布すればよく、その詳細な説明を省略する。   Next, FIG. 11 shows a cross section of a second example of the semiconductor device manufactured by the manufacturing method of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a solid metal layer 29 made of copper foil or the like is provided on the upper surface of the base plate 1 and the upper surface of the metal layer 29 is interposed via a conductive adhesive layer 3a. The semiconductor structure 2 is provided. In the manufacturing method in this case, in a process as shown in FIG. 2, a conductive paste (liquid conductive material) made of silver paste, copper paste or the like is formed at a plurality of locations on the upper surface of the metal layer 29 patterned on the upper surface of the base plate 1. The adhesive may be applied in a dispersed manner, and detailed description thereof is omitted.

ところで、この半導体装置では、半導体構成体２のシリコン基板４下に導電性接着層３ａを介して設けられた金属層２９を放熱板として使用することができる。また、半導体構成体２のシリコン基板４の代わりに、図示していないが、ＳＯＩ(silicon on insulator)と呼ばれるもので、半導体基板上に絶縁膜を設け、絶縁膜上に薄膜トランジスタを形成してなるＳＯＩ集積回路部を設けた構造のＳＯＩ基板を用いる場合には、金属板２９を半導体基板の電位の安定化を図るためのものとして使用することができる。   By the way, in this semiconductor device, the metal layer 29 provided under the silicon substrate 4 of the semiconductor structure 2 via the conductive adhesive layer 3a can be used as a heat sink. Further, although not shown, instead of the silicon substrate 4 of the semiconductor structure 2, it is called SOI (silicon on insulator), and an insulating film is provided on the semiconductor substrate, and a thin film transistor is formed on the insulating film. When an SOI substrate having a structure in which an SOI integrated circuit portion is provided is used, the metal plate 29 can be used for stabilizing the potential of the semiconductor substrate.

次に、図１２はこの発明の製造方法により製造された半導体装置の第３の例の断面部を示す。この半導体装置において、図１に示す半導体装置と大きく異なる点は、上層絶縁膜および上層配線を２層とした点である。すなわち、第１の上層絶縁膜２２Ａの上面には第１の上層下地金属層２４Ａを含む第１の上層配線２５Ａが設けられている。第１の上層下地金属層２４Ａを含む第１の上層配線２５Ａの一端部は、第１の上層絶縁膜２２Ａの開口部２３Ａを介して半導体構成体２の柱状電極１２の上面に接続されている。   Next, FIG. 12 shows a cross section of a third example of the semiconductor device manufactured by the manufacturing method of the present invention. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that the upper insulating film and the upper wiring have two layers. That is, the first upper layer wiring 25A including the first upper base metal layer 24A is provided on the upper surface of the first upper insulating film 22A. One end of the first upper wiring 25A including the first upper base metal layer 24A is connected to the upper surface of the columnar electrode 12 of the semiconductor structure 2 through the opening 23A of the first upper insulating film 22A. .

第１の上層配線２５Ａを含む第１の上層絶縁膜２２Ａの上面には、第１の上層絶縁膜２２Ａと同一の材料からなる第２の上層絶縁膜２２Ｂが設けられている。第２の上層絶縁膜２２Ｂの上面には第２の上層下地金属層２４Ｂを含む第２の上層配線２５Ｂが設けられている。第２の上層下地金属層２４Ｂを含む第２の上層配線２５Ｂの一端部は、第２の上層絶縁膜２２Ｂの開口部２３Ｂを介して第１の上層配線２５Ａの接続パッド部に接続されている。   On the upper surface of the first upper insulating film 22A including the first upper wiring 25A, a second upper insulating film 22B made of the same material as the first upper insulating film 22A is provided. A second upper layer wiring 25B including a second upper layer base metal layer 24B is provided on the upper surface of the second upper layer insulating film 22B. One end of the second upper layer wiring 25B including the second upper layer underlying metal layer 24B is connected to the connection pad portion of the first upper layer wiring 25A through the opening 23B of the second upper layer insulating film 22B. .

第２の上層配線２５Ｂを含む第２の上層絶縁膜２２Ｂの上面に最上層絶縁膜２６が設けられている。第２の上層配線２５Ｂの接続パッド部に対応する部分における最上層絶縁膜２６には開口部２７が設けられている。最上層絶縁膜２６の開口部２７内およびその上方には半田ボール２８が第２の上層配線２５Ｂの接続パッド部に接続されて設けられている。なお、上層絶縁膜および上層配線は３層以上としてもよい。   An uppermost insulating film 26 is provided on the upper surface of the second upper insulating film 22B including the second upper wiring 25B. An opening 27 is provided in the uppermost insulating film 26 in a portion corresponding to the connection pad portion of the second upper layer wiring 25B. Solder balls 28 are provided in and above the opening 27 of the uppermost insulating film 26 so as to be connected to the connection pad portion of the second upper layer wiring 25B. Note that the upper insulating film and the upper wiring may have three or more layers.

ところで、図１０に示す場合では、互いに隣接する半導体構成体２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、２個で１組の半導体構成体２は同種、異種のいずれであってもよい。   By the way, in the case shown in FIG. 10, it cut | disconnected between the semiconductor structure 2 adjacent to each other, but it is not restricted to this, Two or more semiconductor structures 2 are cut | disconnected as 1 set, and a multichip module type semiconductor is cut | disconnected. An apparatus may be obtained. In this case, the two sets of semiconductor structures 2 may be of the same type or different types.

また、上記では、半導体構成体２として、封止膜１３を有し、且つ、外部接続用電極としての柱状電極１２を有する場合について説明したが、これに限らず、例えば、封止膜１３および柱状電極１２を有せず、外部接続用電極としての接続パッド部を有する配線１１を有するものとしてもよい。この場合、配線１１の接続パッド部以外を覆うオーバーコート膜を有するものとしてもよい。   In the above description, the case where the semiconductor structure 2 has the sealing film 13 and the columnar electrode 12 as the external connection electrode has been described. It is good also as what has the wiring 11 which does not have the columnar electrode 12 but has the connection pad part as an external connection electrode. In this case, an overcoat film that covers the wiring 11 other than the connection pad portion may be provided.

この発明の製造方法により製造された半導体装置の第１の例の断面図。Sectional drawing of the 1st example of the semiconductor device manufactured by the manufacturing method of this invention. 図１に示す半導体装置の製造方法の一例において、当初の工程の断面図。Sectional drawing of the initial process in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. この発明の製造方法により製造された半導体装置の第２の例の断面図。Sectional drawing of the 2nd example of the semiconductor device manufactured by the manufacturing method of this invention. この発明の製造方法により製造された半導体装置の第３の例の断面図。Sectional drawing of the 3rd example of the semiconductor device manufactured by the manufacturing method of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
３ａ 導電性接着層
４ シリコン基板
５ 接続パッド
６ 絶縁膜
８ 保護膜
１１ 配線
１２ 柱状電極
１３ 封止膜
２１ 絶縁層
２２ 上層絶縁膜
２５ 上層配線
２６ 最上層絶縁膜
２８ 半田ボール
２９ 金属層
３１ 半導体構成体配置領域
３２ ジェットヘッド
３３ 液状接着剤 DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesive layer 3a Conductive adhesive layer 4 Silicon substrate 5 Connection pad 6 Insulating film 8 Protective film 11 Wiring 12 Columnar electrode 13 Sealing film 21 Insulating layer 22 Upper layer insulating film 25 Upper layer wiring 26 Top layer insulating Film 28 Solder ball 29 Metal layer 31 Semiconductor component arrangement region 32 Jet head 33 Liquid adhesive

Claims (11)

ベース板上の複数の半導体構成体配置領域の各々の複数の箇所に液状接着剤を分散させて塗布する工程と、
前記ベース板上の各半導体構成体配置領域に、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を前記塗布された液状接着剤からなる接着層により固定する工程と、
前記半導体構成体の上部側に少なくとも１層の上層配線を前記半導体構成体の外部接続用電極に接続させて形成する工程と、
前記半導体構成体間における前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 A step of dispersing and applying a liquid adhesive to each of a plurality of locations of a plurality of semiconductor structure arrangement regions on the base plate;
A plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate are bonded to each semiconductor structure arrangement region on the base plate by the applied liquid adhesive. Fixing with layers,
Forming at least one upper layer wiring on the upper side of the semiconductor structure by connecting to an external connection electrode of the semiconductor structure;
Cutting the base plate between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の発明において、前記上層配線を形成する前に、前記半導体構成体の周囲における前記ベース板上および前記半導体構成体上に絶縁層を形成する工程を有する半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an insulating layer on the base plate and the semiconductor structure around the semiconductor structure before forming the upper layer wiring. 請求項１に記載の発明において、前記液状接着剤を塗布する工程はジェットタイプのディスペンサを用いて行うことを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of applying the liquid adhesive is performed using a jet type dispenser. 請求項１に記載の発明において、前記接着層はその平面形状が前記ベース板上の半導体構成体配置領域とほぼ同一となるように形成することを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive layer is formed so that a planar shape thereof is substantially the same as a semiconductor structure arrangement region on the base plate. 請求項１に記載の発明において、前記液状接着剤を塗布する工程は、前記ベース板上の全ての半導体構成体配置領域に液状接着剤を塗布した後に、該液状接着剤を半硬化させる工程であることを特徴とする半導体装置の製造方法。   In the invention according to claim 1, the step of applying the liquid adhesive is a step of semi-curing the liquid adhesive after applying the liquid adhesive to all the semiconductor constituent arrangement regions on the base plate. A method for manufacturing a semiconductor device, comprising: 請求項５に記載の発明において、前記ベース板上の各半導体構成体配置領域に前記半導体構成体を固定する工程は、前記接着剤を本硬化させる工程を有することを特徴とする半導体装置の製造方法。   6. The semiconductor device manufacturing method according to claim 5, wherein the step of fixing the semiconductor structure to each semiconductor structure arrangement region on the base plate includes a step of fully curing the adhesive. Method. 請求項６に記載の発明において、前記本硬化された接着剤からなる前記接着層の厚さは５μm以上２０μm以下であることを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein a thickness of the adhesive layer made of the main-cured adhesive is 5 μm or more and 20 μm or less. 請求項１に記載の発明において、前記液状接着剤を塗布する工程および前記半導体構成体を固定する工程は、前記ベース板上の１つの半導体構成体配置領域に液状接着剤を塗布し、当該半導体構成体配置領域に１つの前記半導体構成体を当該半導体構成体配置領域に塗布された液状接着剤からなる接着層を介して接着させて配置し、これを繰り返す工程であることを特徴とする半導体装置の製造方法。   2. The method according to claim 1, wherein the step of applying the liquid adhesive and the step of fixing the semiconductor structure are performed by applying a liquid adhesive to one semiconductor structure arrangement region on the base plate. A semiconductor characterized in that one semiconductor structure is disposed in a structure arrangement region by adhering it through an adhesive layer made of a liquid adhesive applied to the semiconductor structure arrangement region, and this process is repeated. Device manufacturing method. 請求項１に記載の発明において、前記液状接着剤を塗布する工程は、前記ベース板上の各半導体構成体配置領域に形成された金属層上の複数の箇所に液状導電性接着剤を分散させて塗布する工程であることを特徴とする半導体装置の製造方法。   In the invention according to claim 1, the step of applying the liquid adhesive comprises dispersing the liquid conductive adhesive at a plurality of locations on the metal layer formed in each semiconductor component arrangement region on the base plate. A method for manufacturing a semiconductor device, characterized in that the method is a coating step. 請求項９に記載の発明において、前記半導体構成体はＳＯＩ集積回路部を有するものであることを特徴とする半導体装置の製造方法。   10. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor structure has an SOI integrated circuit portion. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor structure has a columnar electrode as the external connection electrode.
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JP2012530362A (en) * 2009-06-19 2012-11-29 アイメック Reduction of cracks at the metal / organic dielectric interface
JP2011014764A (en) * 2009-07-03 2011-01-20 Casio Computer Co Ltd Semiconductor device, and method of manufacturing the same
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