JP2011014765A - Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof - Google Patents

Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof Download PDF

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JP2011014765A
JP2011014765A JP2009158629A JP2009158629A JP2011014765A JP 2011014765 A JP2011014765 A JP 2011014765A JP 2009158629 A JP2009158629 A JP 2009158629A JP 2009158629 A JP2009158629 A JP 2009158629A JP 2011014765 A JP2011014765 A JP 2011014765A
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common
wiring
connection pads
provided
semiconductor structure
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JP2009158629A
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Japanese (ja)
Inventor
Takeshi Wakabayashi
Shinji Wakizaka
伸治 脇坂
猛 若林
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Casio Computer Co Ltd
カシオ計算機株式会社
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Priority to JP2009158629A priority Critical patent/JP2011014765A/en
Priority claimed from US12/828,492 external-priority patent/US8525335B2/en
Publication of JP2011014765A publication Critical patent/JP2011014765A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with a semiconductor construct called a CSP on a base plate, wherein interconnects for power supply signal and ground signal of the semiconductor construct are not burnt to be cut even when excessive current flows to the interconnects.SOLUTION: The interconnect for power supply signal indicated by number 10a is arranged all over a region in a plane square shape, including four connection pads 5a for power supply signal, on a left upper side of a silicon substrate 4, and connected to all the four connection pads 5a for power supply signal. The interconnect for ground signal indicated by number 10b is the same. Consequently, even if overcurrents flow to the interconnects 10a and 10b, the interconnects 10a and 10b are not burnt to be cut.

Description

  The present invention relates to a semiconductor structure, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

  Some conventional semiconductor devices have a semiconductor structure called a CSP (chip size package) fixed on a base plate larger in size than the semiconductor structure (see, for example, Patent Document 1). In this case, a semiconductor structure called CSP has a structure in which wiring is provided on a semiconductor substrate, a columnar electrode is provided on a connection pad portion of the wiring, and a sealing film is provided around the columnar electrode. .

  The lower surface of the semiconductor substrate of the semiconductor structure is fixed on the base plate. An insulating layer is provided on the base plate around the semiconductor structure. An upper insulating film is provided on the semiconductor structure and the insulating layer. An upper wiring is provided on the upper insulating film so as to be connected to the columnar electrode of the semiconductor structure. The portions other than the connection pad portion of the upper layer wiring are covered with an overcoat film, and solder balls are provided on the connection pad portion of the upper layer wiring.

Japanese Patent Laid-Open No. 2006-12885

  By the way, in the semiconductor structure in the conventional semiconductor device, since the columnar electrode is provided on the connection pad portion of the wiring, the relationship between the wiring and the columnar electrode is 1: 1. For this reason, when the line width of the wiring is reduced to about 20 μm or less with the increase in the number of wirings and columnar electrodes, when an excessive current such as a power supply signal flows through the wiring, the wiring is burned out and disconnected. There is a problem that there is.

Accordingly, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same that can prevent the wiring from burning out even if an excessive current such as a power supply signal flows through the wiring.
It is another object of the present invention to provide a semiconductor device and a method for manufacturing the same that can prevent the wiring from burning out even if an excessive current such as a power supply signal flows through the wiring of the semiconductor structure.

The semiconductor structure according to the invention of claim 1 is a semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, an insulating film provided on the semiconductor substrate, and the insulating film on the insulating film. A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads, and connected to the remaining connection pads on the insulating film And a common columnar electrode provided on the common wiring, and a columnar electrode provided on a connection pad portion of the wiring.
According to a second aspect of the present invention, in the semiconductor structure according to the first aspect, the same number of the common columnar electrodes is provided on the common wiring as the connection pads for common signals. It is what.
According to a third aspect of the present invention, in the semiconductor structure according to the first aspect, the common columnar electrode is provided on the common wiring in a number larger than the number of common connection pads for signals. It is characterized by being.
According to a fourth aspect of the present invention, there is provided a semiconductor structure according to the first aspect, wherein a sealing film is provided around the common columnar electrode and the columnar electrode. .
According to a fifth aspect of the present invention, there is provided the semiconductor structure according to the first aspect of the present invention, wherein the number of the common wiring is two, one of which is for a power supply signal and the other is a ground signal. It is for use.
According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, comprising: preparing a semiconductor substrate having an upper surface formed with an insulating film on a semiconductor substrate having a plurality of connection pads formed thereon; A solid common wiring is formed by connecting to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads, and the wiring is formed on the remaining connection pads on the insulating film. And forming a common columnar electrode on the common wiring, and forming a columnar electrode on the connection pad portion of the wiring.
According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor structure according to the sixth aspect, the same number of the common columnar electrodes as the common signal connection pads are formed on the common wiring. It is a feature.
A method for manufacturing a semiconductor structure according to an eighth aspect of the present invention is the method according to the sixth aspect, wherein the number of the common columnar electrodes on the common wiring is larger than the number of the connection pads for common signals. It is characterized by forming.
A manufacturing method of a semiconductor structure according to the invention described in claim 9 is characterized in that, in the invention described in claim 6, the method includes a step of forming a sealing film around the common columnar electrode and the columnar electrode. To do.
According to a tenth aspect of the present invention, there is provided a semiconductor structure manufacturing method according to the sixth aspect of the present invention, wherein the number of the common wires is two, one of which is for a power supply signal, and the other of the common wires. Is for a ground signal.
A semiconductor device according to an eleventh aspect is provided on a base plate, the base plate, a semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, and the semiconductor substrate. A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads on the insulating film; Semiconductor structure having wiring provided on the insulating film connected to the remaining connection pads, a common columnar electrode provided on the common wiring, and a columnar electrode provided on the connection pad portion of the wiring Body, an insulating layer provided on the base plate around the semiconductor structure, an upper insulating film provided on the semiconductor structure and the insulating layer, and the semiconductor structure on the upper insulating film It is characterized by comprising a common upper layer wiring connected to a common columnar electrode and an upper layer wiring connected to the columnar electrode of the semiconductor structure on the upper insulating film. .
A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the number of the common columnar electrodes is the same as the number of the connection pads for common signals on the common wiring. It is characterized by that.
A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the common columnar electrode is larger than the number of the connection pads for signals common on the common wiring. A large number is provided.
According to a fourteenth aspect of the present invention, in the semiconductor device according to the twelfth or thirteenth aspect of the present invention, the common upper layer wiring is arranged in a solid form in a region including all of the common columnar electrodes. To do.
According to a fifteenth aspect of the present invention, in the semiconductor device according to the eleventh aspect, the line width of the common upper layer wiring and the upper layer wiring is larger than the line width of the wiring of the semiconductor structure. It is characterized by.
A semiconductor device according to a sixteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the semiconductor structure includes the common columnar electrode and a sealing film provided around the columnar electrode. It is what.
A semiconductor device according to a seventeenth aspect of the present invention is the semiconductor device according to the eleventh aspect of the present invention, wherein the common wiring is two in the semiconductor structure, one of which is for a power supply signal, One is for a ground signal.
A semiconductor device according to an eighteenth aspect of the present invention is the semiconductor device according to the eleventh aspect of the present invention, further comprising an overcoat film covering a portion of the common upper layer wiring and the upper layer wiring except for connection pads. is there.
According to a nineteenth aspect of the present invention, in the semiconductor device according to the seventeenth aspect, solder balls are provided on the connection pads of the common upper layer wiring and the upper layer wiring. .
A method of manufacturing a semiconductor device according to claim 20 is provided on a base plate, each of which is provided on a semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, and the semiconductor substrate. An insulating film; a common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads on the insulating film; and the insulation A plurality of semiconductors having a wiring provided on the film connected to the remaining connection pads, a common columnar electrode provided on the common wiring, and a columnar electrode provided on a connection pad portion of the wiring A step of disposing the components apart from each other, a step of forming an insulating layer on the base plate around the semiconductor structure, and forming an upper insulating film on the semiconductor structure and the insulating layer When A common upper layer wiring is formed on the upper insulating film to be connected to the upper surface of the common columnar electrode of the semiconductor structure, and an upper layer wiring is connected to the upper surface of the columnar electrode of the semiconductor structure on the upper insulating film. And forming a plurality of semiconductor devices by cutting the upper insulating film, the insulating layer and the base plate between the semiconductor structures.
According to a twenty-first aspect of the present invention, in the semiconductor device manufacturing method according to the twentieth aspect, in the semiconductor structure, the common columnar electrode is connected to the common signal connection pad on the common wiring. The same number is provided.
According to a twenty-second aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, in the semiconductor structure, the common columnar electrode is formed on the common wiring on the common signal connection pad. More than the number is provided.
According to a twenty-third aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-first or twenty-second aspect of the invention, the common upper layer wiring is formed in a solid shape in a region including all of the common columnar electrodes. It is what.
According to a twenty-fourth aspect of the present invention, in the semiconductor device manufacturing method according to the twentieth aspect, the common upper layer wiring and the upper layer wiring have a line width larger than a line width of the wiring of the semiconductor structure. It forms so that it may become.
According to a twenty-fifth aspect of the invention, in the semiconductor device manufacturing method according to the twentieth aspect, the semiconductor structure has the common columnar electrode and a sealing film provided around the columnar electrode. It is characterized by this.
According to a twenty-sixth aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, in the semiconductor structure, there are two common wirings, one of which is for a power supply signal. The other is for a ground signal.
According to a twenty-seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the twenty-second aspect of the present invention, comprising the step of forming an overcoat film that covers a portion of the common upper layer wiring and the upper layer wiring except for connection pads. It is characterized by this.
A method of manufacturing a semiconductor device according to a twenty-eighth aspect of the invention is characterized in that, in the twenty-seventh aspect of the invention, the method includes the step of forming solder balls on the common upper layer wiring and the connection pads of the upper layer wiring. To do.

  According to the present invention, in the semiconductor structure, the solid common wiring is connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads on the insulating film. Therefore, even if an excessive current such as a power supply signal flows through the common wiring of the semiconductor structure, the common wiring can be prevented from being burned out.

1 is a transparent plan view of a semiconductor device as a first embodiment of the present invention. FIG. 2 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. 1. Sectional drawing of what was initially prepared in an example of the manufacturing method of the semiconductor device shown in FIG.1 and FIG.2. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. The permeation | transmission top view of the semiconductor device as 2nd Embodiment of this invention. FIG. 20 is a cross-sectional view of a suitable portion of the semiconductor device shown in FIG. 19. The permeation | transmission top view of the semiconductor device as 3rd Embodiment of this invention. Sectional drawing of the semiconductor device as 4th Embodiment of this invention.

(First embodiment)
FIG. 1 is a transparent plan view of a semiconductor device as a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. This semiconductor device includes a planar rectangular base plate 1 made of glass cloth base epoxy resin or the like. The lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded to the central portion of the upper surface of the base plate 1 via an adhesive layer 3 made of a die bond material.

  The semiconductor structure 2 is generally called a CSP and includes a silicon substrate (semiconductor substrate) 4. The lower surface of the silicon substrate 4 is bonded to the central portion of the upper surface of the base plate 1 through the adhesive layer 3. On the upper surface of the silicon substrate 4 are formed elements (not shown) such as transistors, diodes, resistors, capacitors, etc. constituting an integrated circuit having a predetermined function. A plurality of connection pads 5a, 5b, and 5c made of an aluminum-based metal or the like connected to each element are provided.

  Here, as an example, in FIG. 1, four connection pads indicated by reference numeral 5a arranged on the upper left side on the silicon substrate 4 are for a common power supply signal. Four connection pads denoted by reference numeral 5b arranged on the lower left side on the silicon substrate 4 are for a common ground signal. The four connection pads indicated by reference numeral 5c arranged on the upper right side and the lower right side on the silicon substrate 4 are for other normal signals. Here, in FIG. 2, the connection pad 5b for ground signal and the portion related thereto are substantially the same as the connection pad 5a for power signal and the portion related thereto, and therefore are shown with parentheses.

  A passivation film (insulating film) 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the peripheral portion of the silicon substrate 4 and the central portions of the connection pads 5a, 5b, and 5c, and the connection pads 5a, 5b, and 5c. The central portion is exposed through openings 7 a, 7 b, 7 c provided in the passivation film 6. A protective film (insulating film) 8 made of polyimide resin or the like is provided on the upper surface of the passivation film 6. Openings 9a, 9b, and 9c are provided in the protective film 8 at portions corresponding to the openings 7a, 7b, and 7c of the passivation film 6.

  Wirings 10 a, 10 b and 10 c are provided on the upper surface of the protective film 8. The wirings 10 a, 10 b, and 10 c include base metal layers 11 a, 11 b, and 11 c made of copper or the like provided on the upper surface of the protective film 8, and upper metal layers 12 a and 12 b made of copper provided on the upper surface of the base metal layer 11. , 12c.

  In this case, as shown in FIG. 1, the wiring (common wiring) denoted by reference numeral 10a is solid in a planar rectangular region including the four power supply signal connection pads 5a on the upper left side on the silicon substrate 4. And is connected to all four power supply signal connection pads 5a through the openings 7a and 9a of the passivation film 6 and the protective film 8.

  The wiring (common wiring) indicated by reference numeral 10b is a solid film disposed in a planar rectangular region including four ground signal connection pads 5b on the lower left side of the silicon substrate 4, and is formed from a passivation film. 6 and the openings 7b and 9b of the protective film 8 are connected to all of the four ground signal connection pads 5b.

  The wiring indicated by reference numeral 10c is arranged in the right region on the silicon substrate 4 and is connected to the normal signal connection pad 5c through the openings 7c and 9c of the passivation film 6 and the protective film 8- 1. It has a planar circular connection pad portion 10c-2 and a lead wire portion 10c-3 therebetween.

  Columnar electrodes (common columnar electrodes) 13a made of copper are provided at predetermined four locations on the upper surface of the planar rectangular wiring indicated by reference numeral 10a. Columnar electrodes (common columnar electrodes) 13b made of copper are provided at predetermined four locations on the upper surface of the planar rectangular wiring denoted by reference numeral 10b. A columnar electrode 13c made of copper is provided on the upper surface of the connection pad portion 10c-2 of the wiring denoted by reference numeral 10c. Here, as shown in FIG. 1, a total of 16 columnar electrodes 13a, 13b, 13c are arranged in a matrix.

  A sealing film 14 made of an epoxy resin or the like is provided around the columnar electrodes 13a, 13b, and 13c on the upper surface of the protective film 8 including the wirings 10a, 10b, and 10c. The columnar electrodes 13 a, 13 b, and 13 c are provided so that their upper surfaces are one to several μm lower than the upper surface of the sealing film 14. Above, description about the structure of the semiconductor structure 2 is complete | finished.

  A rectangular frame-shaped insulating layer 21 is provided on the upper surface of the base plate 1 around the semiconductor structure 2. The insulating layer 21 is made of, for example, a material in which a reinforcing material made of an inorganic material such as silica fuller is dispersed in a thermosetting resin such as an epoxy resin, or a thermosetting resin such as an epoxy resin.

  An upper insulating film 22 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. The upper insulating film 22 is made of, for example, a material such as a glass cloth impregnated with a thermosetting resin such as an epoxy resin, or a thermosetting resin such as an epoxy resin. Openings 23a, 23b, and 23c are provided in the upper insulating film 22 in portions corresponding to the center of the upper surface of the columnar electrodes 13a, 13b, and 13c of the semiconductor structure 2.

  Upper layer wirings 24 a, 24 b and 24 c are provided on the upper surface of the upper layer insulating film 22. The upper wirings 24a, 24b, and 24c are made of the base metal layers 25a, 25b, and 25c made of copper or the like provided on the upper surface of the upper insulating film 22, and the copper provided on the upper surfaces of the base metal layers 25a, 25b, and 25c. It has a two-layer structure with upper metal layers 26a, 26b, and 26c.

  In this case, the upper layer wirings 24a, 24b, and 24c are composed of a connection part, a connection pad part, and a lead line part between them, like the wiring indicated by reference numeral 10c of the semiconductor structure 2. The connection portions of the upper layer wirings (common upper layer wirings) 24 a and 24 b are connected to the upper surfaces of the columnar electrodes 13 a and 13 b of the semiconductor structure 2 through the openings 23 a and 23 b of the upper layer insulating film 22. The connection portion of the upper layer wiring 24 c is connected to the upper surface of the columnar electrode 13 c of the semiconductor structure 2 through the opening 23 c of the upper layer insulating film 22.

  An overcoat film 27 made of a solder resist or the like is provided on the upper surface of the upper insulating film 22 including the upper wirings 24a, 24b, and 24c. Openings 28a, 28b, and 28c are provided in the overcoat film 27 in portions corresponding to the connection pad portions of the upper layer wirings 24a, 24b, and 24c. Solder balls 29a, 29b, and 29c are provided in and above the openings 28a, 28b, and 28c so as to be connected to the connection pad portions of the upper layer wirings 24a, 24b, and 24c. Here, as shown in FIG. 1, the connection pad portions of the upper layer wirings 24 a, 24 b, 24 c and the solder balls 29 a, 29 b, 29 c are arranged only around the semiconductor structure 2.

  As described above, in this semiconductor device, the power signal wiring 10a and the ground signal wiring 10b of the semiconductor structure 2 are formed in a planar rectangular shape and connected to all four connection pads 5a and 5b, respectively. Therefore, even if an excessive current flows through the power supply signal wiring 10a and the ground signal wiring 10b, the wirings 10a and 10b can be prevented from being burned out.

  Here, some dimensions of the semiconductor device will be described. The size of the base plate 1 is 3 × 3 mm. The size of the semiconductor structure 2 is 2 × 2 mm. The line width of the lead line portion 10c-3 of the wiring 10c of the semiconductor structure 2 is 20 μm. The diameters of the columnar electrodes 13a, 13b, 13c of the semiconductor structure 2 are 0.2 mm, and the pitch is 0.4 mm. The diameter of the opening 23 of the upper insulating film 22 is 100 μm. The connection pad portions of the upper layer wirings 24a, 24b, and 24c have a diameter of 0.3 mm and a pitch of 0.65 mm.

  By the way, since the size of the base plate 1 is larger than the size of the semiconductor structure 2, even if the line width 10c-3 of the normal signal wiring 10c of the semiconductor structure 2 is as relatively small as 20 μm, the upper layer The line width of the lead line portions of the wirings 24a, 24b, and 24c can be made relatively large, for example, 100 μm. As a result, even if an excessive current flows through the upper layer wiring 24a for power supply signals and the upper layer wiring 24b for ground signals, these upper layer wirings 24a and 24b can be made hard to burn out.

  Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, the connection pad 5b for the ground signal and the portion related thereto are substantially the same as the connection pad 5a for the power supply signal and the portion related thereto, and thus the description thereof is omitted.

  First, as shown in FIG. 3, connection pads 5a and 5c, a passivation film 6 and a protective film 8 are formed on the upper surface of a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 31), and the central portions of the connection pads 5a and 5c. Are exposed through the openings 7 a and 7 c of the passivation film 6 and the openings 9 a and 9 c of the protective film 8.

  In this case, the semiconductor wafer 31 is thicker than the silicon substrate 4 shown in FIG. In FIG. 3, the area indicated by reference numeral 32 is a dicing street. Then, the passivation film 6 and the protective film 8 in the portions corresponding to the dicing street 32 and both sides thereof are removed.

  Next, as shown in FIG. 4, the entire upper surface of the protective film 8 including the upper surfaces of the connection pads 5 a and 5 c exposed through the openings 7 a and 7 c of the passivation film 6 and the openings 9 a and 9 c of the protective film 8. A base metal layer 33 is formed. In this case, the base metal layer 33 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a plating resist film 34 made of a positive liquid resist is patterned on the upper surface of the base metal layer 33. In this case, openings 35a and 35c are formed in the plating resist film 34 in portions corresponding to the formation regions of the upper metal layers 12a and 12c. Next, when copper electroplating is performed using the base metal layer 33 as a plating current path, the upper metal layers 12 a and 12 c are formed on the upper surface of the base metal layer 33 in the openings 35 a and 35 c of the plating resist film 34. . Next, the plating resist film 34 is peeled off.

  Next, as shown in FIG. 5, a plating resist film 36 made of a negative dry film resist is patterned on the upper surface of the base metal layer 33. In this case, there are openings 37a in the plating resist film 36 at portions corresponding to predetermined four locations (columnar electrode 13a formation region) of the upper metal layer 12a and connection pad portions (columnar electrode 13c formation region) of the upper metal layer 12c. 37c is formed.

  Next, when copper is electroplated using the base metal layer 33 as a plating current path, the upper metal in the opening 37a of the plating resist film 36 and the upper metal in the opening 37c of the plating resist film 36 are formed. Columnar electrodes 13a and 13c are formed on the upper surface of the connection pad portion of the layer 12c. Next, the plating resist film 36 is peeled off.

  Next, when the base metal layer 33 is removed by etching using the upper metal layers 12a and 12c as a mask, the underlying metal layer 33 is removed under the upper metal layers 12a and 12c as shown in FIG. Only the base metal layers 11a and 11c remain. In this state, the upper metal layers 12a and 12c and the underlying metal layers 11a and 11c remaining under the upper metal layers 12a and 12c form wirings 10a and 10c having a two-layer structure.

  Next, as shown in FIG. 7, an epoxy resin or the like is applied to the upper surface of the dicing street 32 and the upper surface of the semiconductor wafer 31 on both sides and the upper surface of the protective film 8 including the wirings 10a and 10c and the columnar electrodes 13a and 13c by spin coating or the like. The sealing film 14 made of is formed so that its thickness is slightly thicker than the height of the columnar electrodes 13a and 13c. Therefore, in this state, the upper surfaces of the columnar electrodes 13 a and 13 c are covered with the sealing film 14.

  Next, the upper surface side of the sealing film 14 is appropriately ground to expose the upper surfaces of the columnar electrodes 13a and 13c and to include the exposed upper surfaces of the columnar electrodes 13a and 13c as shown in FIG. The upper surface of the stop film 14 is flattened. Next, as shown in FIG. 9, the lower surface side of the semiconductor wafer 31 is appropriately ground to reduce the thickness of the semiconductor wafer 31.

  Next, as shown in FIG. 10, the adhesive layer 3 is bonded to the lower surface of the semiconductor wafer 31. The adhesive layer 3 is made of a die bond material such as an epoxy resin, and is fixed to the lower surface of the semiconductor wafer 31 in a semi-cured state by heating and pressing. Next, as shown in FIG. 11, when the sealing film 14, the semiconductor wafer 31, and the adhesive layer 3 are cut along the dicing street 32, a plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface are obtained.

  Next, an example of manufacturing the semiconductor device shown in FIG. 2 using the semiconductor structure 2 shown in FIG. 11 will be described. Also in this case, the portion related to the connection pad 5b for ground signal is substantially the same as the portion related to the connection pad 5a for power signal, and the description thereof is omitted.

  First, as shown in FIG. 12, a base plate 1 made of glass cloth base epoxy resin or the like having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 2 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape. In FIG. 12, an area denoted by reference numeral 41 is an area corresponding to a cutting line for singulation.

  Next, the adhesive layers 3 fixed to the lower surface of the silicon substrate 4 of the plurality of semiconductor structures 2 are bonded to the plurality of semiconductor structure arrangement regions on the upper surface of the base plate 1 while being separated from each other. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

  Next, as shown in FIG. 13, a lattice-shaped insulating layer forming sheet 21 a is arranged on the upper surface of the base plate 1 around the semiconductor structure 2 while being positioned with pins or the like. For example, the lattice-shaped insulating layer forming sheet 21a is formed by dispersing a reinforcing material in a thermosetting resin such as an epoxy-based resin and making the thermosetting resin semi-cured into a sheet shape. A rectangular opening is formed.

  Next, the upper insulating film forming sheet 22a is disposed on the upper surfaces of the semiconductor structure 2 and the insulating layer forming sheet 21a. The upper insulating film forming sheet 22a is formed, for example, by impregnating a glass cloth or the like with a thermosetting resin such as an epoxy resin and making the thermosetting resin semi-cured into a sheet shape.

  Next, the insulating layer forming sheet 21a and the upper insulating film forming sheet 22a are heated and pressed from above and below using the pair of heating and pressing plates 42 and 43. Then, by subsequent cooling, a rectangular frame-shaped insulating layer 21 is formed on the upper surface of the base plate 1 around the semiconductor structure 2, and an upper insulating film 22 is formed on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. Is done. In this case, since the upper surface of the upper insulating film 22 is pressed by the lower surface of the upper heating and pressing plate 42, it becomes a flat surface.

  Next, as shown in FIG. 14, the openings 23 a and 23 c are formed by laser processing that irradiates the upper insulating film 22 in the portion corresponding to the center of the upper surface of the columnar electrodes 13 a and 13 c of the semiconductor structure 2 with a laser beam. Form.

  Next, as shown in FIG. 15, a base metal is formed on the entire upper surface of the upper insulating film 22 including the upper surfaces of the columnar electrodes 13 a and 13 c of the semiconductor structure 2 exposed through the openings 23 a and 23 c of the upper insulating film 22. Layer 44 is formed. Also in this case, the base metal layer 44 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and may be made of titanium or the like formed by sputtering. A copper layer may be formed on the thin film layer by sputtering.

  Next, a plating resist film 45 is patterned on the upper surface of the base metal layer 44. In this case, openings 46a and 46c are formed in the plating resist film 45 in portions corresponding to the formation regions of the upper metal layers 26a and 26c. Next, the upper metal layers 26 a and 26 c are formed on the upper surface of the base metal layer 44 in the openings 46 a and 46 c of the plating resist film 45 by performing electrolytic plating of copper using the base metal layer 44 as a plating current path. .

  Next, the plating resist film 45 is peeled off, and then the base metal layer 44 is removed by etching using the upper metal layers 26a and 26c as masks in regions other than the upper metal layers 26a and 26c, as shown in FIG. In addition, the base metal layers 25a and 25c remain only under the upper metal layers 26a and 26c. In this state, upper wirings 24a and 24c are formed by the upper metal layers 26a and 26c and the underlying metal layers 25a and 25c remaining under the upper metal layers 26a and 26c.

  Next, as shown in FIG. 17, an overcoat film 27 made of a solder resist or the like is formed on the upper surface of the upper insulating film 22 including the upper wirings 24a and 24c by screen printing, spin coating, or the like. In this case, openings 28a and 28c are formed in the overcoat film 27 in portions corresponding to the connection pad portions of the upper layer wirings 24a and 24c.

  Next, solder balls 29a and 29c are formed in and above the openings 28a and 28c of the overcoat film 27 so as to be connected to the connection pads of the upper wirings 24a and 24c. Next, as shown in FIG. 18, when the overcoat film 27, the upper insulating film 22, the insulating layer 21, and the base plate 1 are cut along the cutting line 41 between the adjacent semiconductor structures 2, FIG. A plurality of the semiconductor devices shown are obtained.

(Second Embodiment)
19 is a transparent plan view of a semiconductor device as a second embodiment of the present invention, and FIG. 20 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. This semiconductor device is different from the semiconductor device shown in FIGS. 1 and 2 in that it includes four power supply signal columnar electrodes 13a instead of the power supply signal upper layer wiring 24a and four power supply signal uses. A solid power supply signal upper layer wiring 24a is provided in the region including the solder ball 29a arrangement region, and four ground signal columnar electrodes 13b are included instead of the ground signal upper layer wiring 24b. This is because a solid ground signal upper layer wiring 24b is provided in a region including the ground signal solder ball 29b arrangement region.

  As described above, in this semiconductor device, the upper layer wiring 24a for the power supply signal and the upper layer wiring 24b for the ground signal have a solid shape, so that the upper layer wiring 24a, The resistance of 24b can be reduced, and as a result, the current capacity can be improved.

(Third embodiment)
FIG. 21 is a transparent plan view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 19 in that nine power supply signal columnar electrodes 13a are provided in a matrix on the upper surface of a solid power supply upper layer wiring 24a, and a solid This is because nine ground signal columnar electrodes 13b are provided in a matrix on the upper surface of the ground signal upper layer wiring 24b.

  Thus, in this semiconductor device, since there are nine columnar electrodes 13a for power supply signals and columnar electrodes 13b for ground signals, the columnar electrodes 13a are compared with the semiconductor devices shown in FIGS. , 13b can be reduced in resistance, and the current capacity can be improved. In this case, as an example, the pitch of the columnar electrodes 13a and 13b is 0.25 mm.

(Fourth embodiment)
FIG. 22 is a sectional view of a semiconductor device as the fourth embodiment of the present invention. This semiconductor device is greatly different from the semiconductor device shown in FIG. 2 in that the upper insulating film and the upper wiring have two layers. That is, the second upper layer insulating film 22B made of the same material as the first upper layer insulating film 22A is provided on the upper surface of the first upper layer insulating film 22A including the first upper layer wiring 24A. A second upper layer wiring 24B having a structure similar to that of the first upper layer wiring 24A is provided on the upper surface of the second upper layer insulating film 22B.

One end portion of the first upper layer wiring 24A is connected to the columnar electrode 13 through the opening 23A of the first upper layer insulating film A. One end of the second upper layer wiring 24B is connected to the connection pad portion of the first upper layer wiring 24A through the opening 23B of the second upper layer insulating film 22B. The solder ball 29 is connected to the connection pad portion of the second upper layer wiring 24B through the opening 28 of the overcoat film 27. Note that the upper insulating film and the upper wiring may have three or more layers.

DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5a, 5b, 5c Connection pad 6 Passivation film 8 Protective film 10a, 10b, 10c Wiring 13a, 13b, 13c Columnar electrode 14 Sealing film 21 Insulating layer 22 Upper insulating film 24a, 24b, 24c Upper layer wiring 27 Overcoat film 29a, 29b, 29c Solder ball

Claims (28)

  1. A semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, an insulating film provided on the semiconductor substrate, and a plurality of connection pads for common signals among the connection pads on the insulating film A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including the wiring, a wiring provided connected to the remaining connection pads on the insulating film, and provided on the common wiring And a columnar electrode provided on the connection pad portion of the wiring.
  2.   2. The semiconductor structure according to claim 1, wherein the same number of the common columnar electrodes are provided on the common wiring as the connection pads for common signals.
  3.   2. The semiconductor structure according to claim 1, wherein the number of the common columnar electrodes is greater than the number of the common connection pads for signals on the common wiring.
  4.   The semiconductor structure according to claim 1, wherein a sealing film is provided around the common columnar electrode and the columnar electrode.
  5.   2. The semiconductor structure according to claim 1, wherein there are two common wirings, one of which is for a power supply signal and the other is for a ground signal.
  6. Preparing an insulating film formed on a semiconductor substrate having a plurality of connection pads formed on the upper surface;
    On the insulating film, a solid common wiring is formed in a region including a plurality of common signal connection pads among the connection pads, and is connected to all of the connection pads, and the wiring is formed on the insulating film. Connecting and forming the remaining connection pads;
    Forming a common columnar electrode on the common wiring, and forming a columnar electrode on a connection pad portion of the wiring;
    A method for producing a semiconductor structure, comprising:
  7.   7. The method of manufacturing a semiconductor structure according to claim 6, wherein the same number of the common columnar electrodes as the common signal connection pads are formed on the common wiring.
  8.   7. The method of manufacturing a semiconductor structure according to claim 6, wherein the common columnar electrode is formed on the common wiring in a number larger than the number of common connection pads for signals.
  9.   7. The method of manufacturing a semiconductor structure according to claim 6, further comprising a step of forming a sealing film around the common columnar electrode and the columnar electrode.
  10.   7. The method of manufacturing a semiconductor structure according to claim 6, wherein there are two common wires, one of which is for a power supply signal and the other one is for a ground signal. .
  11. A base plate; a semiconductor substrate provided on the base plate; a plurality of connection pads provided on the semiconductor substrate; an insulating film provided on the semiconductor substrate; and the connection pads on the insulating film A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals, and connected to the remaining connection pads on the insulating film A semiconductor structure having a wiring provided, a common columnar electrode provided on the common wiring, and a columnar electrode provided on a connection pad portion of the wiring; and the base plate around the semiconductor structure An upper insulating layer provided on the insulating layer; an upper insulating layer provided on the insulating layer; and a common upper electrode provided on the upper insulating layer and connected to a common columnar electrode of the semiconductor constituent. A semiconductor device characterized by comprising a wiring, the upper wiring and provided to be connected to the columnar electrode of the semiconductor structure on the upper insulating film.
  12.   12. The semiconductor device according to claim 11, wherein in the semiconductor structure, the common columnar electrodes are provided in the same number as the connection pads for common signals on the common wiring.
  13.   12. The semiconductor device according to claim 11, wherein in the semiconductor structure, the common columnar electrode is provided in a number larger than the number of common connection pads for signals on the common wiring. .
  14.   14. The semiconductor device according to claim 12, wherein the common upper layer wiring is arranged in a solid shape in a region including all of the common columnar electrodes.
  15.   12. The semiconductor device according to claim 11, wherein a line width of the common upper layer wiring and the upper layer wiring is larger than a line width of the wiring of the semiconductor structure.
  16.   12. The semiconductor device according to claim 11, wherein the semiconductor structure includes the common columnar electrode and a sealing film provided around the columnar electrode.
  17.   The invention according to claim 11 is characterized in that, in the semiconductor structure, there are two common wires, one of which is for a power supply signal and the other one is for a ground signal. Semiconductor device.
  18.   12. The semiconductor device according to claim 11, further comprising an overcoat film covering a portion of the common upper layer wiring and the upper layer wiring excluding connection pads.
  19.   18. The semiconductor device according to claim 17, wherein solder balls are provided on connection pads of the common upper layer wiring and the upper layer wiring.
  20. On the base plate, each of the semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, an insulating film provided on the semiconductor substrate, and a common of the connection pads on the insulating film Common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for signals, and wiring provided to be connected to the remaining connection pads on the insulating film And a step of disposing a plurality of semiconductor structures having a common columnar electrode provided on the common wiring and a columnar electrode provided on a connection pad portion of the wiring apart from each other;
    Forming an insulating layer on the base plate around the semiconductor structure, and forming an upper insulating film on the semiconductor structure and the insulating layer;
    A common upper layer wiring is formed on the upper insulating film to be connected to the upper surface of the common columnar electrode of the semiconductor structure, and an upper layer wiring is connected to the upper surface of the columnar electrode of the semiconductor structure on the upper insulating film. Forming the process,
    Cutting the upper insulating film, the insulating layer, and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices;
    A method for manufacturing a semiconductor device, comprising:
  21.   21. The method of manufacturing a semiconductor device according to claim 20, wherein in the semiconductor structure, the common columnar electrodes are provided in the same number as the connection pads for common signals on the common wiring.
  22.   21. The semiconductor device according to claim 20, wherein in the semiconductor structure, the common columnar electrode is provided in a number larger than the number of common connection pads for signals on the common wiring. Manufacturing method.
  23.   23. The method of manufacturing a semiconductor device according to claim 21, wherein the common upper layer wiring is formed in a solid shape in a region including all of the common columnar electrodes.
  24.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the common upper layer wiring and the upper layer wiring are formed so that the line width thereof is larger than the line width of the wiring of the semiconductor structure.
  25.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the semiconductor structure includes the common columnar electrode and a sealing film provided around the columnar electrode.
  26.   The invention according to claim 20 is characterized in that, in the semiconductor structure, there are two common wires, one of which is for a power supply signal and the other one is for a ground signal. A method for manufacturing a semiconductor device.
  27.   21. The method of manufacturing a semiconductor device according to claim 20, further comprising a step of forming an overcoat film covering a portion of the common upper layer wiring and the upper layer wiring excluding connection pads.
  28.   26. The method of manufacturing a semiconductor device according to claim 25, further comprising a step of forming solder balls on the common upper layer wiring and the connection pads of the upper layer wiring.
JP2009158629A 2009-07-03 2009-07-03 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof Pending JP2011014765A (en)

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JP2009158629A JP2011014765A (en) 2009-07-03 2009-07-03 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
US12/828,492 US8525335B2 (en) 2009-07-03 2010-07-01 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
KR1020100063483A KR101169531B1 (en) 2009-07-03 2010-07-01 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
CN2010102227863A CN101944518B (en) 2009-07-03 2010-07-02 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
TW099121769A TW201118993A (en) 2009-07-03 2010-07-02 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
HK11107145.6A HK1153039A1 (en) 2009-07-03 2011-07-11 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
US13/960,485 US8754525B2 (en) 2009-07-03 2013-08-06 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
US14/271,227 US8946079B2 (en) 2009-07-03 2014-05-06 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
US14/571,049 US9406637B2 (en) 2009-07-03 2014-12-15 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof

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Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH10242332A (en) * 1997-02-25 1998-09-11 Casio Comput Co Ltd Semiconductor device
JP2001267350A (en) * 2000-03-21 2001-09-28 Fujitsu Ltd Semiconductor device and manufacturing method for the same
JP2007165579A (en) * 2005-12-14 2007-06-28 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007281116A (en) * 2006-04-05 2007-10-25 Casio Comput Co Ltd Method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242332A (en) * 1997-02-25 1998-09-11 Casio Comput Co Ltd Semiconductor device
JP2001267350A (en) * 2000-03-21 2001-09-28 Fujitsu Ltd Semiconductor device and manufacturing method for the same
JP2007165579A (en) * 2005-12-14 2007-06-28 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007281116A (en) * 2006-04-05 2007-10-25 Casio Comput Co Ltd Method of manufacturing semiconductor device

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