JP2011014764A - Semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor device, and method of manufacturing the same Download PDF

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JP2011014764A
JP2011014764A JP2009158622A JP2009158622A JP2011014764A JP 2011014764 A JP2011014764 A JP 2011014764A JP 2009158622 A JP2009158622 A JP 2009158622A JP 2009158622 A JP2009158622 A JP 2009158622A JP 2011014764 A JP2011014764 A JP 2011014764A
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common
insulating film
wiring
semiconductor device
columnar electrode
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Shinji Wakizaka
伸治 脇坂
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2009158622A priority Critical patent/JP2011014764A/en
Priority to US12/828,492 priority patent/US8525335B2/en
Priority to KR1020100063483A priority patent/KR101169531B1/en
Priority to CN2010102227863A priority patent/CN101944518B/en
Priority to TW099121769A priority patent/TW201118993A/en
Publication of JP2011014764A publication Critical patent/JP2011014764A/en
Priority to HK11107145.6A priority patent/HK1153039A1/en
Priority to US13/960,485 priority patent/US8754525B2/en
Priority to US14/271,227 priority patent/US8946079B2/en
Priority to US14/571,049 priority patent/US9406637B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with a semiconductor construct called a CSP on a base plate, wherein interconnects for power supply signal and ground signal of the semiconductor construct are not burnt to be cut even when excessive current flows to the interconnects.SOLUTION: The interconnect for power supply signal indicated by number 10a is arranged all over a region in a plane square shape, including four connection pads 5a for power supply signal, on a left upper side of a silicon substrate 4, and connected to all the four connection pads 5a for power supply signal. The interconnect for ground signal indicated by number 10b is the same. Consequently, even if overcurrents flow to the interconnects 10a and 10b, the interconnects 10a and 10b are not burnt to be cut. In this case, four columnar electrodes 13a and 13b are provided on the interconnects 10a and 10b. Upper-layer interconnects 24a and 24b provided all thereover with an upper-layer insulating film interposed are connected to the four columnar electrodes 13a and 13b through opening parts 23a and 23b in a plane square shape provided on the upper-layer insulating film.

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、ＣＳＰ(chip size package)と呼ばれる半導体構成体を該半導体構成体よりもサイズの大きいベース板上に固着したものがある（例えば、特許文献１参照）。この場合、ＣＳＰと呼ばれる半導体構成体は、半導体基板上に配線が設けられ、配線の接続パッド部上に柱状電極が設けられ、柱状電極の周囲に封止膜が設けられた構造となっている。   Some conventional semiconductor devices have a semiconductor structure called a CSP (chip size package) fixed on a base plate larger in size than the semiconductor structure (see, for example, Patent Document 1). In this case, a semiconductor structure called CSP has a structure in which wiring is provided on a semiconductor substrate, a columnar electrode is provided on a connection pad portion of the wiring, and a sealing film is provided around the columnar electrode. .

そして、半導体構成体の半導体基板の下面はベース板上に固着されている。半導体構成体の周囲におけるベース板上には絶縁層が設けられている。半導体構成体および絶縁層上には上層絶縁膜が設けられている。上層絶縁膜上には上層配線が半導体構成体の柱状電極に接続されて設けられている。上層配線の接続パッド部を除く部分はオーバーコート膜で覆われ、上層配線の接続パッド部上には半田ボールが設けられている。   The lower surface of the semiconductor substrate of the semiconductor structure is fixed on the base plate. An insulating layer is provided on the base plate around the semiconductor structure. An upper insulating film is provided on the semiconductor structure and the insulating layer. An upper wiring is provided on the upper insulating film so as to be connected to the columnar electrode of the semiconductor structure. The portions other than the connection pad portion of the upper layer wiring are covered with an overcoat film, and solder balls are provided on the connection pad portion of the upper layer wiring.

特開２００６−１２８８５号公報Japanese Patent Laid-Open No. 2006-12885

ところで、上記従来の半導体装置における半導体構成体では、配線の接続パッド部上に柱状電極を設けているので、配線と柱状電極との関係が１対１となっている。このため、配線および柱状電極の本数の増加に伴い、配線の線幅が２０μｍ程度以下と小さくなった場合、配線に電源信号等の過大電流が流れたとき、当該配線が焼き切れて断線することがあるという問題がある。   By the way, in the semiconductor structure in the conventional semiconductor device, since the columnar electrode is provided on the connection pad portion of the wiring, the relationship between the wiring and the columnar electrode is 1: 1. For this reason, when the line width of the wiring is reduced to about 20 μm or less with the increase in the number of wirings and columnar electrodes, when an excessive current such as a power supply signal flows through the wiring, the wiring is burned out and disconnected. There is a problem that there is.

そこで、この発明は、半導体構成体の配線に電源信号等の過大電流が流れても、当該配線が焼き切れないようにすることができる半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent the wiring from burning out even if an excessive current such as a power supply signal flows through the wiring of the semiconductor structure.

請求項１に記載の発明に係る半導体装置は、ベース板と、前記ベース板上に設けられ、半導体基板と、前記半導体基板上に設けられた複数の接続パッドと、前記半導体基板上に設けられた絶縁膜と、前記絶縁膜上において前記接続パッドのうち共通の信号用の複数の接続パッドを含む領域に当該接続パッドの全てに接続されるようにベタ状に設けられた共通配線と、前記絶縁膜上に残りの前記接続パッドに接続されて設けられた配線と、前記共通配線上に設けられた共通柱状電極と、前記配線の接続パッド部上に設けられた柱状電極とを有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記半導体構成体の共通柱状電極に対応する部分における前記上層絶縁膜に設けられた１つの第１の開口部と、前記半導体構成体の柱状電極に対応する部分における前記上層絶縁膜に設けられた第２の開口部と、前記上層絶縁膜上に該上層絶縁膜の第１の開口部を介して前記半導体構成体の共通柱状電極に接続されて設けられたベタ状の共通上層配線と、前記上層絶縁膜上に該上層絶縁膜の第２の開口部を介して前記半導体構成体の柱状電極に接続されて設けられた上層配線とを備えていることを特徴とするものである。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体は、前記共通柱状電極および前記柱状電極の周囲に設けられた封止膜を有することを特徴とするものである。
請求項３に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体において、前記共通配線は２つであり、そのうちの１つは電源信号用であり、他の１つはグランド信号用であることを特徴とするものである。
請求項４に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記柱状電極と同一形状のものからなり、前記共通配線上に複数設けられていることを特徴とするものである。
請求項５に記載の発明に係る半導体装置は、請求項４に記載の発明において、前記共通柱状電極の数は前記共通の信号用の接続パッドの数と同一であることを特徴とするものである。
請求項６に記載の発明に係る半導体装置は、請求項４または５に記載の発明において、前記共通上層配線は前記上層絶縁膜の第１の開口部を介して前記共通柱状電極の全てに接続されていることを特徴とするものである。
請求項７に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記共通配線上に該共通配線と同様にベタ状に設けられていることを特徴とするものである。
請求項８に記載の発明に係る半導体装置は、請求項５に記載の発明において、前記上層絶縁膜の第１の開口部の平面形状は、前記半導体構成体のベタ状の共通柱状電極の平面形状に応じて、前記上層絶縁膜の第２の開口部の平面形状よりも大きくなっていることを特徴とするものである。
請求項９に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記共通上層配線および前記上層配線の上面は面一となっていることを特徴とするものである。
請求項１０に記載の発明に係る半導体装置は請求項１に記載の発明において、前記共通上層配線の複数の箇所および前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を有することを特徴とするものである。
請求項１１に記載の発明に係る半導体装置は、請求項１０に記載の発明において、前記共通上層配線の複数の箇所上および前記上層配線の接続パッド上に半田ボールが設けられていることを特徴とするものである。
請求項１２に記載の発明に係る半導体装置は、請求項１１に記載の発明において、前記共通上層配線の複数の箇所上に設けられた前記半田ボールの数は前記共通の信号用の接続パッドの数と同一であることを特徴とするものである。
請求項１３に記載の発明に係る半導体装置の製造方法は、ベース板上に、各々が、半導体基板と、前記半導体基板上に設けられた複数の接続パッドと、前記半導体基板上に設けられた絶縁膜と、前記絶縁膜上において前記接続パッドのうち共通の信号用の複数の接続パッドを含む領域に当該接続パッドの全てに接続されるようにベタ状に設けられた共通配線と、前記絶縁膜上に残りの前記接続パッドに接続されて設けられた配線と、前記共通配線上に設けられた共通柱状電極と、前記配線の接続パッド部上に設けられた柱状電極とを有する複数の半導体構成体を相互に離間させて配置する工程と、前記半導体構成体の周囲における前記ベース板上に絶縁層を形成し、且つ、前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、前記半導体構成体の共通柱状電極に対応する部分における前記上層絶縁膜に１つの第１の開口部を形成し、且つ、前記半導体構成体の柱状電極に対応する部分における前記上層絶縁膜に第２の開口部を形成する工程と、前記上層絶縁膜上にベタ状の共通上層配線を前記上層絶縁膜の第１の開口部を介して前記半導体構成体の共通柱状電極に接続させて形成し、且つ、前記上層絶縁膜上に上層配線を前記上層絶縁膜の第２の開口部を介して前記半導体構成体の柱状電極に接続させて形成する工程と、前記半導体構成体間における前記上層絶縁膜、前記絶縁層および前記ベース板を切断して半導体装置を複数個得る工程と、を有することを特徴とするものである。
請求項１４に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体構成体は、前記共通柱状電極および前記柱状電極の周囲に設けられた封止膜を有することを特徴とするものである。
請求項１５に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体構成体において、前記共通配線は２つであり、そのうちの１つは電源信号用であり、他の１つはグランド信号用であることを特徴とするものである。
請求項１６に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記柱状電極と同一形状のものからなり、前記共通配線上に複数設けられていることを特徴とするものである。
請求項１７に記載の発明に係る半導体装置の製造方法は、請求項１６に記載の発明において、前記共通柱状電極の数は前記共通の信号用の接続パッドの数と同一であることを特徴とするものである。
請求項１８に記載の発明に係る半導体装置の製造方法は、請求項１６または１７に記載の発明において、前記共通上層配線は前記上層絶縁膜の第１の開口部を介して前記共通柱状電極の全てに接続されるように形成することを特徴とするものである。
請求項１９に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記共通配線上に該共通配線と同様にベタ状に設けられていることを特徴とするものである。
請求項２０に記載の発明に係る半導体装置の製造方法は、請求項１９に記載の発明において、前記上層絶縁膜の第１の開口部は、その平面形状が、前記半導体構成体のベタ状の共通柱状電極の平面形状に応じて、前記上層絶縁膜の第２の開口部の平面形状よりも大きくなるように形成することを特徴とするものである。
請求項２１に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記共通上層配線および前記上層配線を形成する工程は、前記上層絶縁膜の第１、第２の開口部内を含む前記上層絶縁膜上の全体に下地金属層を形成する工程と、前記下地金属層上に電解メッキにより共通上層配線用上部金属層および上層配線用上部金属層を形成する工程と、前記共通上層配線用上部金属層および前記上層配線用上部金属層の上面側を研削して前記共通上層配線用上部金属層および前記上層配線用上部金属層の上面を面一とする工程と、前記共通上層配線用上部金属層および前記上層配線用上部金属層下以外の領域における前記下地金属層を除去する工程とを含むことを特徴とするものである。
請求項２２に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記共通上層配線の複数の箇所および前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を形成する工程を有することを特徴とするものである。
請求項２３に記載の発明に係る半導体装置の製造方法は、請求項２２に記載の発明において、前記共通上層配線の複数の箇所上および前記上層配線の接続パッド上に半田ボールを形成する工程を有することを特徴とするものである。
請求項２４に記載の発明に係る半導体装置の製造方法は、請求項２３に記載の発明において、前記共通上層配線の複数の箇所上に形成される前記半田ボールの数は前記共通の信号用の接続パッドの数と同一であることを特徴とするものである。 A semiconductor device according to claim 1 is provided on a base plate, the base plate, a semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, and the semiconductor substrate. A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads on the insulating film; Semiconductor structure having wiring provided on the insulating film connected to the remaining connection pads, a common columnar electrode provided on the common wiring, and a columnar electrode provided on the connection pad portion of the wiring A semiconductor substrate, an insulating layer provided on the base plate around the semiconductor structure, an upper insulating film provided on the semiconductor structure and the insulating layer, and a common columnar electrode of the semiconductor structure A first opening provided in the upper insulating film in a portion of the semiconductor structure, a second opening provided in the upper insulating film in a portion corresponding to the columnar electrode of the semiconductor structure, and the upper insulating film A solid common upper layer wiring connected to the common columnar electrode of the semiconductor structure via the first opening of the upper insulating film on the film; and the upper insulating film on the upper insulating film. And an upper layer wiring provided to be connected to the columnar electrode of the semiconductor structure through a second opening.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the semiconductor structure includes a common columnar electrode and a sealing film provided around the columnar electrode. It is what.
According to a third aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein the common wiring is two in the semiconductor structure, one of which is for a power supply signal, One is for a ground signal.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the common columnar electrode has the same shape as the columnar electrode, and a plurality of the common columnar electrodes are formed on the common wiring. It is characterized by being provided.
According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the number of the common columnar electrodes is the same as the number of the common signal connection pads. is there.
A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fourth or fifth aspect, wherein the common upper layer wiring is connected to all of the common columnar electrodes through the first opening of the upper layer insulating film. It is characterized by being.
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the first aspect, wherein the common columnar electrode is provided in a solid shape on the common wiring in the same manner as the common wiring. It is characterized by being.
According to an eighth aspect of the present invention, in the semiconductor device according to the fifth aspect, the planar shape of the first opening of the upper insulating film is the plane of the solid common columnar electrode of the semiconductor structure. According to the shape, it is larger than the planar shape of the second opening of the upper insulating film.
According to a ninth aspect of the present invention, in the semiconductor device according to the first aspect, the common upper layer wiring and the upper surface of the upper layer wiring are flush with each other.
A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the first aspect, wherein the semiconductor device has an overcoat film that covers a plurality of portions of the common upper layer wiring and a portion other than the connection pads of the upper layer wiring. To do.
The semiconductor device according to an eleventh aspect is the semiconductor device according to the tenth aspect, wherein solder balls are provided on a plurality of locations of the common upper layer wiring and on connection pads of the upper layer wiring. It is what.
A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the number of the solder balls provided on a plurality of locations of the common upper layer wiring is the number of the common signal connection pads. It is the same as the number.
According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor substrate; a plurality of connection pads provided on the semiconductor substrate; and a plurality of connection pads provided on the semiconductor substrate. An insulating film; a common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals among the connection pads on the insulating film; and the insulation A plurality of semiconductors having a wiring provided on the film connected to the remaining connection pads, a common columnar electrode provided on the common wiring, and a columnar electrode provided on a connection pad portion of the wiring A step of disposing the components apart from each other, a step of forming an insulating layer on the base plate around the semiconductor structure, and forming an upper insulating film on the semiconductor structure and the insulating layer When A first opening is formed in the upper insulating film in a portion corresponding to the common columnar electrode of the semiconductor structure, and a second opening is formed in the upper insulating film in a portion corresponding to the columnar electrode of the semiconductor structure. And forming a solid common upper layer wiring on the upper insulating film via the first opening of the upper insulating film and connecting to the common columnar electrode of the semiconductor structure, A step of forming an upper wiring on the upper insulating film by connecting to a columnar electrode of the semiconductor structure via a second opening of the upper insulating film; and the upper insulating film between the semiconductor structures. And a step of cutting the insulating layer and the base plate to obtain a plurality of semiconductor devices.
According to a fourteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect, the semiconductor structure includes the common columnar electrode and a sealing film provided around the columnar electrode. It is characterized by this.
According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, in the semiconductor structure, there are two common wirings, one of which is for a power supply signal. The other is for a ground signal.
According to a sixteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, in the semiconductor structure, the common columnar electrode has the same shape as the columnar electrode, and the common wiring A plurality of devices are provided on the top.
According to a seventeenth aspect of the present invention, in the semiconductor device manufacturing method according to the sixteenth aspect, the number of the common columnar electrodes is the same as the number of the common signal connection pads. To do.
According to an eighteenth aspect of the present invention, in the semiconductor device manufacturing method according to the sixteenth or seventeenth aspect of the present invention, the common upper-layer wiring is connected to the common columnar electrode via the first opening of the upper-layer insulating film. It is characterized by being formed so as to be connected to all.
According to a nineteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, in the semiconductor structure, the common columnar electrode is formed in a solid shape on the common wiring in the same manner as the common wiring. It is characterized by being provided.
According to a twentieth aspect of the invention, in the semiconductor device manufacturing method according to the twentieth aspect, the planar shape of the first opening of the upper insulating film is a solid shape of the semiconductor structure. According to the planar shape of the common columnar electrode, it is formed so as to be larger than the planar shape of the second opening of the upper insulating film.
According to a twenty-first aspect of the present invention, in the method of manufacturing a semiconductor device according to the thirteenth aspect of the present invention, the step of forming the common upper layer wiring and the upper layer wiring includes first and second steps of the upper insulating film. Forming a base metal layer on the entire upper insulating film including the inside of the opening, and forming a common upper layer upper metal layer and an upper layer upper metal layer by electrolytic plating on the base metal layer; Grinding the upper surface side of the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring so that the upper surface of the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring are flush with each other; And a step of removing the base metal layer in a region other than the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring.
A method of manufacturing a semiconductor device according to a twenty-second aspect is the method according to the thirteenth aspect, wherein an overcoat film is formed to cover a plurality of portions of the common upper layer wiring and portions other than the connection pads of the upper layer wiring. It has the process to perform.
A method of manufacturing a semiconductor device according to a twenty-third aspect of the present invention is the method of manufacturing the semiconductor device according to the twenty-second aspect, comprising the step of forming solder balls on a plurality of portions of the common upper layer wiring and on connection pads of the upper layer wiring. It is characterized by having.
According to a twenty-fourth aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-third aspect, the number of the solder balls formed on a plurality of locations of the common upper layer wiring is the same for the common signal. It is the same as the number of connection pads.

この発明によれば、半導体構成体において、絶縁膜上において接続パッドのうち共通の信号用の複数の接続パッドを含む領域にベタ状の共通配線を当該接続パッドの全てに接続させて設けているので、半導体構成体の共通配線に電源信号等の過大電流が流れても、当該共通配線が焼き切れないようにすることができる。この場合、半導体構成体の共通柱状電極に対応する部分における上層絶縁膜に１つの第１の開口部を設け、上層絶縁膜上にベタ状の共通上層配線を上層絶縁膜の第１の開口部を介して半導体構成体の共通柱状電極に接続させることにより、上層絶縁膜の第１の開口部の部分を低抵抗化することができ、電流容量を向上させることができる。   According to the present invention, in the semiconductor structure, the solid common wiring is connected to all of the connection pads in the region including a plurality of connection pads for common signals among the connection pads on the insulating film. Therefore, even if an excessive current such as a power supply signal flows through the common wiring of the semiconductor structure, the common wiring can be prevented from being burned out. In this case, one first opening is provided in the upper insulating film in the portion corresponding to the common columnar electrode of the semiconductor structure, and the solid common upper layer wiring is provided on the upper insulating film as the first opening of the upper insulating film. By connecting to the common columnar electrode of the semiconductor structure via the first insulating layer, the resistance of the first opening portion of the upper insulating film can be reduced, and the current capacity can be improved.

この発明の第１実施形態としての半導体装置の透過平面図。1 is a transparent plan view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の適当な部分の断面図。FIG. 2 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. 1. 図１および図２に示す半導体装置の製造方法の一例において、当初準備したものの断面図。Sectional drawing of what was initially prepared in an example of the manufacturing method of the semiconductor device shown in FIG.1 and FIG.2. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１６に続く工程の断面図。FIG. 17 is a cross-sectional view of the process following FIG. 16. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17. 図１８に続く工程の断面図。FIG. 19 is a cross-sectional view of the process following FIG. 18. この発明の第２実施形態としての半導体装置の透過平面図。The permeation | transmission top view of the semiconductor device as 2nd Embodiment of this invention. 図２０に示す半導体装置の適当な部分の断面図。FIG. 21 is a cross-sectional view of a suitable portion of the semiconductor device shown in FIG. 20.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の透過平面図を示し、図２は図１に示す半導体装置の適当な部分の断面図を示す。この半導体装置は、ガラス布基材エポキシ樹脂等からなる平面方形状のベース板１を備えている。ベース板１の上面中央部には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。 (First embodiment)
FIG. 1 is a transparent plan view of a semiconductor device as a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. This semiconductor device includes a planar rectangular base plate 1 made of glass cloth base epoxy resin or the like. The lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded to the central portion of the upper surface of the base plate 1 via an adhesive layer 3 made of a die bond material.

半導体構成体２は、一般的にはＣＳＰと呼ばれるものであり、シリコン基板（半導体基板）４を備えている。シリコン基板４の下面は接着層３を介してベース板１の上面中央部に接着されている。シリコン基板４の上面には所定の機能の集積回路を構成する素子、例えば、トランジスタ、ダイオード、抵抗、コンデンサ等の素子（図示せず）が形成され、その上面周辺部には、上記集積回路の各素子に接続されたアルミニウム系金属等からなる複数の接続パッド５ａ、５ｂ、５ｃが設けられている。   The semiconductor structure 2 is generally called a CSP and includes a silicon substrate (semiconductor substrate) 4. The lower surface of the silicon substrate 4 is bonded to the central portion of the upper surface of the base plate 1 through the adhesive layer 3. On the upper surface of the silicon substrate 4 are formed elements (not shown) such as transistors, diodes, resistors, capacitors, etc. constituting an integrated circuit having a predetermined function. A plurality of connection pads 5a, 5b, and 5c made of an aluminum-based metal or the like connected to each element are provided.

ここで、一例として、図１において、シリコン基板４上の左上側に４個配置された符号５ａで示す接続パッドは、共通の電源信号用である。シリコン基板４上の左下側に４個配置された符号５ｂで示す接続パッドは、共通のグランド信号用である。シリコン基板４上の右上側および右下側にそれぞれ４個ずつ配置された符号５ｃで示す接続パッドは、それ以外の通常信号用である。ここで、図２において、グランド信号用の接続パッド５ｂおよびそれに関連する部分については、電源信号用の接続パッド５ａおよびそれに関連する部分とほぼ同様であるので、かっこを付けて示す。   Here, as an example, in FIG. 1, four connection pads indicated by reference numeral 5a arranged on the upper left side on the silicon substrate 4 are for a common power supply signal. Four connection pads denoted by reference numeral 5b arranged on the lower left side on the silicon substrate 4 are for a common ground signal. The four connection pads indicated by reference numeral 5c arranged on the upper right side and the lower right side on the silicon substrate 4 are for other normal signals. Here, in FIG. 2, the connection pad 5b for ground signal and the portion related thereto are substantially the same as the connection pad 5a for power signal and the portion related thereto, and therefore are shown with parentheses.

シリコン基板４の周辺部および接続パッド５ａ、５ｂ、５ｃの中央部を除くシリコン基板４の上面には酸化シリコン等からなるパッシベーション膜（絶縁膜）６が設けられ、接続パッド５ａ、５ｂ、５ｃの中央部はパッシベーション膜６に設けられた開口部７ａ、７ｂ、７ｃを介して露出されている。パッシベーション膜６の上面にはポリイミド系樹脂等からなる保護膜（絶縁膜）８が設けられている。パッシベーション膜６の開口部７ａ、７ｂ、７ｃに対応する部分における保護膜８には開口部９ａ、９ｂ、９ｃが設けられている。   A passivation film (insulating film) 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the peripheral portion of the silicon substrate 4 and the central portions of the connection pads 5a, 5b, and 5c, and the connection pads 5a, 5b, and 5c. The central portion is exposed through openings 7 a, 7 b, 7 c provided in the passivation film 6. A protective film (insulating film) 8 made of polyimide resin or the like is provided on the upper surface of the passivation film 6. Openings 9a, 9b, and 9c are provided in the protective film 8 at portions corresponding to the openings 7a, 7b, and 7c of the passivation film 6.

保護膜８の上面には配線１０ａ、１０ｂ、１０ｃが設けられている。配線１０ａ、１０ｂ、１０ｃは、保護膜８の上面に設けられた銅等からなる下地金属層１１ａ、１１ｂ、１１ｃと、下地金属層１１の上面に設けられた銅からなる上部金属層１２ａ、１２ｂ、１２ｃとの２層構造となっている。   Wirings 10 a, 10 b and 10 c are provided on the upper surface of the protective film 8. The wirings 10 a, 10 b, and 10 c include base metal layers 11 a, 11 b, and 11 c made of copper or the like provided on the upper surface of the protective film 8, and upper metal layers 12 a and 12 b made of copper provided on the upper surface of the base metal layer 11. , 12c.

この場合、図１に示すように、符号１０ａで示す配線（共通配線）は、シリコン基板４上の左上側において、４個の電源信号用の接続パッド５ａを含む平面方形状の領域にベタ状に配置されたものからなり、パッシベーション膜６および保護膜８の開口部７ａ、９ａを介して４個の電源信号用の接続パッド５ａの全てに接続されている。   In this case, as shown in FIG. 1, the wiring (common wiring) denoted by reference numeral 10a is solid in a planar rectangular region including the four power supply signal connection pads 5a on the upper left side on the silicon substrate 4. And is connected to all four power supply signal connection pads 5a through the openings 7a and 9a of the passivation film 6 and the protective film 8.

符号１０ｂで示す配線（共通配線）は、シリコン基板４上の左下側において、４個のグランド信号用の接続パッド５ｂを含む平面方形状の領域にベタ状に配置されたものからなり、パッシベーション膜６および保護膜８の開口部７ｂ、９ｂを介して４個のグランド信号用の接続パッド５ｂの全てに接続されている。   The wiring (common wiring) indicated by reference numeral 10b is a solid film disposed in a planar rectangular region including four ground signal connection pads 5b on the lower left side of the silicon substrate 4, and is formed from a passivation film. 6 and the openings 7b and 9b of the protective film 8 are connected to all of the four ground signal connection pads 5b.

符号１０ｃで示す配線は、シリコン基板４上の右側の領域に配置され、パッシベーション膜６および保護膜８の開口部７ｃ、９ｃを介して通常信号用の接続パッド５ｃに接続された接続部１０ｃ−１、平面円形状の接続パッド部１０ｃ−２およびその間の引き回し線部１０ｃ−３を有するものからなっている。   The wiring indicated by reference numeral 10c is arranged in the right region on the silicon substrate 4 and is connected to the normal signal connection pad 5c through the openings 7c and 9c of the passivation film 6 and the protective film 8- 1. It has a planar circular connection pad portion 10c-2 and a lead wire portion 10c-3 therebetween.

符号１０ａで示す平面方形状の配線の上面の所定の４箇所には銅からなる平面円形状の柱状電極（共通柱状電極）１３ａが設けられている。符号１０ｂで示す平面方形状の配線の上面の所定の４箇所には銅からなる平面円形状の柱状電極（共通柱状電極）１３ｂが設けられている。符号１０ｃで示す配線の接続パッド部１０ｃ−２の上面には銅からなる平面円形状の柱状電極１３ｃが設けられている。   Planar circular columnar electrodes (common columnar electrodes) 13a made of copper are provided at predetermined four locations on the upper surface of the planar rectangular wiring denoted by reference numeral 10a. Planar circular columnar electrodes (common columnar electrodes) 13b made of copper are provided at predetermined four locations on the upper surface of the planar rectangular wiring indicated by reference numeral 10b. A planar circular columnar electrode 13c made of copper is provided on the upper surface of the connection pad portion 10c-2 of the wiring indicated by reference numeral 10c.

ここで、柱状電極１３ａ、１３ｂの各本数は、電源信号用およびグランド信号用の接続パッド５ａ、５ｂの各個数と同一となっている。また、柱状電極１３ａ、１３ｂは柱状電極１３ｃと同一形状となっている。さらに、図１に示すように、合計１６本の柱状電極１３ａ、１３ｂ、１３ｃはマトリクス状に配置されている。   Here, the number of columnar electrodes 13a and 13b is the same as the number of connection pads 5a and 5b for power supply signals and ground signals. The columnar electrodes 13a and 13b have the same shape as the columnar electrode 13c. Further, as shown in FIG. 1, a total of 16 columnar electrodes 13a, 13b, 13c are arranged in a matrix.

配線１０ａ、１０ｂ、１０ｃを含む保護膜８の上面において柱状電極１３ａ、１３ｂ、１３ｃの周囲にはエポキシ系樹脂等からなる封止膜１４が設けられている。柱状電極１３ａ、１３ｂ、１３ｃは、その上面が封止膜１４の上面と面一乃至数μｍ低くなるように設けられている。以上で、半導体構成体２の構造についての説明を終了する。   A sealing film 14 made of an epoxy resin or the like is provided around the columnar electrodes 13a, 13b, and 13c on the upper surface of the protective film 8 including the wirings 10a, 10b, and 10c. The columnar electrodes 13 a, 13 b, and 13 c are provided so that their upper surfaces are one to several μm lower than the upper surface of the sealing film 14. Above, description about the structure of the semiconductor structure 2 is complete | finished.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の絶縁層２１が設けられている。絶縁層２１は、例えば、エポキシ系樹脂等の熱硬化性樹脂中にシリカフラー等の無機材料からなる補強材を分散させたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   A rectangular frame-shaped insulating layer 21 is provided on the upper surface of the base plate 1 around the semiconductor structure 2. The insulating layer 21 is made of, for example, a material in which a reinforcing material made of an inorganic material such as silica fuller is dispersed in a thermosetting resin such as an epoxy resin, or a thermosetting resin such as an epoxy resin.

半導体構成体２および絶縁層２１の上面には上層絶縁膜２２が設けられている。上層絶縁膜２２は、例えば、ガラス布等の基材にエポキシ系樹脂等の熱硬化性樹脂を含浸させたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   An upper insulating film 22 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. The upper insulating film 22 is made of, for example, a material such as a glass cloth impregnated with a thermosetting resin such as an epoxy resin, or a thermosetting resin such as an epoxy resin.

半導体構成体２の各４本の柱状電極１３ａ、１３ｂを含む平面方形状の領域に対応する部分における上層絶縁膜２２には平面方形状の開口部（第１の開口部）２３ａ、２３ｂが設けられている。半導体構成体２の柱状電極１３ｃの上面中央部に対応する部分における上層絶縁膜２２には平面円形状の開口部（第２の開口部）２３ｃが設けられている。   Planar rectangular openings (first openings) 23a and 23b are provided in the upper insulating film 22 in the portion corresponding to the planar rectangular region including the four columnar electrodes 13a and 13b of the semiconductor structure 2 respectively. It has been. A planar circular opening (second opening) 23c is provided in the upper insulating film 22 in a portion corresponding to the center of the upper surface of the columnar electrode 13c of the semiconductor structure 2.

上層絶縁膜２２の上面には上層配線２４ａ、２４ｂ、２４ｃが設けられている。上層配線２４ａ、２４ｂ、２４ｃは、上層絶縁膜２２の上面に設けられた銅等からなる下地金属層２５ａ、２５ｂ、２５ｃと、下地金属層２５ａ、２５ｂ、２５ｃの上面に設けられた銅からなる上部金属層２６ａ、２６ｂ、２６ｃとの２層構造となっている。   Upper layer wirings 24 a, 24 b and 24 c are provided on the upper surface of the upper layer insulating film 22. The upper wirings 24a, 24b, and 24c are made of the base metal layers 25a, 25b, and 25c made of copper or the like provided on the upper surface of the upper insulating film 22, and the copper provided on the upper surfaces of the base metal layers 25a, 25b, and 25c. It has a two-layer structure with upper metal layers 26a, 26b, and 26c.

この場合、図１に示すように、符号２４ａで示す上層配線（共通上層配線）は、上層絶縁膜２２上の左上側において、上層絶縁膜２２の平面方形状の開口部２３ａを含む領域にベタ状に配置され、上層絶縁膜２２の１つの平面方形状の開口部２３ａを介して半導体構成体２の４本の電源信号用の柱状電極１３ａの全ての上面に接続されている。ここで、上層配線２４ａは、上層絶縁膜２２の開口部２３ａ内において、半導体構成体２の４本の柱状電極１３ａの上面およびその周囲における封止膜１４の上面に設けられている。   In this case, as shown in FIG. 1, the upper layer wiring (common upper layer wiring) indicated by reference numeral 24 a is solid on the upper left side of the upper layer insulating film 22 in the region including the planar rectangular opening 23 a. And is connected to all the upper surfaces of the four power supply signal columnar electrodes 13a of the semiconductor structure 2 through one planar rectangular opening 23a of the upper insulating film 22. Here, the upper layer wiring 24 a is provided in the opening 23 a of the upper layer insulating film 22 on the upper surface of the four columnar electrodes 13 a of the semiconductor structure 2 and on the upper surface of the sealing film 14 around it.

符号２４ｂで示す上層配線（共通上層配線）は、上層絶縁膜２２上の左下側において、上層絶縁膜２２の平面方形状の開口部２３ｂを含む領域にベタ状に配置され、上層絶縁膜２２の１つの平面方形状の開口部２３ｂを介して半導体構成体２の４本のグランド信号用の柱状電極１３ｂの全ての上面に接続されている。この場合も、上層配線２４ｂは、上層絶縁膜２２の開口部２３ｂ内において、半導体構成体２の４本の柱状電極１３ｂの上面およびその周囲における封止膜１４の上面に設けられている。   The upper layer wiring (common upper layer wiring) indicated by reference numeral 24 b is arranged in a solid shape in the lower left side on the upper insulating film 22 in a region including the planar rectangular opening 23 b of the upper insulating film 22. It is connected to all the upper surfaces of the four ground signal columnar electrodes 13b of the semiconductor structure 2 through one planar rectangular opening 23b. Also in this case, the upper layer wiring 24 b is provided in the opening 23 b of the upper layer insulating film 22 on the upper surface of the four columnar electrodes 13 b of the semiconductor structure 2 and the upper surface of the sealing film 14 in the periphery thereof.

符号２４ｃで示す上層配線は、半導体構成体２の符号１０ｃで示す配線と同様に、接続部、接続パッド部およびその間の引き回し線部を有するものからなり、上層絶縁膜２２の平面円形状の開口部２３ｃを介して半導体構成体２の柱状電極１３ｃの上面中央部に接続されている。ここで、図２に示すように、上層配線２４ａ、２４ｂ、２４ｃの上面は面一となっている。   Similar to the wiring indicated by reference numeral 10 c of the semiconductor structure 2, the upper wiring indicated by reference numeral 24 c has a connection part, a connection pad part, and a lead-out line part therebetween, and a planar circular opening of the upper insulating film 22. The central portion of the upper surface of the columnar electrode 13c of the semiconductor structure 2 is connected via the portion 23c. Here, as shown in FIG. 2, the upper surfaces of the upper layer wirings 24a, 24b, and 24c are flush with each other.

上層配線２４ａ、２４ｂ、２４ｃを含む上層絶縁膜２２の上面にはソルダーレジスト等からなるオーバーコート膜２７が設けられている。上層配線２４ａ、２４ｂの周辺部の各所定の４箇所に対応する部分におけるオーバーコート膜２７には開口部２８ａ、２８ｂが設けられている。上層配線２４ｃの接続パッド部に対応する部分におけるオーバーコート膜２７には開口部２８ｃが設けられている。   An overcoat film 27 made of a solder resist or the like is provided on the upper surface of the upper insulating film 22 including the upper wirings 24a, 24b, and 24c. Openings 28a and 28b are provided in the overcoat film 27 in the portions corresponding to the respective four predetermined positions in the peripheral portions of the upper layer wirings 24a and 24b. An opening 28c is provided in the overcoat film 27 in a portion corresponding to the connection pad portion of the upper layer wiring 24c.

オーバーコート膜２７の開口部２８ａ、２８ｂ、２８ｃ内およびその上方には半田ボール２９ａ、２９ｂ、２９ｃが上層配線２４ａ、２４ｂ、２４ｃに接続されて設けられている。この場合、図１に示すように、半田ボール２９ａ、２９ｂ、２９ｃは半導体構成体２の周囲にのみ配置されている。また、半田ボール２９ａ、２９ｂの数はそれぞれ４個であり、半導体構成体２の電源信号用およびグランド信号用の接続パッド５ａ、５ｂの数（４個）と同一となっている。   Solder balls 29a, 29b, and 29c are provided in and above the openings 28a, 28b, and 28c of the overcoat film 27 so as to be connected to the upper layer wirings 24a, 24b, and 24c. In this case, as shown in FIG. 1, the solder balls 29 a, 29 b, 29 c are arranged only around the semiconductor structure 2. The number of solder balls 29a and 29b is four, which is the same as the number (four) of connection pads 5a and 5b for power supply signals and ground signals of the semiconductor structure 2.

以上のように、この半導体装置では、半導体構成体２の電源信号用の配線１０ａおよびグランド信号用の配線１０ｂを平面方形状のベタ状とし、それぞれ４個の接続パッド５ａ、５ｂの全てに接続させているので、電源信号用の配線１０ａおよびグランド信号用の配線１０ｂに過大電流が流れても、これらの配線１０ａ、１０ｂが焼き切れないようにすることができる。   As described above, in this semiconductor device, the power signal wiring 10a and the ground signal wiring 10b of the semiconductor structure 2 are formed in a planar rectangular shape and connected to all four connection pads 5a and 5b, respectively. Therefore, even if an excessive current flows through the power supply signal wiring 10a and the ground signal wiring 10b, the wirings 10a and 10b can be prevented from being burned out.

また、半導体構成体２の各４本の電源信号用およびグランド信号用の柱状電極１３ａ、１３ｂに対応する部分における上層絶縁膜２２にそれぞれ１つの平面方形状の開口部２３ａ、２３ｂを設け、上層絶縁膜２２上にベタ状の上層配線２４ａ、２４ｂを上層絶縁膜２２の開口部２３ａ、２３ｂを介して半導体構成体２の各４本の柱状電極１３ａ、１３ｂの全てに接続させて設けているので、上層絶縁膜２２の開口部２３ａ、２３ｂの部分を低抵抗化することができ、ひいては電流容量を向上させることができる。   Also, one planar rectangular openings 23a and 23b are provided in the upper insulating film 22 in portions corresponding to the four power supply signal and ground signal columnar electrodes 13a and 13b of the semiconductor structure 2, respectively. Solid upper layer wirings 24 a and 24 b are provided on the insulating film 22 through the openings 23 a and 23 b of the upper insulating film 22 so as to be connected to all four columnar electrodes 13 a and 13 b of the semiconductor structure 2. Therefore, the resistance of the openings 23a and 23b of the upper insulating film 22 can be reduced, and the current capacity can be improved.

ここで、この半導体装置の一部の寸法について説明する。ベース板１のサイズは３×３ｍｍである。半導体構成体２のサイズは２×２ｍｍである。半導体構成体２の配線１０ｃの引き回し線部１０ｃ−３の線幅は２０μｍである。半導体構成体２の柱状電極１３ａ、１３ｂ、１３ｃの直径は０．２ｍｍ、ピッチは０．４ｍｍである。上層絶縁膜２２の平面円形状の開口部２３ｃの直径は１００μｍである。半田ボール２９ａ、２９ｂ、２９ｃの直径は０．３ｍｍ、ピッチは０．６５ｍｍである。   Here, some dimensions of the semiconductor device will be described. The size of the base plate 1 is 3 × 3 mm. The size of the semiconductor structure 2 is 2 × 2 mm. The line width of the lead line portion 10c-3 of the wiring 10c of the semiconductor structure 2 is 20 μm. The diameters of the columnar electrodes 13a, 13b, 13c of the semiconductor structure 2 are 0.2 mm, and the pitch is 0.4 mm. The diameter of the planar circular opening 23c of the upper insulating film 22 is 100 μm. The solder balls 29a, 29b, 29c have a diameter of 0.3 mm and a pitch of 0.65 mm.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、グランド信号用の接続パッド５ｂおよびそれに関連する部分については、電源信号用の接続パッド５ａおよびそれに関連する部分とほぼ同様であるので、その説明は省略する。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, the connection pad 5b for the ground signal and the portion related thereto are substantially the same as the connection pad 5a for the power supply signal and the portion related thereto, and thus the description thereof is omitted.

まず、図３に示すように、ウエハ状態のシリコン基板（以下、半導体ウエハ３１という）の上面に接続パッド５ａ、５ｃ、パッシベーション膜６および保護膜８が形成され、接続パッド５ａ、５ｃの中央部がパッシベーション膜６の開口部７ａ、７ｃおよび保護膜８の開口部９ａ、９ｃを介して露出されたものを準備する。   First, as shown in FIG. 3, connection pads 5a and 5c, a passivation film 6 and a protective film 8 are formed on the upper surface of a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 31), and the central portions of the connection pads 5a and 5c. Are exposed through the openings 7 a and 7 c of the passivation film 6 and the openings 9 a and 9 c of the protective film 8.

この場合、半導体ウエハ３１の厚さは、図２に示すシリコン基板４の厚さよりも厚くなっている。なお、図３において、符号３２で示す領域はダイシングストリートである。そして、ダイシングストリート３２およびその両側に対応する部分におけるパッシベーション膜６および保護膜８は除去されている。   In this case, the semiconductor wafer 31 is thicker than the silicon substrate 4 shown in FIG. In FIG. 3, the area indicated by reference numeral 32 is a dicing street. Then, the passivation film 6 and the protective film 8 in the portions corresponding to the dicing street 32 and both sides thereof are removed.

次に、図４に示すように、パッシベーション膜６の開口部７ａ、７ｃおよび保護膜８の開口部９ａ、９ｃを介して露出された接続パッド５ａ、５ｃの上面を含む保護膜８の上面全体に下地金属層３３を形成する。この場合、下地金属層３３は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 4, the entire upper surface of the protective film 8 including the upper surfaces of the connection pads 5 a and 5 c exposed through the openings 7 a and 7 c of the passivation film 6 and the openings 9 a and 9 c of the protective film 8. A base metal layer 33 is formed. In this case, the base metal layer 33 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層３３の上面にポジ型の液状レジストからなるメッキレジスト膜３４をパターン形成する。この場合、上部金属層１２ａ、１２ｃ形成領域に対応する部分におけるメッキレジスト膜３４には開口部３５ａ、３５ｃが形成されている。次に、下地金属層３３をメッキ電流路とした銅の電解メッキを行なうと、メッキレジスト膜３４の開口部３５ａ、３５ｃ内の下地金属層３３の上面に上部金属層１２ａ、１２ｃが形成される。次に、メッキレジスト膜３４を剥離する。   Next, a plating resist film 34 made of a positive liquid resist is patterned on the upper surface of the base metal layer 33. In this case, openings 35a and 35c are formed in the plating resist film 34 in portions corresponding to the formation regions of the upper metal layers 12a and 12c. Next, when copper electroplating is performed using the base metal layer 33 as a plating current path, the upper metal layers 12 a and 12 c are formed on the upper surface of the base metal layer 33 in the openings 35 a and 35 c of the plating resist film 34. . Next, the plating resist film 34 is peeled off.

次に、図５に示すように、下地金属層３３の上面にネガ型のドライフィルムレジストからなるメッキレジスト膜３６をパターン形成する。この場合、上部金属層１２ａの所定の４箇所（柱状電極１３ａ形成領域）および上部金属層１２ｃの接続パッド部（柱状電極１３ｃ形成領域）に対応する部分におけるメッキレジスト膜３６には開口部３７ａ、３７ｃが形成されている。   Next, as shown in FIG. 5, a plating resist film 36 made of a negative dry film resist is patterned on the upper surface of the base metal layer 33. In this case, there are openings 37a in the plating resist film 36 at portions corresponding to predetermined four locations (columnar electrode 13a formation region) of the upper metal layer 12a and connection pad portions (columnar electrode 13c formation region) of the upper metal layer 12c. 37c is formed.

次に、下地金属層３３をメッキ電流路とした銅の電解メッキを行なうと、メッキレジスト膜３６の開口部３７ａ内の上部金属層１２ａの上面に柱状電極１３ａが形成され、且つ、メッキレジスト膜３６の開口部３７ｃ内の上部金属層１２ｃの接続パッド部上面に柱状電極１３ｃが形成される。次に、メッキレジスト膜３６を剥離する。   Next, when copper is electroplated using the base metal layer 33 as a plating current path, the columnar electrode 13a is formed on the upper surface of the upper metal layer 12a in the opening 37a of the plating resist film 36, and the plating resist film A columnar electrode 13 c is formed on the upper surface of the connection pad portion of the upper metal layer 12 c in the opening 37 c of 36. Next, the plating resist film 36 is peeled off.

次に、上部金属層１２ａ、１２ｃをマスクとして該上部金属層１２ａ、１２ｃ下以外の領域における下地金属層３３をエッチングして除去すると、図６に示すように、上部金属層１２ａ、１２ｃ下にのみ下地金属層１１ａ、１１ｃが残存される。この状態では、上部金属層１２ａ、１２ｃとその下に残存された下地金属層１１ａ、１１ｃとにより、２層構造の配線１０ａ、１０ｃが形成されている。   Next, when the base metal layer 33 is removed by etching using the upper metal layers 12a and 12c as a mask, the underlying metal layer 33 is removed under the upper metal layers 12a and 12c as shown in FIG. Only the base metal layers 11a and 11c remain. In this state, the upper metal layers 12a and 12c and the underlying metal layers 11a and 11c remaining under the upper metal layers 12a and 12c form wirings 10a and 10c having a two-layer structure.

次に、図７に示すように、ダイシングストリート３２およびその両側における半導体ウエハ３１の上面並びに配線１０ａ、１０ｃおよび柱状電極１３ａ、１３ｃを含む保護膜８の上面にスピンコート法等によりエポキシ系樹脂等からなる封止膜１４をその厚さが柱状電極１３ａ、１３ｃの高さよりもやや厚くなるように形成する。したがって、この状態では、柱状電極１３ａ、１３ｃの上面は封止膜１４によって覆われている。   Next, as shown in FIG. 7, an epoxy resin or the like is applied to the upper surface of the dicing street 32 and the upper surface of the semiconductor wafer 31 on both sides and the upper surface of the protective film 8 including the wirings 10a and 10c and the columnar electrodes 13a and 13c by spin coating or the like. The sealing film 14 made of is formed so that its thickness is slightly thicker than the height of the columnar electrodes 13a and 13c. Therefore, in this state, the upper surfaces of the columnar electrodes 13 a and 13 c are covered with the sealing film 14.

次に、封止膜１４の上面側を適宜に研削し、図８に示すように、柱状電極１３ａ、１３ｃの上面を露出させ、且つ、この露出された柱状電極１３ａ、１３ｃの上面を含む封止膜１４の上面を平坦化する。次に、図９に示すように、半導体ウエハ３１の下面側を適宜に研削し、半導体ウエハ３１の厚さを薄くする。   Next, the upper surface side of the sealing film 14 is appropriately ground to expose the upper surfaces of the columnar electrodes 13a and 13c and to include the exposed upper surfaces of the columnar electrodes 13a and 13c as shown in FIG. The upper surface of the stop film 14 is flattened. Next, as shown in FIG. 9, the lower surface side of the semiconductor wafer 31 is appropriately ground to reduce the thickness of the semiconductor wafer 31.

次に、図１０に示すように、半導体ウエハ３１の下面に接着層３を接着する。接着層３は、エポキシ系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態で半導体ウエハ３１の下面に固着される。次に、図１１に示すように、封止膜１４、半導体ウエハ３１および接着層３をダイシングストリート３２に沿って切断すると、下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 10, the adhesive layer 3 is bonded to the lower surface of the semiconductor wafer 31. The adhesive layer 3 is made of a die bond material such as an epoxy resin, and is fixed to the lower surface of the semiconductor wafer 31 in a semi-cured state by heating and pressing. Next, as shown in FIG. 11, when the sealing film 14, the semiconductor wafer 31, and the adhesive layer 3 are cut along the dicing street 32, a plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface are obtained.

次に、図１１に示す半導体構成体２を用いて、図２に示す半導体装置を製造する場合の一例について説明する。この場合も、グランド信号用の接続パッド５ｂに関連する部分については、電源信号用の接続パッド５ａに関連する部分とほぼ同様であるので、その説明は省略する。   Next, an example of manufacturing the semiconductor device shown in FIG. 2 using the semiconductor structure 2 shown in FIG. 11 will be described. Also in this case, the portion related to the connection pad 5b for ground signal is substantially the same as the portion related to the connection pad 5a for power signal, and the description thereof is omitted.

まず、図１２に示すように、図２に示す完成された半導体装置を複数個形成することが可能な面積を有するガラス布基材エポキシ樹脂等からなるベース板１を準備する。ベース板１は、限定する意味ではないが、例えば、平面方形状である。なお、図１２において、符号４１で示す領域は、個片化するための切断ラインに対応する領域である。   First, as shown in FIG. 12, a base plate 1 made of glass cloth base epoxy resin or the like having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 2 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape. In FIG. 12, an area denoted by reference numeral 41 is an area corresponding to a cutting line for singulation.

次に、ベース板１の上面の複数の半導体構成体配置領域に複数の半導体構成体２のシリコン基板４の下面に固着された接着層３を相互に離間させて接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, the adhesive layers 3 fixed to the lower surface of the silicon substrate 4 of the plurality of semiconductor structures 2 are bonded to the plurality of semiconductor structure arrangement regions on the upper surface of the base plate 1 while being separated from each other. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、図１３に示すように、半導体構成体２の周囲におけるベース板１の上面に格子状の絶縁層形成用シート２１ａをピン等で位置決めしながら配置する。格子状の絶縁層形成用シート２１ａは、例えば、エポキシ系樹脂等の熱硬化性樹脂中に補強材を分散させ、熱硬化性樹脂を半硬化状態にしてシート状となし、パンチング等により、複数の方形状の開口部を形成したものである。   Next, as shown in FIG. 13, a lattice-shaped insulating layer forming sheet 21 a is arranged on the upper surface of the base plate 1 around the semiconductor structure 2 while being positioned with pins or the like. For example, the lattice-shaped insulating layer forming sheet 21a is formed by dispersing a reinforcing material in a thermosetting resin such as an epoxy-based resin and making the thermosetting resin semi-cured into a sheet shape. A rectangular opening is formed.

次に、半導体構成体２および絶縁層形成用シート２１ａの上面に上層絶縁膜形成用シート２２ａを配置する。上層絶縁膜形成用シート２２ａは、例えば、ガラス布等にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。   Next, the upper insulating film forming sheet 22a is disposed on the upper surfaces of the semiconductor structure 2 and the insulating layer forming sheet 21a. The upper insulating film forming sheet 22a is formed, for example, by impregnating a glass cloth or the like with a thermosetting resin such as an epoxy resin and making the thermosetting resin semi-cured into a sheet shape.

次に、一対の加熱加圧板４２、４３を用いて上下から絶縁層形成用シート２１ａおよび上層絶縁膜形成用シート２２ａを加熱加圧する。そして、その後の冷却により、半導体構成体２の周囲におけるベース板１の上面に方形枠状の絶縁層２１が形成され、また、半導体構成体２および絶縁層２１の上面に上層絶縁膜２２が形成される。この場合、上層絶縁膜２２の上面は、上側の加熱加圧板４２の下面によって押さえ付けられるため、平坦面となる。   Next, the insulating layer forming sheet 21a and the upper insulating film forming sheet 22a are heated and pressed from above and below using the pair of heating and pressing plates 42 and 43. Then, by subsequent cooling, a rectangular frame-shaped insulating layer 21 is formed on the upper surface of the base plate 1 around the semiconductor structure 2, and an upper insulating film 22 is formed on the upper surfaces of the semiconductor structure 2 and the insulating layer 21. Is done. In this case, since the upper surface of the upper insulating film 22 is pressed by the lower surface of the upper heating and pressing plate 42, it becomes a flat surface.

次に、図１４に示すように、レーザビームを照射するレーザ加工により、半導体構成体２の４本の柱状電極１３ａを含む平面方形状の領域に対応する部分における上層絶縁膜２２に平面方形状の開口部２３ａを形成し、且つ、半導体構成体２の柱状電極１３ｃの上面中央部に対応する部分における上層絶縁膜２２に平面円形状の開口部２３ｃを形成する。この状態では、柱状電極１３ａの周囲における封止膜１４の上面は平面方形状の開口部２３ａを介して露出されている。   Next, as shown in FIG. 14, a planar rectangular shape is formed on the upper insulating film 22 in a portion corresponding to the planar rectangular region including the four columnar electrodes 13a of the semiconductor structure 2 by laser processing with laser beam irradiation. And a planar circular opening 23c is formed in the upper insulating film 22 in a portion corresponding to the center of the upper surface of the columnar electrode 13c of the semiconductor structure 2. In this state, the upper surface of the sealing film 14 around the columnar electrode 13a is exposed through the planar rectangular opening 23a.

次に、図１５に示すように、上層絶縁膜２２の開口部２３ａを介して露出された半導体構成体２の柱状電極１３ａおよび封止膜１４の上面並びに上層絶縁膜２２の開口部２３ｃを介して露出された半導体構成体２の柱状電極１３ｃの上面を含む上層絶縁膜２２の上面全体に下地金属層４４を形成する。この場合も、下地金属層４４は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 15, the upper surface of the columnar electrode 13 a and the sealing film 14 of the semiconductor structure 2 exposed through the opening 23 a of the upper insulating film 22 and the opening 23 c of the upper insulating film 22 are exposed. A base metal layer 44 is formed on the entire upper surface of the upper insulating film 22 including the upper surface of the columnar electrode 13c of the semiconductor structure 2 exposed in this manner. Also in this case, the base metal layer 44 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and may be made of titanium or the like formed by sputtering. A copper layer may be formed on the thin film layer by sputtering.

次に、下地金属層４４の上面にメッキレジスト膜４５をパターン形成する。この場合、上部金属層２６ａ、２６ｃ形成領域に対応する部分におけるメッキレジスト膜４５には開口部４６ａ、４６ｃが形成されている。次に、下地金属層４４をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜４５の開口部４６ａ、４６ｃ内の下地金属層４４の上面に上部金属層２６ａ、２６ｃを形成する。   Next, a plating resist film 45 is patterned on the upper surface of the base metal layer 44. In this case, openings 46a and 46c are formed in the plating resist film 45 in portions corresponding to the formation regions of the upper metal layers 26a and 26c. Next, the upper metal layers 26 a and 26 c are formed on the upper surface of the base metal layer 44 in the openings 46 a and 46 c of the plating resist film 45 by performing electrolytic plating of copper using the base metal layer 44 as a plating current path. .

この場合、銅メッキは下地金属層４４の上面に等方的に形成されるため、上層絶縁膜２２の開口部２３ａ内における下地金属層４４の上面に形成される上部金属層２６ａの最も薄い部分の厚さが図２に示す上部金属層２６ａの厚さと同じかそれ以上の厚さとなるようにする。次に、メッキレジスト膜４５を剥離する。次に、上部金属層２６ａ、２６ｃの上面側を適宜に研削し、図１６に示すように、上部金属層２６ａ、２６ｃの上面が面一となるようにする。   In this case, since the copper plating is isotropically formed on the upper surface of the base metal layer 44, the thinnest portion of the upper metal layer 26 a formed on the upper surface of the base metal layer 44 in the opening 23 a of the upper insulating film 22. Is set to be equal to or greater than the thickness of the upper metal layer 26a shown in FIG. Next, the plating resist film 45 is peeled off. Next, the upper surface sides of the upper metal layers 26a and 26c are appropriately ground so that the upper surfaces of the upper metal layers 26a and 26c are flush with each other as shown in FIG.

次に、上部金属層２６ａ、２６ｃをマスクとして該上部金属層２６ａ、２６ｃ下以外の領域における下地金属層４４をエッチングして除去すると、図１７に示すように、上部金属層２６ａ、２６ｃ下にのみ下地金属層２５ａ、２５ｃが残存される。この状態では、上部金属層２６ａ、２６ｃおよびその下に残存された下地金属層２５ａ、２５ｃにより、上層配線２４ａ、２４ｃが形成されている。   Next, when the upper metal layers 26a and 26c are used as a mask to remove the underlying metal layer 44 in regions other than the upper metal layers 26a and 26c by etching, as shown in FIG. 17, the upper metal layers 26a and 26c are formed under the upper metal layers 26a and 26c. Only the base metal layers 25a and 25c remain. In this state, upper wirings 24a and 24c are formed by the upper metal layers 26a and 26c and the underlying metal layers 25a and 25c remaining under the upper metal layers 26a and 26c.

次に、図１８に示すように、上層配線２４ａ、２４ｃを含む上層絶縁膜２２の上面に、スクリーン印刷法やスピンコート法等により、ソルダーレジスト等からなるオーバーコート膜２７を形成する。この場合、上層配線２４ａの上面の所定の４箇所および上層配線２４ｃの接続パッド部に対応する部分におけるオーバーコート膜２７には開口部２８ａ、２８ｃが形成されている。   Next, as shown in FIG. 18, an overcoat film 27 made of a solder resist or the like is formed on the upper surface of the upper insulating film 22 including the upper wirings 24a and 24c by screen printing or spin coating. In this case, openings 28a and 28c are formed in the overcoat film 27 at predetermined four locations on the upper surface of the upper wiring 24a and at portions corresponding to the connection pad portions of the upper wiring 24c.

次に、オーバーコート膜２７の開口部２８ａ、２８ｃ内およびその上方に半田ボール２９ａ、２９ｃを上層配線２４ａの上面の所定の４箇所および上層配線２４ｃの接続パッド部に接続させて形成する。次に、図１９に示すように、互いに隣接する半導体構成体２間における切断ライン４１に沿って、オーバーコート膜２７、上層絶縁膜２２、絶縁層２１およびベース板１を切断すると、図２に示す半導体装置が複数個得られる。   Next, solder balls 29a and 29c are formed in and above the openings 28a and 28c of the overcoat film 27 so as to be connected to predetermined four locations on the upper surface of the upper wiring 24a and connection pads of the upper wiring 24c. Next, as shown in FIG. 19, when the overcoat film 27, the upper insulating film 22, the insulating layer 21, and the base plate 1 are cut along the cutting line 41 between the adjacent semiconductor structures 2, FIG. A plurality of the semiconductor devices shown are obtained.

（第２実施形態）
図２０はこの発明の第２実施形態としての半導体装置の透過平面図を示し、図２１は図２０に示す半導体装置の適当な部分の断面図を示す。この半導体装置において、図１および図２に示す半導体装置と異なる点は、半導体構成体２において、符号１０ａ、１０ｂで示す平面方形状の電源信号用およびグランド信号用の配線の上面の周辺部以外の領域に平面方形状の柱状電極１３ａ、１３ｂを配線１０ａ、１０ｂと同様にベタ状に設けた点である。 (Second Embodiment)
20 is a transparent plan view of a semiconductor device as a second embodiment of the present invention, and FIG. 21 is a cross-sectional view of an appropriate portion of the semiconductor device shown in FIG. This semiconductor device is different from the semiconductor device shown in FIGS. 1 and 2 in the semiconductor structure 2 except for the peripheral portion on the upper surface of the wiring for the planar rectangular power signal and ground signal indicated by reference numerals 10a and 10b. This is that the planar rectangular columnar electrodes 13a and 13b are provided in a solid shape in the same manner as the wirings 10a and 10b.

この場合、上層絶縁膜２２の開口部２３ａ、２３ｂは、柱状電極１３ａ、１３ｂの上面の周辺部以外の領域に対応する部分に設けられている。そして、上層配線２４ａ、２４ｂは、上層絶縁膜２２の開口部２３ａ、２３ｂを介して、柱状電極１３ａ、１３ｂの上面の周辺部以外の領域に接続されている。   In this case, the openings 23a and 23b of the upper insulating film 22 are provided in portions corresponding to regions other than the peripheral portions on the upper surfaces of the columnar electrodes 13a and 13b. The upper layer wirings 24 a and 24 b are connected to regions other than the peripheral portion on the upper surfaces of the columnar electrodes 13 a and 13 b through the openings 23 a and 23 b of the upper layer insulating film 22.

このように、この半導体装置では、半導体構成体２の電源信号用の柱状電極１３ａおよびグランド信号用の柱状電極１３ｂをベタ状としているので、当該柱状電極１３ａ、１３ｂを低抵抗化することができ、ひいては電流容量をより一層向上させることができる。   Thus, in this semiconductor device, since the columnar electrode 13a for power supply signal and the columnar electrode 13b for ground signal of the semiconductor structure 2 are solid, the resistance of the columnar electrodes 13a and 13b can be reduced. As a result, the current capacity can be further improved.

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５ａ、５ｂ、５ｃ 接続パッド
６ パッシベーション膜
８ 保護膜
１０ａ、１０ｂ、１０ｃ 配線
１３ａ、１３ｂ、１３ｃ 柱状電極
１４ 封止膜
２１ 絶縁層
２２ 上層絶縁膜
２３ａ、２３ｂ、２３ｃ 開口部
２４ａ、２４ｂ、２４ｃ 上層配線
２７ オーバーコート膜
２９ａ、２９ｂ、２９ｃ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5a, 5b, 5c Connection pad 6 Passivation film 8 Protective film 10a, 10b, 10c Wiring 13a, 13b, 13c Columnar electrode 14 Sealing film 21 Insulating layer 22 Upper insulating film 23a, 23b, 23c Opening 24a, 24b, 24c Upper layer wiring 27 Overcoat film 29a, 29b, 29c Solder ball

Claims (24)

ベース板と、前記ベース板上に設けられ、半導体基板と、前記半導体基板上に設けられた複数の接続パッドと、前記半導体基板上に設けられた絶縁膜と、前記絶縁膜上において前記接続パッドのうち共通の信号用の複数の接続パッドを含む領域に当該接続パッドの全てに接続されるようにベタ状に設けられた共通配線と、前記絶縁膜上に残りの前記接続パッドに接続されて設けられた配線と、前記共通配線上に設けられた共通柱状電極と、前記配線の接続パッド部上に設けられた柱状電極とを有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記半導体構成体の共通柱状電極に対応する部分における前記上層絶縁膜に設けられた１つの第１の開口部と、前記半導体構成体の柱状電極に対応する部分における前記上層絶縁膜に設けられた第２の開口部と、前記上層絶縁膜上に該上層絶縁膜の第１の開口部を介して前記半導体構成体の共通柱状電極に接続されて設けられたベタ状の共通上層配線と、前記上層絶縁膜上に該上層絶縁膜の第２の開口部を介して前記半導体構成体の柱状電極に接続されて設けられた上層配線とを備えていることを特徴とする半導体装置。 A base plate; a semiconductor substrate provided on the base plate; a plurality of connection pads provided on the semiconductor substrate; an insulating film provided on the semiconductor substrate; and the connection pads on the insulating film A common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for common signals, and connected to the remaining connection pads on the insulating film A semiconductor structure having a wiring provided, a common columnar electrode provided on the common wiring, and a columnar electrode provided on a connection pad portion of the wiring; and the base plate around the semiconductor structure An insulating layer provided on the semiconductor structure, an upper insulating film provided on the insulating layer, and an upper insulating film in a portion corresponding to the common columnar electrode of the semiconductor structure; One first opening, a second opening provided in the upper insulating film in a portion corresponding to the columnar electrode of the semiconductor structure, and a first opening of the upper insulating film on the upper insulating film A solid common upper layer wiring provided connected to the common columnar electrode of the semiconductor structure via an opening, and the semiconductor structure on the upper insulating film via a second opening of the upper insulating film A semiconductor device comprising an upper wiring connected to a columnar electrode of a body. 請求項１に記載の発明において、前記半導体構成体は、前記共通柱状電極および前記柱状電極の周囲に設けられた封止膜を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor structure has a sealing film provided around the common columnar electrode and the columnar electrode. 請求項１に記載の発明において、前記半導体構成体において、前記共通配線は２つであり、そのうちの１つは電源信号用であり、他の１つはグランド信号用であることを特徴とする半導体装置。   The invention according to claim 1 is characterized in that in the semiconductor structure, there are two common wirings, one of which is for a power supply signal and the other one is for a ground signal. Semiconductor device. 請求項１に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記柱状電極と同一形状のものからなり、前記共通配線上に複数設けられていることを特徴とする半導体装置。   The semiconductor device according to claim 1, wherein the common columnar electrode has the same shape as the columnar electrode, and a plurality of the common columnar electrodes are provided on the common wiring. 請求項４に記載の発明において、前記共通柱状電極の数は前記共通の信号用の接続パッドの数と同一であることを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein the number of the common columnar electrodes is the same as the number of the common signal connection pads. 請求項４または５に記載の発明において、前記共通上層配線は前記上層絶縁膜の第１の開口部を介して前記共通柱状電極の全てに接続されていることを特徴とする半導体装置。   6. The semiconductor device according to claim 4, wherein the common upper layer wiring is connected to all of the common columnar electrodes through the first opening of the upper layer insulating film. 請求項１に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記共通配線上に該共通配線と同様にベタ状に設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein in the semiconductor structure, the common columnar electrode is provided in a solid shape on the common wiring in the same manner as the common wiring. 請求項５に記載の発明において、前記上層絶縁膜の第１の開口部の平面形状は、前記半導体構成体のベタ状の共通柱状電極の平面形状に応じて、前記上層絶縁膜の第２の開口部の平面形状よりも大きくなっていることを特徴とする半導体装置。   In the invention according to claim 5, the planar shape of the first opening of the upper insulating film is the second shape of the upper insulating film according to the planar shape of the solid common columnar electrode of the semiconductor structure. A semiconductor device characterized by being larger than the planar shape of the opening. 請求項１に記載の発明において、前記共通上層配線および前記上層配線の上面は面一となっていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein upper surfaces of the common upper layer wiring and the upper layer wiring are flush with each other. 請求項１に記載の発明において、前記共通上層配線の複数の箇所および前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, further comprising an overcoat film that covers a plurality of portions of the common upper layer wiring and portions other than the connection pads of the upper layer wiring. 請求項１０に記載の発明において、前記共通上層配線の複数の箇所上および前記上層配線の接続パッド上に半田ボールが設けられていることを特徴とする半導体装置。   11. The semiconductor device according to claim 10, wherein solder balls are provided on a plurality of portions of the common upper layer wiring and on connection pads of the upper layer wiring. 請求項１１に記載の発明において、前記共通上層配線の複数の箇所上に設けられた前記半田ボールの数は前記共通の信号用の接続パッドの数と同一であることを特徴とする半導体装置。   12. The semiconductor device according to claim 11, wherein the number of the solder balls provided on a plurality of locations of the common upper layer wiring is the same as the number of the common signal connection pads. ベース板上に、各々が、半導体基板と、前記半導体基板上に設けられた複数の接続パッドと、前記半導体基板上に設けられた絶縁膜と、前記絶縁膜上において前記接続パッドのうち共通の信号用の複数の接続パッドを含む領域に当該接続パッドの全てに接続されるようにベタ状に設けられた共通配線と、前記絶縁膜上に残りの前記接続パッドに接続されて設けられた配線と、前記共通配線上に設けられた共通柱状電極と、前記配線の接続パッド部上に設けられた柱状電極とを有する複数の半導体構成体を相互に離間させて配置する工程と、
前記半導体構成体の周囲における前記ベース板上に絶縁層を形成し、且つ、前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、
前記半導体構成体の共通柱状電極に対応する部分における前記上層絶縁膜に１つの第１の開口部を形成し、且つ、前記半導体構成体の柱状電極に対応する部分における前記上層絶縁膜に第２の開口部を形成する工程と、
前記上層絶縁膜上にベタ状の共通上層配線を前記上層絶縁膜の第１の開口部を介して前記半導体構成体の共通柱状電極に接続させて形成し、且つ、前記上層絶縁膜上に上層配線を前記上層絶縁膜の第２の開口部を介して前記半導体構成体の柱状電極に接続させて形成する工程と、
前記半導体構成体間における前記上層絶縁膜、前記絶縁層および前記ベース板を切断して半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 On the base plate, each of the semiconductor substrate, a plurality of connection pads provided on the semiconductor substrate, an insulating film provided on the semiconductor substrate, and a common of the connection pads on the insulating film Common wiring provided in a solid shape so as to be connected to all of the connection pads in a region including a plurality of connection pads for signals, and wiring provided to be connected to the remaining connection pads on the insulating film And a step of disposing a plurality of semiconductor structures having a common columnar electrode provided on the common wiring and a columnar electrode provided on a connection pad portion of the wiring apart from each other;
Forming an insulating layer on the base plate around the semiconductor structure, and forming an upper insulating film on the semiconductor structure and the insulating layer;
A first opening is formed in the upper insulating film in a portion corresponding to the common columnar electrode of the semiconductor structure, and a second opening is formed in the upper insulating film in a portion corresponding to the columnar electrode of the semiconductor structure. Forming an opening of
A solid common upper layer wiring is formed on the upper insulating film so as to be connected to the common columnar electrode of the semiconductor structure through the first opening of the upper insulating film, and the upper layer is formed on the upper insulating film. Forming a wiring by connecting to a columnar electrode of the semiconductor structure through a second opening of the upper insulating film;
Cutting the upper insulating film, the insulating layer, and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 請求項１３に記載の発明において、前記半導体構成体は、前記共通柱状電極および前記柱状電極の周囲に設けられた封止膜を有することを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor structure includes a common columnar electrode and a sealing film provided around the columnar electrode. 請求項１３に記載の発明において、前記半導体構成体において、前記共通配線は２つであり、そのうちの１つは電源信号用であり、他の１つはグランド信号用であることを特徴とする半導体装置の製造方法。   14. The semiconductor device according to claim 13, wherein in the semiconductor structure, there are two common wires, one of which is for a power supply signal and the other one is for a ground signal. A method for manufacturing a semiconductor device. 請求項１３に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記柱状電極と同一形状のものからなり、前記共通配線上に複数設けられていることを特徴とする半導体装置の製造方法。   14. The semiconductor device according to claim 13, wherein the common columnar electrode has the same shape as the columnar electrode, and a plurality of the common columnar electrodes are provided on the common wiring. Method. 請求項１６に記載の発明において、前記共通柱状電極の数は前記共通の信号用の接続パッドの数と同一であることを特徴とする半導体装置の製造方法。   17. The method of manufacturing a semiconductor device according to claim 16, wherein the number of the common columnar electrodes is the same as the number of the common signal connection pads. 請求項１６または１７に記載の発明において、前記共通上層配線は前記上層絶縁膜の第１の開口部を介して前記共通柱状電極の全てに接続されるように形成することを特徴とする半導体装置の製造方法。   18. The semiconductor device according to claim 16, wherein the common upper layer wiring is formed so as to be connected to all of the common columnar electrodes through the first opening of the upper layer insulating film. Manufacturing method. 請求項１３に記載の発明において、前記半導体構成体において、前記共通柱状電極は前記共通配線上に該共通配線と同様にベタ状に設けられていることを特徴とする半導体装置。   14. The semiconductor device according to claim 13, wherein in the semiconductor structure, the common columnar electrode is provided in a solid shape on the common wiring in the same manner as the common wiring. 請求項１９に記載の発明において、前記上層絶縁膜の第１の開口部は、その平面形状が、前記半導体構成体のベタ状の共通柱状電極の平面形状に応じて、前記上層絶縁膜の第２の開口部の平面形状よりも大きくなるように形成することを特徴とする半導体装置。   20. The first opening of the upper insulating film according to claim 19, wherein the planar shape of the first opening of the upper insulating film depends on the planar shape of the solid common columnar electrode of the semiconductor structure. A semiconductor device formed so as to be larger than a planar shape of the two openings. 請求項１３に記載の発明において、前記共通上層配線および前記上層配線を形成する工程は、前記上層絶縁膜の第１、第２の開口部内を含む前記上層絶縁膜上の全体に下地金属層を形成する工程と、前記下地金属層上に電解メッキにより共通上層配線用上部金属層および上層配線用上部金属層を形成する工程と、前記共通上層配線用上部金属層および前記上層配線用上部金属層の上面側を研削して前記共通上層配線用上部金属層および前記上層配線用上部金属層の上面を面一とする工程と、前記共通上層配線用上部金属層および前記上層配線用上部金属層下以外の領域における前記下地金属層を除去する工程とを含むことを特徴とする半導体装置。   14. The method according to claim 13, wherein the step of forming the common upper layer wiring and the upper layer wiring includes forming a base metal layer on the entire upper insulating film including the first and second openings of the upper insulating film. Forming the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring by electrolytic plating on the base metal layer, and the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring. The upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring are flush with each other, and the upper metal layer for common upper layer wiring and the upper metal layer for upper layer wiring are below And a step of removing the base metal layer in a region other than the region. 請求項１３に記載の発明において、前記共通上層配線の複数の箇所および前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を形成する工程を有することを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, further comprising a step of forming an overcoat film that covers a plurality of portions of the common upper layer wiring and portions other than the connection pads of the upper layer wiring. 請求項２２に記載の発明において、前記共通上層配線の複数の箇所上および前記上層配線の接続パッド上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。   23. The method of manufacturing a semiconductor device according to claim 22, further comprising a step of forming solder balls on a plurality of portions of the common upper layer wiring and on connection pads of the upper layer wiring. 請求項２３に記載の発明において、前記共通上層配線の複数の箇所上に形成される前記半田ボールの数は前記共通の信号用の接続パッドの数と同一であることを特徴とする半導体装置の製造方法。   24. The semiconductor device according to claim 23, wherein the number of solder balls formed on a plurality of locations of the common upper layer wiring is the same as the number of common signal connection pads. Production method.
JP2009158622A 2009-07-03 2009-07-03 Semiconductor device, and method of manufacturing the same Pending JP2011014764A (en)

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