JP2008544528A5 - - Google Patents

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Publication number
JP2008544528A5
JP2008544528A5 JP2008517112A JP2008517112A JP2008544528A5 JP 2008544528 A5 JP2008544528 A5 JP 2008544528A5 JP 2008517112 A JP2008517112 A JP 2008517112A JP 2008517112 A JP2008517112 A JP 2008517112A JP 2008544528 A5 JP2008544528 A5 JP 2008544528A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008517112A
Other versions
JP2008544528A (ja
JP5253158B2 (ja
Filing date
Publication date
Priority claimed from US11/329,576 external-priority patent/US7989958B2/en
Priority claimed from US11/329,556 external-priority patent/US7767493B2/en
Application filed filed Critical
Priority claimed from PCT/US2006/023364 external-priority patent/WO2006138492A2/en
Publication of JP2008544528A publication Critical patent/JP2008544528A/ja
Publication of JP2008544528A5 publication Critical patent/JP2008544528A5/ja
Application granted granted Critical
Publication of JP5253158B2 publication Critical patent/JP5253158B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008517112A 2005-06-14 2006-06-14 ポストおよびペネトレーション相互接続 Expired - Fee Related JP5253158B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US69075905P 2005-06-14 2005-06-14
US60/690,759 2005-06-14
US11/329,576 US7989958B2 (en) 2005-06-14 2006-01-10 Patterned contact
US11/329,576 2006-01-10
US11/329,481 2006-01-10
US11/329,556 2006-01-10
US11/329,481 US8154131B2 (en) 2005-06-14 2006-01-10 Profiled contact
US11/329,556 US7767493B2 (en) 2005-06-14 2006-01-10 Post & penetration interconnection
PCT/US2006/023364 WO2006138492A2 (en) 2005-06-14 2006-06-14 Post & penetration interconnection

Publications (3)

Publication Number Publication Date
JP2008544528A JP2008544528A (ja) 2008-12-04
JP2008544528A5 true JP2008544528A5 (ja) 2009-07-30
JP5253158B2 JP5253158B2 (ja) 2013-07-31

Family

ID=37571183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008517112A Expired - Fee Related JP5253158B2 (ja) 2005-06-14 2006-06-14 ポストおよびペネトレーション相互接続

Country Status (3)

Country Link
JP (1) JP5253158B2 (ja)
KR (1) KR101419548B1 (ja)
WO (1) WO2006138492A2 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7850060B2 (en) 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US7748116B2 (en) 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US8258625B2 (en) * 2007-04-06 2012-09-04 Hitachi, Ltd. Semiconductor device
KR100975652B1 (ko) * 2007-10-05 2010-08-17 한국과학기술원 아연 및 아연합금을 이용한 비아 및 그의 형성 방법, 그를3차원 다중 칩 스택 패키지 제조 방법
CN103050420A (zh) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
KR102544296B1 (ko) * 2018-09-13 2023-06-16 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 표면발광레이저 소자 및 이를 구비한 표면발광레이저 장치

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0516866A1 (en) * 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
US5234153A (en) * 1992-08-28 1993-08-10 At&T Bell Laboratories Permanent metallic bonding method
JP3348528B2 (ja) * 1994-07-20 2002-11-20 富士通株式会社 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US7052941B2 (en) * 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
JPH10270498A (ja) * 1997-03-27 1998-10-09 Toshiba Corp 電子装置の製造方法
JP2000114206A (ja) * 1998-10-05 2000-04-21 Sony Corp 半導体パッケージの製造方法
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
JP3386029B2 (ja) * 2000-02-09 2003-03-10 日本電気株式会社 フリップチップ型半導体装置及びその製造方法
JP2001338947A (ja) * 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
JP3723453B2 (ja) * 2000-09-12 2005-12-07 ローム株式会社 半導体装置
JP2002134545A (ja) 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd 半導体集積回路チップ及び基板、並びにその製造方法
JP3832334B2 (ja) * 2000-12-28 2006-10-11 松下電工株式会社 半導体チップ実装基板およびその製造方法
US6512300B2 (en) * 2001-01-10 2003-01-28 Raytheon Company Water level interconnection
US6939789B2 (en) * 2002-05-13 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer level chip scale packaging
SG111972A1 (en) * 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7230318B2 (en) * 2003-12-24 2007-06-12 Agency For Science, Technology And Research RF and MMIC stackable micro-modules

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