JP2008541460A5 - - Google Patents

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Publication number
JP2008541460A5
JP2008541460A5 JP2008511413A JP2008511413A JP2008541460A5 JP 2008541460 A5 JP2008541460 A5 JP 2008541460A5 JP 2008511413 A JP2008511413 A JP 2008511413A JP 2008511413 A JP2008511413 A JP 2008511413A JP 2008541460 A5 JP2008541460 A5 JP 2008541460A5
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JP
Japan
Prior art keywords
semiconductor chip
package assembly
chip package
polyimide
assembly according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008511413A
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English (en)
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JP2008541460A (ja
JP4563483B2 (ja
Filing date
Publication date
Priority claimed from US10/908,480 external-priority patent/US7199450B2/en
Application filed filed Critical
Publication of JP2008541460A publication Critical patent/JP2008541460A/ja
Publication of JP2008541460A5 publication Critical patent/JP2008541460A5/ja
Application granted granted Critical
Publication of JP4563483B2 publication Critical patent/JP4563483B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (7)

  1. シリコン基板と、
    少なくとも1つの半導体チップと、
    少なくとも1つの露出端部とその中に充填された多孔質材料とを有する、前記シリコン基板内の少なくとも1つの電気伝導性ビアと、
    リフローされて前記少なくとも1つの電気伝導性ビアの前記多孔質材料内へ浸入し、前記多孔質材料を封止する、高分子材料を含むシーラントと、
    を含む、半導体チップ・パッケージ組立体。
  2. 前記高分子材料が、ポリイミド材料又は高い熱安定性の熱硬化性材料を含む、請求項に記載の半導体チップ・パッケージ組立体。
  3. 前記高分子材料が、ポリイミド前駆体溶液を含む、請求項に記載の半導体チップ・パッケージ組立体。
  4. 前記ポリイミド前駆体溶液が、高濃度の固形分を含み、1cPから150cPまでの粘度を有する、請求項に記載の半導体チップ・パッケージ組立体。
  5. 前記ポリイミド材料が、その前駆体状態において低粘度及び低融点のニートな熱硬化性材料である、請求項に記載の半導体チップ・パッケージ組立体。
  6. 前記熱安定性の熱硬化性材料が、Matrimid(登録商標)、PMDA−ODA、BPDA−PDA、又はPI2562を含む、請求項に記載の半導体チップ・パッケージ組立体。
  7. 前記シーラントが堆積された銅被覆を含む、請求項1に記載の半導体チップ・パッケージ組立体。
JP2008511413A 2005-05-13 2006-05-12 半導体チップ・パッケージ組立体 Expired - Fee Related JP4563483B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/908,480 US7199450B2 (en) 2005-05-13 2005-05-13 Materials and method to seal vias in silicon substrates
PCT/US2006/018458 WO2006124607A2 (en) 2005-05-13 2006-05-12 Materials and method to seal vias in silicon substrates

Publications (3)

Publication Number Publication Date
JP2008541460A JP2008541460A (ja) 2008-11-20
JP2008541460A5 true JP2008541460A5 (ja) 2009-07-23
JP4563483B2 JP4563483B2 (ja) 2010-10-13

Family

ID=37418363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008511413A Expired - Fee Related JP4563483B2 (ja) 2005-05-13 2006-05-12 半導体チップ・パッケージ組立体

Country Status (6)

Country Link
US (1) US7199450B2 (ja)
EP (1) EP1883961A4 (ja)
JP (1) JP4563483B2 (ja)
CN (1) CN101176203B (ja)
TW (1) TWI406365B (ja)
WO (1) WO2006124607A2 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090083977A1 (en) * 2007-09-28 2009-04-02 Andre Hanke Method for Filling Via Holes in Semiconductor Substrates
US9666514B2 (en) 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
CN110402616B (zh) 2016-11-18 2023-04-04 申泰公司 填充材料以及基板通孔的填充方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126758A (en) * 1973-12-03 1978-11-21 Raychem Corporation Method for sealing integrated circuit components with heat recoverable cap and resulting package
US4880684A (en) * 1988-03-11 1989-11-14 International Business Machines Corporation Sealing and stress relief layers and use thereof
US5139851A (en) * 1988-03-11 1992-08-18 International Business Machines Corporation Low dielectric composite substrate
JPH02106956A (ja) * 1988-10-17 1990-04-19 Hitachi Ltd 半導体装置及びその製造方法
JPH05198697A (ja) * 1992-01-20 1993-08-06 Fujitsu Ltd シリコン基板金属ビア形成方法およびマルチチップモジュール製造方法
US5904502A (en) * 1997-09-04 1999-05-18 International Business Machines Corporation Multiple 3-dimensional semiconductor device processing method and apparatus
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6100114A (en) * 1998-08-10 2000-08-08 International Business Machines Corporation Encapsulation of solder bumps and solder connections
US6555762B2 (en) * 1999-07-01 2003-04-29 International Business Machines Corporation Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition
JP4576728B2 (ja) * 2001-03-06 2010-11-10 ソニー株式会社 導電性ぺースト、プリント配線基板とその製造方法および半導体装置とその製造方法
US6593644B2 (en) 2001-04-19 2003-07-15 International Business Machines Corporation System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face
JP3993458B2 (ja) * 2002-04-17 2007-10-17 株式会社東芝 半導体装置

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