JP2008536334A - 改善されたセル安定性及び性能のためのハイブリッド・バルク−ｓｏｉ６ｔ−ｓｒａｍセル - Google Patents

改善されたセル安定性及び性能のためのハイブリッド・バルク−ｓｏｉ６ｔ−ｓｒａｍセル Download PDF

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Publication number
JP2008536334A
JP2008536334A JP2008506486A JP2008506486A JP2008536334A JP 2008536334 A JP2008536334 A JP 2008536334A JP 2008506486 A JP2008506486 A JP 2008506486A JP 2008506486 A JP2008506486 A JP 2008506486A JP 2008536334 A JP2008536334 A JP 2008536334A
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Japan
Prior art keywords
region
bulk
soi
sram cell
semiconductor structure
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JP2008506486A
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Japanese (ja)
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JP2008536334A5 (enExample
Inventor
チャン、リーランド
ナラシンハ、シュリーシュ
ローラー、ノーマン、ジェイ
スライト、ジェフリー、ダブリュー
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International Business Machines Corp
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International Business Machines Corp
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Publication of JP2008536334A publication Critical patent/JP2008536334A/ja
Publication of JP2008536334A5 publication Critical patent/JP2008536334A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP2008506486A 2005-04-15 2006-03-27 改善されたセル安定性及び性能のためのハイブリッド・バルク−ｓｏｉ６ｔ−ｓｒａｍセル Pending JP2008536334A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/108,012 US7274072B2 (en) 2005-04-15 2005-04-15 Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance
PCT/US2006/011167 WO2006113061A2 (en) 2005-04-15 2006-03-27 A hybrid bulk-soi 6t-sram cell for improved cell stability and performance

Publications (2)

Publication Number Publication Date
JP2008536334A true JP2008536334A (ja) 2008-09-04
JP2008536334A5 JP2008536334A5 (enExample) 2009-08-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008506486A Pending JP2008536334A (ja) 2005-04-15 2006-03-27 改善されたセル安定性及び性能のためのハイブリッド・バルク−ｓｏｉ６ｔ−ｓｒａｍセル

Country Status (6)

Country Link
US (1) US7274072B2 (enExample)
EP (1) EP1875516A4 (enExample)
JP (1) JP2008536334A (enExample)
CN (1) CN101160667B (enExample)
TW (1) TW200723548A (enExample)
WO (1) WO2006113061A2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234793A (ja) * 2006-02-28 2007-09-13 Seiko Epson Corp 半導体装置及びその製造方法
JP2014236097A (ja) * 2013-05-31 2014-12-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2015111674A (ja) * 2010-01-28 2015-06-18 レイセオン カンパニー 共通基板上にカラムｉｉｉ−ｖトランジスタとともにシリコンｃｍｏｓトランジスタを有する半導体構造

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KR100539243B1 (ko) * 2003-10-04 2005-12-27 삼성전자주식회사 부분 에스오아이 기판에 구현된 에스램 소자
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
JP2007158295A (ja) * 2005-11-10 2007-06-21 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP2007251005A (ja) * 2006-03-17 2007-09-27 Toshiba Corp 半導体装置及びその製造方法
DE102006015076B4 (de) * 2006-03-31 2014-03-20 Advanced Micro Devices, Inc. Halbleiterbauelement mit SOI-Transistoren und Vollsubstrattransistoren und ein Verfahren zur Herstellung
US20090026524A1 (en) * 2007-07-27 2009-01-29 Franz Kreupl Stacked Circuits
US7948008B2 (en) * 2007-10-26 2011-05-24 Micron Technology, Inc. Floating body field-effect transistors, and methods of forming floating body field-effect transistors
US7718496B2 (en) 2007-10-30 2010-05-18 International Business Machines Corporation Techniques for enabling multiple Vt devices using high-K metal gate stacks
US7985633B2 (en) * 2007-10-30 2011-07-26 International Business Machines Corporation Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
US20090200635A1 (en) * 2008-02-12 2009-08-13 Viktor Koldiaev Integrated Circuit Having Electrical Isolation Regions, Mask Technology and Method of Manufacturing Same
US20100200918A1 (en) * 2009-02-10 2010-08-12 Honeywell International Inc. Heavy Ion Upset Hardened Floating Body SRAM Cells
US8294485B2 (en) 2009-02-12 2012-10-23 International Business Machines Corporation Detecting asymmetrical transistor leakage defects
US8324665B2 (en) * 2009-04-21 2012-12-04 Texas Instruments Incorporated SRAM cell with different crystal orientation than associated logic
US8080456B2 (en) * 2009-05-20 2011-12-20 International Business Machines Corporation Robust top-down silicon nanowire structure using a conformal nitride
US8018007B2 (en) * 2009-07-20 2011-09-13 International Business Machines Corporation Selective floating body SRAM cell
US8426917B2 (en) * 2010-01-07 2013-04-23 International Business Machines Corporation Body-tied asymmetric P-type field effect transistor
US8643107B2 (en) * 2010-01-07 2014-02-04 International Business Machines Corporation Body-tied asymmetric N-type field effect transistor
US8299519B2 (en) * 2010-01-11 2012-10-30 International Business Machines Corporation Read transistor for single poly non-volatile memory using body contacted SOI device
US8372725B2 (en) * 2010-02-23 2013-02-12 International Business Machines Corporation Structures and methods of forming pre fabricated deep trench capacitors for SOI substrates
CN103295951A (zh) * 2012-02-27 2013-09-11 中国科学院上海微系统与信息技术研究所 基于混合晶向soi的器件系统结构及制备方法
US8822295B2 (en) * 2012-04-03 2014-09-02 International Business Machines Corporation Low extension dose implants in SRAM fabrication
US9041105B2 (en) 2012-07-20 2015-05-26 International Business Machines Corporation Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
CN103579191B (zh) * 2012-07-20 2016-06-15 无锡华润上华半导体有限公司 用于测试六管sram的漏电流的半导体测试结构
US8963208B2 (en) * 2012-11-15 2015-02-24 GlobalFoundries, Inc. Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
US10109638B1 (en) * 2017-10-23 2018-10-23 Globalfoundries Singapore Pte. Ltd. Embedded non-volatile memory (NVM) on fully depleted silicon-on-insulator (FD-SOI) substrate
US11749671B2 (en) * 2020-10-09 2023-09-05 Globalfoundries U.S. Inc. Integrated circuit structures with well boundary distal to substrate midpoint and methods to form the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03129777A (ja) * 1989-07-13 1991-06-03 Mitsubishi Electric Corp 電界効果型トランジスタを備えた半導体装置およびその製造方法
JPH07193188A (ja) * 1993-11-22 1995-07-28 Semiconductor Energy Lab Co Ltd 半導体集積回路
JP2001352077A (ja) * 2000-04-12 2001-12-21 Internatl Business Mach Corp <Ibm> Ｓｏｉ電界効果トランジスタ
JP2004079705A (ja) * 2002-08-14 2004-03-11 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP2004303340A (ja) * 2003-03-31 2004-10-28 Renesas Technology Corp 半導体記憶装置

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WO2000048245A1 (en) * 1999-02-12 2000-08-17 Ibis Technology Corporation Patterned silicon-on-insulator devices
JP4850387B2 (ja) * 2002-12-09 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
KR100539243B1 (ko) * 2003-10-04 2005-12-27 삼성전자주식회사 부분 에스오아이 기판에 구현된 에스램 소자

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03129777A (ja) * 1989-07-13 1991-06-03 Mitsubishi Electric Corp 電界効果型トランジスタを備えた半導体装置およびその製造方法
JPH07193188A (ja) * 1993-11-22 1995-07-28 Semiconductor Energy Lab Co Ltd 半導体集積回路
JP2001352077A (ja) * 2000-04-12 2001-12-21 Internatl Business Mach Corp <Ibm> Ｓｏｉ電界効果トランジスタ
JP2004079705A (ja) * 2002-08-14 2004-03-11 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP2004303340A (ja) * 2003-03-31 2004-10-28 Renesas Technology Corp 半導体記憶装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
M. YANG, ET AL.: ""High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations"", IEDM, JPN5008004106, December 2003 (2003-12-01), US, pages 453 - 456, XP010684050, ISSN: 0001365797 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234793A (ja) * 2006-02-28 2007-09-13 Seiko Epson Corp 半導体装置及びその製造方法
JP2015111674A (ja) * 2010-01-28 2015-06-18 レイセオン カンパニー 共通基板上にカラムｉｉｉ−ｖトランジスタとともにシリコンｃｍｏｓトランジスタを有する半導体構造
JP2014236097A (ja) * 2013-05-31 2014-12-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP1875516A4 (en) 2008-08-13
CN101160667A (zh) 2008-04-09
CN101160667B (zh) 2010-06-16
TW200723548A (en) 2007-06-16
US20060231899A1 (en) 2006-10-19
WO2006113061A2 (en) 2006-10-26
US7274072B2 (en) 2007-09-25
WO2006113061A3 (en) 2007-05-24
EP1875516A2 (en) 2008-01-09

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