JP2008524836A - 小型マイクロ波パッケージ及び該パッケージの製造方法 - Google Patents
小型マイクロ波パッケージ及び該パッケージの製造方法 Download PDFInfo
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- JP2008524836A JP2008524836A JP2007546022A JP2007546022A JP2008524836A JP 2008524836 A JP2008524836 A JP 2008524836A JP 2007546022 A JP2007546022 A JP 2007546022A JP 2007546022 A JP2007546022 A JP 2007546022A JP 2008524836 A JP2008524836 A JP 2008524836A
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002470 thermal conductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 238000010923 batch production Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003847 radiation curing Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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Abstract
用途:小型マイクロ波パッケージ
【選択図】図5
Description
− 既存のパッケージのフットプリント(およそ20mm2)。
− 特に高速(特にマイクロ波)のロジック及びアナログ用途における電気的な性能の低下。この問題の原因は、相互接続(ボンディングワイヤやトランジション線路(transition line)等)の長さ、及び従来技術のパッケージの寸法と関連付けられた寄生要素にある。特に、これらのパッケージの、結果として発生する寄生インダクタンスは、カプセル化された回路のゲイン、安定性、及び動作周波数を制限する。
− 従来技術の特定のパッケージソリューションの表面実装手法との非互換性。
− パッケージ化された部品をテストするための生産設備(試験治具、ハンドラ等)の必要性。
− アクティブ部品(トランジスタ)及びパッシブ部品の寄生容量を増やす結果となる誘電体の使用に起因して、特にマイクロ波用途の場合に性能が大幅に低下する。
− 特に高速ロジック及びアナログ用途において電気性能が低下する。この性能低下はボンディングワイヤの長さに起因するものである。
− 一組の集積回路139であって、該集積回路の各々は、アクティブ素子144と電気伝導体146とを含むアクティブ面140と、電気伝導体148を含む、該アクティブ面の反対側に位置する背面142と、チップ内に、アクティブ面の電気伝導体146と背面の電気伝導体148とを接続するメッキスルーホール150とを有する集積回路を、ガリウム砒素、窒化ガリウム、又はリン化インジウムでできた単結晶又はウェーハ上に、例えば公知の技術を使用して、製造するステップ(図10aを参照)、
− エッチングされたシリコンウェーハから、
a)保護すべき前記チップの前記アクティブ面と一緒にしてキャビティを形成するための凹部154と、
b)蓋で覆われた集積回路を分離するために、蓋の間に形成されたダイシングパス156と
を有する蓋ウェーハ152を製造するステップ(図10bを参照)、
− 凹部154の縁158に接着要素を局部的に堆積させるステップ、
− 蓋ウェーハ152を、その凹部154の縁158を介して、集積回路ウェーハ(図10a)上の集積回路のアクティブ面140にウェーハボンディングによって実装し、カプセル化された集積回路ウェーハ160を形成するステップ(図10cを参照)、
− ダイシングパス156が集積回路ウェーハの集積回路を保護するための蓋を分離するまで、蓋ウェーハ152側から、カプセル化された集積回路ウェーハ160を薄くしていくステップ(図10dを参照)、
− それぞれ蓋176、178、180によって保護された集積回路を有するパッケージ170、172、174を分離するために、カプセル化された集積回路ウェーハ160をダイシングするステップ(図10eを参照)。
− 仮基板190上に一連の電気コンタクト192(又はリードフレーム)を成長させるとともに、該電気コンタクト192上にはんだバンプ194を成長させるステップ(図11aを参照)、
− 蓋176によって保護された集積回路を有するパッケージ170を集積回路の背面142を介して、一連の電気コンタクト192にはんだバンプ194によって実装するステップ(図11bを参照)、
− 蓋によって保護された集積回路と仮基板190上の一連の電気コンタクト192とをモールディング196にて封止するステップ(図11cを参照)、
− 仮基板190を、リードフレームの電気コンタクト192まで薄くするステップ(図11dを参照)、
− 蓋によって保護された集積回路を有するモールド済パッケージ200をダイシング及び分離するステップ(図11eを参照)。
− サーマルパスを短くすることによる、熱問題の著しい改善。
− 製造方法に必要な一括処理を従来技術に比べて大幅に簡素化。
− 相互接続を非常に短くしたことによる、高速ロジック及びアナログ用途での電気性能の大幅向上。
− 部品の表面実装を必要し、さらにボンディングワイヤの使用を回避する生産技術との互換性。
− 蓋とチップのアクティブ面との間の空気キャビティの縮小化による、寄生容量の増大防止、及び後続のカプセル化又はパッケージ化作業から回路が受ける影響の緩和。さらに、このキャビティの高次モードの遮断周波数は、使用可能な周波数の完全に外にある(他の実施形態では、矩形の導波管又はフィルタを製作するためにキャビティの高さを選択できる)。
− 寸法の非常に小さな空気キャビティを製造することにより、MEMS(マイクロマシン:microelectromechanical system)部品の機械要素を移動及び機能させること。
− 光窓、ダイシングパス、集積アンテナ用のバックショートを製造するためにキャビティの高さを適合させることが可能。
− プローブ生産試験方法との互換性。
− 現在の集積回路の製造方法との互換性。
− 好適な放射硬化を提供する保護。
Claims (11)
- アクティブ面(12、42、62、140)を備えたマイクロ波チップ(10、40、60)を有する小型マイクロ波パッケージであって、
前記チップが前記アクティブ面に固定され前記チップを少なくとも部分的に覆う保護蓋(72、176、178、180)を含み、前記蓋が前記チップの前記アクティブ面と一緒になってキャビティ(80、94、96、98)を形成する少なくとも1つの凹部(154)を含むことを特徴とする、小型マイクロ波パッケージ。 - 前記蓋が前記チップの前記アクティブ面全面を覆うことを特徴とする、請求項1に記載の小型マイクロ波パッケージ。
- 前記蓋が複数の凹部を含み、前記凹部の各々が前記チップの前記アクティブ面と一緒になってキャビティ(80、94、96、98)を形成することを特徴とする、請求項1又は2に記載の小型マイクロ波パッケージ。
- 前記チップ(60)の前記アクティブ面(62)が電気伝導体(64)とアクティブマイクロ波部品(65)とを前記アクティブ面に含み、
前記チップが電気伝導体(68)を含む背面(66)を前記アクティブ面の反対側に有し、
集積回路のための前記保護蓋(72)が前記チップの前記アクティブ面(62)と平行な上部プレート(74)を有し、
前記上部プレート(74)が該上部プレートに対して垂直な壁(76)によって延長され、前記チップと一緒になって、前記蓋の前記上部プレート(74)と前記アクティブ面との間に位置するキャビティ(80)を形成するように前記チップの前記アクティブ面(62)と接触した端部(78)で終端していることを特徴とする、請求項1〜3のいずれか一項に記載の小型マイクロ波パッケージ。 - 前記蓋(72)が該蓋の前記上部プレート(74)に対して垂直な他の壁(90、92)を有し、前記チップの前記アクティブ面(62)と一緒になって、他の複数のキャビティ(94、96、98)を形成することを特徴とする、請求項4に記載の小型マイクロ波パッケージ。
- 前記チップの前記アクティブ面に面する側にある、前記蓋の凹部はエッチング又はモールディングによって製造することができ、この凹部が前記アクティブ面と一緒になって前記キャビティ(80、94、96、98)を形成することを特徴とする、請求項3〜5のいずれか一項に記載の小型マイクロ波パッケージ。
- 前記蓋が、前記チップの前記アクティブ面(62)に面している、前記プレート(72)の面(84)側に電気伝導体及び熱伝導体(110)を含み、該電気伝導体及び熱伝導体が前記アクティブ面の電気伝導体(112)と接触していることを特徴とする、請求項5又は6に記載の小型マイクロ波パッケージ。
- アクティブ面(130)を備えた集積回路(60)を有する小型マイクロ波パッケージであって、前記アクティブ面が電気伝導体(132)を有し、前記アクティブ面上のこれらの伝導体の中でも、前記チップを外部回路に電気的に接続するための電気接続部(134)を有し、
前記チップを保護するための蓋(136)が、前記チップの前記アクティブ面の面積より狭く、前記チップを部分的にしか覆わないことにより、前記チップの前記電気的接続部(134)を露出させていることを特徴とする、請求項4〜7のいずれか一項に記載の小型マイクロ波パッケージ。 - 前記蓋が好ましくは、シリコン、プラスチック、ダイヤモンド、ガラス、有機又は高分子材料、金属の中から選択した材料で製造されることを特徴とする、請求項1〜8のいずれか一項に記載の小型マイクロ波パッケージ。
- 請求項1〜9のいずれか一項に記載の蓋によって保護されたマイクロ波チップを有する小型マイクロ波パッケージを一括製造するための方法であって、該方法が少なくとも、
− 一組の集積回路(139)であって、該集積回路の各々が、アクティブ要素(144)と電気伝導体(146)とを含むアクティブ面(140)と、電気伝導体(148)を含む、前記アクティブ面の反対側に位置する背面(142)と、前記チップ内に前記アクティブ面の前記電気伝導体(146)と前記背面の前記電気伝導体(148)とを接続するメッキスルーホール(150)とを有する集積回路を、ガリウム砒素、窒化ガリウム、又はリン化インジウムでできた単結晶又はウェーハに、例えば公知の技術を使用して製造するステップと、
− エッチングされたシリコンウェーハから
a)保護すべき前記チップの前記アクティブ面と一緒にキャビティを形成するための凹部(154)と、
b)前記蓋で覆われた集積回路を分離するために、前記蓋の間にダイシングパス(156)と
を有する蓋ウェーハ(152)を製造するステップと、
− 前記凹部(154)の縁(158)に接着要素を局部的に堆積させるステップと、
− 前記蓋ウェーハ(152)を、前記凹部(154)の前記縁(158)を介して、前記集積回路ウェーハ上の前記集積回路の前記アクティブ面(140)にウェーハボンディングによって実装し、カプセル化された集積回路ウェーハ(160)を構成するステップと、
− 前記ダイシングパス(156)が前記集積回路ウェーハの前記集積回路を保護するための前記蓋を分離するまで、前記蓋ウェーハ(152)側から、前記カプセル化された集積回路ウェーハ(160)を薄くしていくステップと、
− それぞれ蓋(176、178、180)によって保護された前記集積回路を有する前記パッケージ(170、172、174)を分離するために、前記カプセル化された集積回路ウェーハ(160)をダイシングするステップと、を含むことを特徴とする方法。 - 請求項1〜9のいずれか一項に記載の蓋によって保護された集積回路をカプセル化するための方法であって、該方法が少なくとも、
− 仮基板(190)上に一連の電気コンタクト(192)(又はリードフレーム)を成長させるとともに前記電気コンタクト(192)上にはんだバンプ(194)を成長させるステップと、
− 前記蓋(176)によって保護された集積回路を有する前記パッケージ(170)を、前記集積回路の背面(142)を介して前記一連の電気コンタクト(192)に前記はんだバンプ(194)によって実装するステップと、
− 前記蓋によって保護された前記集積回路と前記仮基板(190)上の前記一連の電気コンタクト(192)とをモールディング(196)するステップと、
− 前記仮基板(190)を、前記リードフレームの前記電気コンタクト(192)まで薄くするステップと、
− 前記蓋によって保護された前記集積回路を有するモールド済パッケージ(200)をダイシング及び分離するステップと、を含むことを特徴とする方法。
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US20160240448A1 (en) * | 2015-02-12 | 2016-08-18 | Ampleon Netherlands B.V. | RF Package |
FR3077284B1 (fr) | 2018-01-30 | 2020-03-06 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede d'encapsulation d'un dispositif microelectronique, par des substrats fins ou ultrafins, facilement manipulables |
US20190311962A1 (en) * | 2018-04-10 | 2019-10-10 | Bae Systems Information And Electronic Systems Integration Inc. | Heterogeneous integrated circuits with integrated covers |
US10896861B2 (en) * | 2019-04-22 | 2021-01-19 | Raytheon Company | Heterogeneous multi-layer MMIC assembly |
US11881494B2 (en) * | 2020-09-20 | 2024-01-23 | UTAC Headquarters Pte. Ltd. | Semiconductor package with dams |
US11784103B2 (en) * | 2020-12-09 | 2023-10-10 | Texas Instruments Incorporated | Covers for semiconductor package components |
CN116495697B (zh) * | 2023-06-26 | 2023-09-08 | 南京睿芯峰电子科技有限公司 | 含空气桥芯片的sip塑封件及其制作方法 |
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JP2004006816A (ja) * | 2002-04-17 | 2004-01-08 | Sanyo Electric Co Ltd | 半導体スイッチ回路装置およびその製造方法 |
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JP2004312666A (ja) * | 2003-03-25 | 2004-11-04 | Fuji Photo Film Co Ltd | 固体撮像装置及び固体撮像装置の製造方法 |
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2004
- 2004-12-20 FR FR0413584A patent/FR2879889B1/fr not_active Expired - Fee Related
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2005
- 2005-12-07 WO PCT/EP2005/056583 patent/WO2006067045A1/fr active Application Filing
- 2005-12-07 EP EP05815910A patent/EP1829105B1/fr active Active
- 2005-12-07 DE DE602005026448T patent/DE602005026448D1/de active Active
- 2005-12-07 US US11/722,329 patent/US20100038776A1/en not_active Abandoned
- 2005-12-07 ES ES05815910T patent/ES2363910T3/es active Active
- 2005-12-07 AT AT05815910T patent/ATE498907T1/de not_active IP Right Cessation
- 2005-12-07 JP JP2007546022A patent/JP4794569B2/ja active Active
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JPH1197564A (ja) * | 1997-09-24 | 1999-04-09 | Nec Corp | 半導体装置およびその製造方法 |
JP2003100919A (ja) * | 2001-06-11 | 2003-04-04 | Matsushita Electric Ind Co Ltd | 電子デバイス及びその製造方法 |
JP2004006816A (ja) * | 2002-04-17 | 2004-01-08 | Sanyo Electric Co Ltd | 半導体スイッチ回路装置およびその製造方法 |
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JP2015056606A (ja) * | 2013-09-13 | 2015-03-23 | 株式会社東芝 | 半導体装置 |
Also Published As
Publication number | Publication date |
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FR2879889A1 (fr) | 2006-06-23 |
JP4794569B2 (ja) | 2011-10-19 |
WO2006067045A1 (fr) | 2006-06-29 |
DE602005026448D1 (de) | 2011-03-31 |
EP1829105B1 (fr) | 2011-02-16 |
FR2879889B1 (fr) | 2007-01-26 |
US20100038776A1 (en) | 2010-02-18 |
EP1829105A1 (fr) | 2007-09-05 |
ATE498907T1 (de) | 2011-03-15 |
ES2363910T3 (es) | 2011-08-19 |
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