JP2008508717A - 相補型金属−酸化膜−半導体電界効果トランジスタ構造 - Google Patents
相補型金属−酸化膜−半導体電界効果トランジスタ構造 Download PDFInfo
- Publication number
- JP2008508717A JP2008508717A JP2007523559A JP2007523559A JP2008508717A JP 2008508717 A JP2008508717 A JP 2008508717A JP 2007523559 A JP2007523559 A JP 2007523559A JP 2007523559 A JP2007523559 A JP 2007523559A JP 2008508717 A JP2008508717 A JP 2008508717A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide
- effect transistor
- semiconductor substrate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/903,784 US7119381B2 (en) | 2004-07-30 | 2004-07-30 | Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices |
| PCT/US2005/021495 WO2006023025A1 (en) | 2004-07-30 | 2005-06-16 | Cmos with only a single implant |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008508717A true JP2008508717A (ja) | 2008-03-21 |
| JP2008508717A5 JP2008508717A5 (https=) | 2008-07-31 |
Family
ID=35731120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007523559A Pending JP2008508717A (ja) | 2004-07-30 | 2005-06-16 | 相補型金属−酸化膜−半導体電界効果トランジスタ構造 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7119381B2 (https=) |
| JP (1) | JP2008508717A (https=) |
| KR (1) | KR20070038128A (https=) |
| CN (1) | CN100524658C (https=) |
| TW (1) | TWI395329B (https=) |
| WO (1) | WO2006023025A1 (https=) |
Families Citing this family (59)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4712683B2 (ja) * | 2006-12-21 | 2011-06-29 | パナソニック株式会社 | トランジスタおよびその製造方法 |
| US7842587B2 (en) * | 2008-01-30 | 2010-11-30 | Freescale Semiconductor, Inc. | III-V MOSFET fabrication and device |
| US7952150B1 (en) | 2008-06-05 | 2011-05-31 | Rf Micro Devices, Inc. | Enhancement mode MOSFET and depletion mode FET on a common group III-V substrate |
| FR2934716B1 (fr) * | 2008-07-31 | 2010-09-10 | Commissariat Energie Atomique | Diode electroluminescente en materiau semiconducteur et son procede de fabrication |
| US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
| US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
| US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
| US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
| US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
| US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
| US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
| US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
| US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
| US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
| US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
| US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
| US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
| US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
| US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
| US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
| US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
| US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
| WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
| US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
| US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
| US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
| US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
| US8803242B2 (en) * | 2011-09-19 | 2014-08-12 | Eta Semiconductor Inc. | High mobility enhancement mode FET |
| US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
| US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
| US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
| US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
| US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
| US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
| US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
| US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
| US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
| US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
| US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
| US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
| US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
| US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
| CN104854698A (zh) | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | 具有低变化晶体管外围电路的dram型器件以及相关方法 |
| US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
| US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
| US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
| US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
| US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
| US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
| US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
| US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
| US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
| US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
| US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
| US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
| US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
| US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
| CN104779169B (zh) * | 2015-04-22 | 2017-12-08 | 上海华力微电子有限公司 | 一种双工作电压FinFET结构器件的制造方法 |
| US9722065B1 (en) * | 2016-02-03 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6159875A (ja) * | 1984-08-31 | 1986-03-27 | Fujitsu Ltd | 相補型半導体装置 |
| JPS63185056A (ja) * | 1987-01-28 | 1988-07-30 | Hitachi Ltd | 半導体装置 |
| JPH06104290A (ja) * | 1992-09-22 | 1994-04-15 | Fujitsu Ltd | 化合物半導体装置の製造方法 |
| JPH08255877A (ja) * | 1995-03-17 | 1996-10-01 | Fujitsu Ltd | 相補型電界効果トランジスタ及びその製造方法 |
| WO2004064172A2 (en) * | 2003-01-09 | 2004-07-29 | Freescale Semiconductor, Inc. | An enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983620A (en) * | 1975-05-08 | 1976-10-05 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
| EP0206274B1 (en) | 1985-06-21 | 1991-10-23 | Honeywell Inc. | High transconductance complementary ic structure |
| US4729000A (en) | 1985-06-21 | 1988-03-01 | Honeywell Inc. | Low power AlGaAs/GaAs complementary FETs incorporating InGaAs n-channel gates |
| US4746627A (en) | 1986-10-30 | 1988-05-24 | Mcdonnell Douglas Corporation | Method of making complementary GaAs heterojunction transistors |
| US5223724A (en) * | 1990-07-31 | 1993-06-29 | At & T Bell Laboratories | Multiple channel high electron mobility transistor |
| US5060031A (en) | 1990-09-18 | 1991-10-22 | Motorola, Inc | Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices |
| US5945718A (en) | 1998-02-12 | 1999-08-31 | Motorola Inc. | Self-aligned metal-oxide-compound semiconductor device and method of fabrication |
-
2004
- 2004-07-30 US US10/903,784 patent/US7119381B2/en not_active Expired - Lifetime
-
2005
- 2005-06-16 WO PCT/US2005/021495 patent/WO2006023025A1/en not_active Ceased
- 2005-06-16 CN CNB200580024017XA patent/CN100524658C/zh not_active Expired - Fee Related
- 2005-06-16 KR KR1020077002248A patent/KR20070038128A/ko not_active Withdrawn
- 2005-06-16 JP JP2007523559A patent/JP2008508717A/ja active Pending
- 2005-07-13 TW TW094123768A patent/TWI395329B/zh not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6159875A (ja) * | 1984-08-31 | 1986-03-27 | Fujitsu Ltd | 相補型半導体装置 |
| JPS63185056A (ja) * | 1987-01-28 | 1988-07-30 | Hitachi Ltd | 半導体装置 |
| JPH06104290A (ja) * | 1992-09-22 | 1994-04-15 | Fujitsu Ltd | 化合物半導体装置の製造方法 |
| JPH08255877A (ja) * | 1995-03-17 | 1996-10-01 | Fujitsu Ltd | 相補型電界効果トランジスタ及びその製造方法 |
| WO2004064172A2 (en) * | 2003-01-09 | 2004-07-29 | Freescale Semiconductor, Inc. | An enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1985365A (zh) | 2007-06-20 |
| TW200620654A (en) | 2006-06-16 |
| WO2006023025A1 (en) | 2006-03-02 |
| CN100524658C (zh) | 2009-08-05 |
| TWI395329B (zh) | 2013-05-01 |
| US20060022217A1 (en) | 2006-02-02 |
| KR20070038128A (ko) | 2007-04-09 |
| US7119381B2 (en) | 2006-10-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008508717A (ja) | 相補型金属−酸化膜−半導体電界効果トランジスタ構造 | |
| US20090134402A1 (en) | Silicon carbide mos field-effect transistor and process for producing the same | |
| CN108604600B (zh) | 碳化硅半导体装置及其制造方法 | |
| JP7024761B2 (ja) | 窒化物半導体装置および窒化物半導体装置の製造方法 | |
| WO2023233802A1 (ja) | 半導体装置の製造方法 | |
| JP2020057636A (ja) | 窒化物半導体装置および窒化物半導体装置の製造方法 | |
| JP2010251505A (ja) | 窒化物半導体装置 | |
| US6245624B1 (en) | Methods of fabricating field effect transistors by first forming heavily doped source/drain regions and then forming lightly doped source/drain regions | |
| JP7290540B2 (ja) | 半導体装置 | |
| JP4541489B2 (ja) | 半導体装置及びその製造方法 | |
| KR101911764B1 (ko) | 게르마늄층을 채널 영역으로 하는 반도체 장치 및 그 제조 방법 | |
| JPS6354231B2 (https=) | ||
| JP4713078B2 (ja) | 半導体装置の製造方法および半導体装置 | |
| JPH0575041A (ja) | Cmos半導体装置 | |
| JPH01214172A (ja) | 半導体装置の製造方法 | |
| JPH11204783A (ja) | 半導体装置およびその製造方法 | |
| JPH04158529A (ja) | 半導体素子の製造方法 | |
| JPH06326316A (ja) | 半導体装置の製造方法 | |
| JPH0311731A (ja) | 半導体装置の製造方法 | |
| JPH11135801A (ja) | 薄膜トランジスタの製造方法 | |
| KR940016884A (ko) | 엘디디(ldd)형 모스 트랜지스터 제조방법 | |
| JPH0260218B2 (https=) | ||
| JPH06224421A (ja) | Mos電界効果トランジスタ | |
| JPH07283402A (ja) | 半導体装置とその製造方法 | |
| JP2004031492A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080611 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080611 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110830 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111130 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120124 |