JP2008219232A - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP2008219232A
JP2008219232A JP2007051170A JP2007051170A JP2008219232A JP 2008219232 A JP2008219232 A JP 2008219232A JP 2007051170 A JP2007051170 A JP 2007051170A JP 2007051170 A JP2007051170 A JP 2007051170A JP 2008219232 A JP2008219232 A JP 2008219232A
Authority
JP
Japan
Prior art keywords
signal
type transistor
circuit
delay clock
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007051170A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008219232A5 (enExample
Inventor
Akira Masuo
昭 増尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2007051170A priority Critical patent/JP2008219232A/ja
Priority to US12/027,411 priority patent/US20080211556A1/en
Priority to CNA2008100809379A priority patent/CN101256824A/zh
Publication of JP2008219232A publication Critical patent/JP2008219232A/ja
Publication of JP2008219232A5 publication Critical patent/JP2008219232A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Static Random-Access Memory (AREA)
  • Pulse Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2007051170A 2007-03-01 2007-03-01 半導体集積回路 Withdrawn JP2008219232A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007051170A JP2008219232A (ja) 2007-03-01 2007-03-01 半導体集積回路
US12/027,411 US20080211556A1 (en) 2007-03-01 2008-02-07 Semiconductor integrated circuit
CNA2008100809379A CN101256824A (zh) 2007-03-01 2008-02-29 半导体集成电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007051170A JP2008219232A (ja) 2007-03-01 2007-03-01 半導体集積回路

Publications (2)

Publication Number Publication Date
JP2008219232A true JP2008219232A (ja) 2008-09-18
JP2008219232A5 JP2008219232A5 (enExample) 2010-02-25

Family

ID=39732670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007051170A Withdrawn JP2008219232A (ja) 2007-03-01 2007-03-01 半導体集積回路

Country Status (3)

Country Link
US (1) US20080211556A1 (enExample)
JP (1) JP2008219232A (enExample)
CN (1) CN101256824A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5963647B2 (ja) * 2012-01-30 2016-08-03 エスアイアイ・セミコンダクタ株式会社 半導体記憶回路を備えた半導体装置
CN110956990B (zh) * 2018-09-26 2022-03-01 展讯通信（上海）有限公司 Sram读取延时控制电路及sram
CN114545807B (zh) * 2020-11-25 2024-03-26 长鑫存储技术有限公司 控制电路和延时电路
EP4033661B1 (en) 2020-11-25 2024-01-24 Changxin Memory Technologies, Inc. Control circuit and delay circuit
US11681313B2 (en) 2020-11-25 2023-06-20 Changxin Memory Technologies, Inc. Voltage generating circuit, inverter, delay circuit, and logic gate circuit
EP4033664B1 (en) 2020-11-25 2024-01-10 Changxin Memory Technologies, Inc. Potential generation circuit, inverter, delay circuit, and logic gate circuit
EP4033312B1 (en) 2020-11-25 2024-08-21 Changxin Memory Technologies, Inc. Control circuit and delay circuit
CN114582392B (zh) * 2021-12-14 2025-04-18 上海华力集成电路制造有限公司 写入辅助电路

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3071915B2 (ja) * 1991-12-20 2000-07-31 株式会社東芝 出力回路
US5424985A (en) * 1993-06-30 1995-06-13 Sgs-Thomson Microelectronics, Inc. Compensating delay element for clock generation in a memory device
US5841300A (en) * 1994-04-18 1998-11-24 Hitachi, Ltd. Semiconductor integrated circuit apparatus
US6590423B1 (en) * 1994-10-11 2003-07-08 Derek Wong Digital circuits exhibiting reduced power consumption
US5517136A (en) * 1995-03-03 1996-05-14 Intel Corporation Opportunistic time-borrowing domino logic
US5661675A (en) * 1995-03-31 1997-08-26 Intel Corporation Positive feedback circuit for fast domino logic
US6104213A (en) * 1998-03-02 2000-08-15 International Business Machines Corporation Domino logic circuit having a clocked precharge
US6097207A (en) * 1998-08-21 2000-08-01 International Business Machines Corporation Robust domino circuit design for high stress conditions
JP3358612B2 (ja) * 1999-03-15 2002-12-24 日本電気株式会社 半導体集積回路
JP3241686B2 (ja) * 1999-03-26 2001-12-25 日本電気株式会社 ダイナミック型論理回路及びドミノ論理素子
US6137319A (en) * 1999-04-30 2000-10-24 Intel Corporation Reference-free single ended clocked sense amplifier circuit
US6346831B1 (en) * 1999-09-28 2002-02-12 Intel Corporation Noise tolerant wide-fanin domino circuits
US6549040B1 (en) * 2000-06-29 2003-04-15 Intel Corporation Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates
US6469953B1 (en) * 2001-08-08 2002-10-22 Intel Corporation Latch circuit
US6429689B1 (en) * 2001-10-10 2002-08-06 International Business Machines Corporation Method and apparatus for controlling both active and standby power in domino circuits
US6933744B2 (en) * 2002-06-11 2005-08-23 The Regents Of The University Of Michigan Low-leakage integrated circuits and dynamic logic circuits
US7218151B1 (en) * 2002-06-28 2007-05-15 University Of Rochester Domino logic with variable threshold voltage keeper
JP2004048313A (ja) * 2002-07-11 2004-02-12 Matsushita Electric Ind Co Ltd ダイナミック回路
US6765414B2 (en) * 2002-09-17 2004-07-20 Intel Corporation Low frequency testing, leakage control, and burn-in control for high-performance digital circuits
US7034576B2 (en) * 2003-06-27 2006-04-25 Sun Microsystems, Inc. Pulsed dynamic keeper gating
US7202705B2 (en) * 2004-10-14 2007-04-10 International Business Machines Corporation Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
US7282960B2 (en) * 2005-06-28 2007-10-16 International Business Machines Corporation Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
JP2007096907A (ja) * 2005-09-29 2007-04-12 Matsushita Electric Ind Co Ltd 半導体集積回路
US7764087B2 (en) * 2006-02-01 2010-07-27 Wisconsin Alumni Research Foundation Low swing domino logic circuits
US7332938B2 (en) * 2006-06-23 2008-02-19 The Curators Of The University Of Missouri Domino logic testing systems and methods

Also Published As

Publication number Publication date
CN101256824A (zh) 2008-09-03
US20080211556A1 (en) 2008-09-04

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