JP2008205454A - 選択エピタキシープロセス制御 - Google Patents
選択エピタキシープロセス制御 Download PDFInfo
- Publication number
- JP2008205454A JP2008205454A JP2008019367A JP2008019367A JP2008205454A JP 2008205454 A JP2008205454 A JP 2008205454A JP 2008019367 A JP2008019367 A JP 2008019367A JP 2008019367 A JP2008019367 A JP 2008019367A JP 2008205454 A JP2008205454 A JP 2008205454A
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- Prior art keywords
- zone
- gas
- process chamber
- deposition
- silicon
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Links
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- 238000012546 transfer Methods 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
-
- H—ELECTRICITY
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Abstract
【解決手段】 一つ以上の実施形態において、プロセスチャンバの圧力を、基板上に物質を堆積させる間では下げ、基板から物質をエッチングする間では上げる。実施形態によれば、第1ゾーンに流されるガス量と第2ゾーンに流されるガス量の比を得るようにプロセスガスが第1ゾーンと第2ゾーンを通ってチャンバへ流される。一つ以上の実施形態において、第1ゾーンは内部半径方向ゾーンであり、第2ゾーンは外部半径方向ゾーンであり、内部ゾーンガス流と外部ゾーンガス流との比はエッチングの間より堆積の間の方が小さい。一つ以上の実施形態によれば、選択的エピタキシャルプロセスは、エピタキシャル層の所望の厚さが成長するまで、堆積と、その後のエッチングプロセスと、所望によるパージのサイクルを繰り返すステップを含む。
Description
概要
[0008]一実施形態によれば、基板表面上にシリコン含有物質を選択的に且つエピタキシャル的に形成する方法は、
a)単結晶表面と少なくとも誘電体表面を備える基板をプロセスチャンバへ配置するステップであって、プロセスチャンバが第1ゾーンと第2ゾーンとを含む前記ステップと;
b)基板をシリコン含有堆積ガスに曝し、プロセスチャンバの圧力を約50トール未満に維持して、単結晶表面上にエピタキシャル層と誘電体表面上に第2物質を形成するステップと;
c)続いて、プロセスチャンバへの堆積ガス流を停止し、プロセスチャンバの圧力を上げ、基板をエッチングガスに曝して、相対的に高いエッチングガス分圧を維持するとともに第2物質をエッチングするステップと;
d)続いて、プロセスチャンバへのエッチングガス流を停止し、プロセスチャンバへパージガス流を流すステップと;
e)ステップb)、c)、d)を順次少なくとも一回繰り返すステップと;
を含む。
詳細な説明
[0020]本発明の実施形態は、一般的には、電子デバイスの製造で基板の単結晶表面上にシリコン含有物質を選択的に且つエピタキシャル的に堆積させるプロセスを提供する。単結晶表面(例えば、シリコン又はシリコンゲルマニウム)と少なくとも第2表面、アモルファス表面及び/又は多結晶表面(例えば、酸化物又は窒化物)を含有するパターン形成された基板をエピタキシャルプロセスに曝して、第2表面上に制限された多結晶層を形成するか又は形成せずに、単結晶表面上にエピタキシャル層を形成する。一つ以上の実施形態によれば、エピタキシャルプロセスは、交互ガス供給(AGS)プロセスとも言われ、エピタキシャルプロセスは、エピタキシャル層の所望の厚さに成長するまで堆積プロセスとエッチングプロセスのサイクルを繰り返すことを含む。AGSプロセスは、SelectiveEpitaxy Process With Alternating Gas Supplyと称する米国特許出願公開第2006/0115934号として公開された同時系属中の共同譲渡された米国特許出願第11/001,774号に記載されている。一つ以上の実施形態によれば、交互ガス供給プロセスは、エピタキシャル層の所望の厚さに成長するまで、堆積プロセスと、エッチングプロセスと、パージプロセスのサイクルを繰り返すことを含むのがよい。
[0071]凹部構造を持つ基板と凹部構造を持たない基板の二タイプのパターン形成基板へのシリコンとSiGeの選択的エピタキシー。各タイプの基板を、AccusettTM計量バルブを持つEPICentura RP処理チャンバに挿入した。SiGe層を、従来のコフロープロセスを用いるその後の選択的シリコン堆積に“マーカー層”として使用するように選択的に堆積させた。シリコン堆積のためのプロセス条件は以下の通りであった:堆積圧力は10トールであり、シランを50sccmで流し、ジクロロシランを15sccmで流し、水素キャリヤガスを5SLMで流した。上で定義されたI/O比は、計量バルブを用いて100/250に設定した。堆積を750℃で5秒間行った。エッチングステップを行った。プロセスチャンバ圧を約100トールに上げ、HClエッチング剤を5SLMの水素キャリヤガスとともに650sccmで流し、ガスは760℃で6.5秒間250/100のI/O比で流した。その後、圧力を10トールに750℃で10秒間減じ、水素パージガスを100/250のI/O比で流すことによって、プロセスチャンバをパージした。堆積、エッチング、パージのこのようなシーケンスを17回繰り返した。
[0073]例1のプロセス条件を、高密度の凹部を持つ基板上に繰り返した。堆積の間、処理チャンバの圧力を5トールに維持し、エッチングの間、圧力を70トールに上げた。パージの間、圧力を5トールに減じた。本実施例で得られた成長速度は、100オングストローム毎分を超えたが、顕微鏡を用いて膜を調べると、すみに小さいファセットプロファイルが示された。
[0074]実施例2のプロセス条件を、凹部パターン構造を持たない基板で繰り返したが、本実施例では、窒素をキャリヤガスとして用い、温度を700℃に下げた。得られた成長速度は35オングストローム/分であり、プロセスチャンバへエッチングガスと堆積ガスを同時に流す従来の方法を用いて観測された約12-15オングストローム/分の成長速度の約2倍である。
Claims (20)
- 基板表面上にシリコン含有物質を選択的に且つエピタキシャル的に形成する方法であって、
a)単結晶表面と少なくとも誘電体表面を備える基板をプロセスチャンバへ配置するステップであって、該プロセスチャンバが第1ゾーンと第2ゾーンとを含む前記ステップと;
b)該基板をシリコン含有堆積ガスに曝し、該プロセスチャンバの圧力を約50トール未満に維持して、該単結晶表面上にエピタキシャル層を、また、該誘電体表面上に第2物質を形成するステップと;
c)続いて、該プロセスチャンバへの堆積ガス流を停止し、該プロセスチャンバの圧力を上げ、該基板をエッチングガスに曝して、相対的に高いエッチングガス分圧を維持するとともに第2物質をエッチングするステップと;
d)続いて、該プロセスチャンバへのエッチングガス流を停止し、該プロセスチャンバへパージガスを流すステップと;
e)ステップb)、c)、d)を順次少なくとも一回繰り返すステップと;
を含む前記方法。 - 該第1ゾーンと該第2ゾーンへの該ガス流を制御して、第1ゾーンガス流と第2ゾーンガス流との比を得、該比がステップb)とステップc)で異なるように第1ゾーンガス流と第2ゾーンガス流との比を変えるステップを更に含む、請求項1に記載の方法。
- 該第1ゾーンが内部半径方向ゾーンを含み、該第2ゾーンが外部半径方向ゾーンを含み、該ガスがプロセスチャンバへの内部ゾーンガス流と外部ゾーンガス流との比(I/O)を得る方法で流され、該基板を該堆積ガスに曝す間、I/Oを約1未満に維持し、該基板を該エッチングガスに曝す間、約1を超えるI/Oに維持する、請求項2に記載の方法。
- エッチングガスが該プロセスチャンバへほとんど流されず、該堆積ガスが該プロセスチャンバへ流れる、請求項3に記載の方法。
- 該基板を該堆積ガスに曝す間の該I/Oが約0.2〜1.0であり、該基板を該エッチングガスへ曝す間の該I/Oが約1.0を超え、約6.0未満である、請求項3に記載の方法。
- 該エッチングガスに曝す間、該プロセスチャンバの圧力の増加によって該基板温度が上がり、該パージガスに曝す間、該チャンバ圧が低下し、それにより、該基板温度が下がる、請求項1に記載の方法。
- 該エッチングガスに曝す間の該プロセスチャンバの圧力が、該基板を該堆積ガスに曝す間の該プロセスチャンバの圧力の約2〜約10倍である、請求項6に記載の方法。
- 該プロセスの温度が、全プロセス中、約800℃未満に維持される、請求項6に記載の方法。
- 該プロセスの温度が、全プロセス中、約750℃未満に維持される、請求項7に記載の方法。
- 基板表面上にシリコン含有物質を選択的に且つエピタキシャル的に形成する方法であって、
単結晶表面と少なくとも誘電体表面を備える基板をプロセスチャンバへ配置するステップであって、該プロセスチャンバが第1ガス流ゾーンと第2ガス流ゾーンとを含む、前記ステップと;
シリコン含有堆積ガスを第1圧力で該プロセスチャンバへ、また、該第1ゾーンと第2ゾーンへ流すステップであって、該第1ゾーンと該第2ゾーンとの堆積ガス流比が1未満である、前記ステップと;
続いて、該プロセスチャンバへの堆積ガス流を停止し、該プロセスチャンバの圧力を第2圧力に上げ、エッチングガスをプロセスチャンバの該内部半径方向ゾーンと外部半径方向ゾーンへ1を超える該第1ゾーンガス流と第2ゾーンガス流とのエッチングガス流比で流すステップと;
続いて、該プロセスチャンバへのエッチングガス流を停止し、該プロセスチャンバへパージガス流を流すステップと;
該堆積ガスを流し、該エッチングガスを流し、該パージガスを流す連続ステップを、所望の厚さを有するシリコン含有物質が形成されるまで少なくとも一回繰り返すステップと;
を含む前記方法。 - 該エッチングガスに曝す間、該プロセスチャンバの圧力の増加によって該基板温度が上がり、該パージガスに曝す間、該チャンバ圧を低下させ、それにより、該基板温度が下がる、請求項10記載の方法。
- 第2圧力が第1圧力の約2〜10倍である、請求項11に記載の方法。
- 該堆積ガスを流す間、該第1ゾーンと該第2ゾーンとのガス流比が約0.2〜1.0である、請求項12に記載の方法。
- 該エッチングガスを流す間、該第1ゾーンと該第2ゾーンとのガス流比が、約1.0を超え、約6.0未満である、請求項12に記載の方法。
- 基板表面上にシリコン含有物質を選択的に且つエピタキシャル的に形成する方法であって、
単結晶表面と少なくとも誘電体表面を備える基板をプロセスチャンバへ配置するステップであって、該プロセスチャンバが第1ガス流ゾーンと第2ガス流ゾーンとを含む前記ステップと;
エッチングガスが該プロセスチャンバへ流されていない該プロセスチャンバへシリコン含有ガスを流す工程を含む堆積ステップを行うステップと;
シリコン含有ガスが該プロセスチャンバへ流されていない該プロセスチャンバへエッチングガスを流す工程を含むエッチングステップを行うステップと;
パージガスが流されるパージステップを行うステップであって、単一プロセスサイクルが堆積ステップとエッチングステップとパージステップとを含み、該プロセスサイクルを少なくとも一回繰り返し、ガスを該第1ゾーンと第2ゾーンに流して、該堆積ステップとエッチングステップとパージステップのそれぞれの間の該プロセスチャンバの圧力と該第1ゾーンと第2ゾーンとのガス流比を得、該プロセスチャンバの圧力の少なくとも一つと該ガス流比が該堆積ステップと該エッチングステップの間で異なる、前記ステップと;
を含む前記方法。 - 該プロセスチャンバの圧力が、エッチングの間より該堆積の間の方が低く、結果としてエッチングの間より堆積の間の方が基板温度が低くなる、請求項15に記載の方法。
- 該第1ゾーンと該第2ゾーンのガス流比が、該エッチングステップの間より該堆積ステップの間の方が小さい、請求項16に記載の方法。
- 該第1ゾーンが該プロセスチャンバの内部半径方向ゾーンを備え、該第2ゾーンが該チャンバの外部半径方向ゾーンを備える、請求項17に記載の方法。
- エッチングの間の圧力が、堆積の間の圧力の少なくとも2倍である、請求項17に記載の方法。
- 約800℃未満の温度でプロセスが行われる、請求項19に記載の方法。
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