JP2008141061A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008141061A JP2008141061A JP2006327323A JP2006327323A JP2008141061A JP 2008141061 A JP2008141061 A JP 2008141061A JP 2006327323 A JP2006327323 A JP 2006327323A JP 2006327323 A JP2006327323 A JP 2006327323A JP 2008141061 A JP2008141061 A JP 2008141061A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chip
- ground plane
- semiconductor chip
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19032—Structure including wave guides being a microstrip line type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】半導体装置1は、半導体チップ10、パッケージ基板20(配線基板)、伝送路30、およびダミーチップ40(回路部品)を備えている。パッケージ基板20の上面上には、伝送路30が設けられている。伝送路30は、半導体チップ10からの信号を伝送する。ダミーチップ40は、グランドプレーンを有している。伝送路30の一部は、このグランドプレーンと共にマイクロストリップ線路を構成している。
【選択図】図1
Description
10 半導体チップ
12 シリコン基板
14 配線層
15 グランド配線
20 パッケージ基板
22 絶縁膜
30 伝送路
30a 第1の部分
30b 第2の部分
31a 接続部
31b 接続部
32 グランド線
33a 接続部
33b 接続部
34 電源線
36 グランド線
40 ダミーチップ
42 シリコン基板
43 絶縁層
44 電源プレーン
46 グランドプレーン
47 信号線
48 信号線
49 貫通電極
50 半田ボール
52 導体プラグ
62 アンダーフィル樹脂
64 封止樹脂
70 半導体チップ
72 導体バンプ
74 アンダーフィル樹脂
82 導体バンプ
84 導体バンプ
90 支持基板
91 シード膜
92 シード膜
93 フォトレジスト
Claims (9)
- 半導体チップを備える半導体装置であって、
配線基板と、
前記配線基板の第1面上に設けられ、前記半導体チップからの信号を伝送する伝送路と、
前記配線基板の前記第1面の上方に設けられたグランドプレーンと、を備え、
前記伝送路の少なくとも一部は、前記グランドプレーンと共にマイクロストリップ線路を構成していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記配線基板の前記第1面上に実装され、前記グランドプレーンを有する回路部品を備える半導体装置。 - 請求項2に記載の半導体装置において、
前記回路部品は、フリップチップボンディングによって、前記配線基板の前記第1面上に実装されている半導体装置。 - 請求項2または3に記載の半導体装置において、
前記回路部品は、ダミーチップである半導体装置。 - 請求項2乃至4いずれかに記載の半導体装置において、
前記半導体チップは、前記回路部品上に実装されている半導体装置。 - 請求項2乃至4いずれかに記載の半導体装置において、
前記半導体チップおよび前記回路部品は、前記配線基板の前記第1面の相異なる領域上に実装されている半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記配線基板の前記第1面と反対側の面である第2面上には、グランドプレーンが設けられていない半導体装置。 - 請求項1乃至7いずれかに記載の半導体装置において、
前記伝送路は、前記マイクロストリップ線路を構成する第1の部分と、前記第1の部分に連設され、コプレーナ線路を構成する第2の部分と、を含んでいる半導体装置。 - 請求項8に記載の半導体装置において、
前記グランドプレーンは、前記伝送路の前記第1および第2の部分のうち、前記第1の部分にのみ対向している半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006327323A JP4897451B2 (ja) | 2006-12-04 | 2006-12-04 | 半導体装置 |
US11/987,624 US20080128916A1 (en) | 2006-12-04 | 2007-12-03 | Semiconductor device including microstrip line and coplanar line |
CNA2007101865136A CN101197343A (zh) | 2006-12-04 | 2007-12-04 | 包括有微带线和共面线的半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006327323A JP4897451B2 (ja) | 2006-12-04 | 2006-12-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008141061A true JP2008141061A (ja) | 2008-06-19 |
JP4897451B2 JP4897451B2 (ja) | 2012-03-14 |
Family
ID=39474777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006327323A Expired - Fee Related JP4897451B2 (ja) | 2006-12-04 | 2006-12-04 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20080128916A1 (ja) |
JP (1) | JP4897451B2 (ja) |
CN (1) | CN101197343A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9721876B2 (en) | 2014-12-17 | 2017-08-01 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method of making the same |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090321932A1 (en) * | 2008-06-30 | 2009-12-31 | Javier Soto Gonzalez | Coreless substrate package with symmetric external dielectric layers |
JP5579402B2 (ja) * | 2009-04-13 | 2014-08-27 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法並びに電子装置 |
US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
US20110221053A1 (en) * | 2010-03-11 | 2011-09-15 | Qualcomm Incorporated | Pre-processing to reduce wafer level warpage |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US20120001339A1 (en) * | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8127979B1 (en) * | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
FR2966982B1 (fr) | 2010-10-27 | 2012-12-07 | St Microelectronics Sa | Ligne de transmission pour circuits electroniques |
US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
US8848380B2 (en) | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
CN103765578B (zh) * | 2011-08-31 | 2016-09-14 | 飞思卡尔半导体公司 | 集成电路封装 |
US9620430B2 (en) * | 2012-01-23 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sawing underfill in packaging processes |
US20130265733A1 (en) * | 2012-04-04 | 2013-10-10 | Texas Instruments Incorporated | Interchip communication using an embedded dielectric waveguide |
US9257368B2 (en) | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
DE112012006469B4 (de) | 2012-06-08 | 2022-05-05 | Intel Corporation | Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel |
US9685350B2 (en) * | 2013-03-08 | 2017-06-20 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB |
JP2015056563A (ja) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | 半導体装置およびその製造方法 |
US9922964B1 (en) * | 2016-09-19 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with dummy die |
US10297471B2 (en) * | 2016-12-15 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out structure and method of fabricating the same |
CN106783633B (zh) * | 2016-12-26 | 2020-02-14 | 通富微电子股份有限公司 | 一种扇出的封装结构及其封装方法 |
US9978698B1 (en) * | 2017-01-25 | 2018-05-22 | Raytheon Company | Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members |
KR102397902B1 (ko) * | 2018-01-29 | 2022-05-13 | 삼성전자주식회사 | 반도체 패키지 |
KR102450575B1 (ko) * | 2018-07-10 | 2022-10-07 | 삼성전자주식회사 | 뒤틀림의 제어를 위한 채널을 포함하는 반도체 칩 모듈 및 이의 제조 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005197926A (ja) * | 2004-01-06 | 2005-07-21 | Renesas Technology Corp | 高周波モジュール及びその製造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5544017A (en) * | 1992-08-05 | 1996-08-06 | Fujitsu Limited | Multichip module substrate |
US6728113B1 (en) * | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
CA2178681C (en) * | 1995-06-15 | 2001-01-16 | Attilio Joseph Rainal | Low-crosstalk modular electrical connector assembly |
US5872393A (en) * | 1995-10-30 | 1999-02-16 | Matsushita Electric Industrial Co., Ltd. | RF semiconductor device and a method for manufacturing the same |
US6329702B1 (en) * | 2000-07-06 | 2001-12-11 | Tyco Electronics Corporation | High frequency carrier |
TW459361B (en) * | 2000-07-17 | 2001-10-11 | Siliconware Precision Industries Co Ltd | Three-dimensional multiple stacked-die packaging structure |
US6414384B1 (en) * | 2000-12-22 | 2002-07-02 | Silicon Precision Industries Co., Ltd. | Package structure stacking chips on front surface and back surface of substrate |
US7034386B2 (en) * | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
US20030038356A1 (en) * | 2001-08-24 | 2003-02-27 | Derderian James M | Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods |
US20030150641A1 (en) * | 2002-02-14 | 2003-08-14 | Noyan Kinayman | Multilayer package for a semiconductor device |
US6891266B2 (en) * | 2002-02-14 | 2005-05-10 | Mia-Com | RF transition for an area array package |
SG111935A1 (en) * | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
JP3688249B2 (ja) * | 2002-04-05 | 2005-08-24 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
TW556961U (en) * | 2002-12-31 | 2003-10-01 | Advanced Semiconductor Eng | Multi-chip stack flip-chip package |
KR100541393B1 (ko) * | 2003-04-26 | 2006-01-10 | 삼성전자주식회사 | 멀티칩 bga 패키지 |
JP4467318B2 (ja) * | 2004-01-28 | 2010-05-26 | Necエレクトロニクス株式会社 | 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法 |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4365750B2 (ja) * | 2004-08-20 | 2009-11-18 | ローム株式会社 | 半導体チップの製造方法、および半導体装置の製造方法 |
TWI255536B (en) * | 2005-02-02 | 2006-05-21 | Siliconware Precision Industries Co Ltd | Chip-stacked semiconductor package and fabrication method thereof |
JP4790297B2 (ja) * | 2005-04-06 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7582960B2 (en) * | 2005-05-05 | 2009-09-01 | Stats Chippac Ltd. | Multiple chip package module including die stacked over encapsulated package |
-
2006
- 2006-12-04 JP JP2006327323A patent/JP4897451B2/ja not_active Expired - Fee Related
-
2007
- 2007-12-03 US US11/987,624 patent/US20080128916A1/en not_active Abandoned
- 2007-12-04 CN CNA2007101865136A patent/CN101197343A/zh active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005197926A (ja) * | 2004-01-06 | 2005-07-21 | Renesas Technology Corp | 高周波モジュール及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9721876B2 (en) | 2014-12-17 | 2017-08-01 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method of making the same |
Also Published As
Publication number | Publication date |
---|---|
CN101197343A (zh) | 2008-06-11 |
JP4897451B2 (ja) | 2012-03-14 |
US20080128916A1 (en) | 2008-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4897451B2 (ja) | 半導体装置 | |
US11469201B2 (en) | Semiconductor package and method for fabricating base for semiconductor package | |
US9607947B2 (en) | Reliable microstrip routing for electronics components | |
US20190148268A1 (en) | Underfill material flow control for reduced die-to-die spacing in semiconductor packages | |
US6462423B1 (en) | Flip-chip with matched lines and ground plane | |
US9177899B2 (en) | Semiconductor package and method for fabricating base for semiconductor package | |
US7791173B2 (en) | Chip having side pad, method of fabricating the same and package using the same | |
EP1223617B1 (en) | Multichip module with a plurality of semiconductor chips mounted on a semiconductor substrate | |
US8154125B2 (en) | Chip package structure | |
US7816754B2 (en) | Ball grid array package construction with raised solder ball pads | |
US20100237491A1 (en) | Semiconductor package with reduced internal stress | |
JP2005260053A (ja) | 半導体装置及び半導体装置の製造方法 | |
KR20080031644A (ko) | 반도체 디바이스 및 반도체 디바이스의 제조 방법 | |
US8975760B2 (en) | Semiconductor device reducing risks of a wire short-circuit and a wire flow | |
KR20120070193A (ko) | 패키지 및 이의 제조 방법 | |
TWI260753B (en) | Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus | |
US11177199B2 (en) | Semiconductor packages with external bump pads having trench portions and semiconductor modules including the semiconductor packages | |
JP4728079B2 (ja) | 半導体装置用基板および半導体装置 | |
US8603911B2 (en) | Semiconductor device and fabrication method thereof | |
JP2004133762A (ja) | データキャリア及びその製造方法 | |
JP2001267489A (ja) | 半導体装置および半導体チップ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091112 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110120 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110201 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110331 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111220 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111222 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150106 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |