JP2008071883A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2008071883A JP2008071883A JP2006248324A JP2006248324A JP2008071883A JP 2008071883 A JP2008071883 A JP 2008071883A JP 2006248324 A JP2006248324 A JP 2006248324A JP 2006248324 A JP2006248324 A JP 2006248324A JP 2008071883 A JP2008071883 A JP 2008071883A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000463 material Substances 0.000 claims abstract description 32
- 230000008859 change Effects 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 8
- 238000011144 upstream manufacturing Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 description 13
- 239000011241 protective layer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】配線基板20にフェースダウンボンディングされた半導体チップ10の周囲でノズル32を移動させ、ノズル32からアンダーフィル材を連続的に供給して、配線基板20と半導体チップ10の間にアンダーフィル材を充填する。半導体チップ10の配線基板20との対向面の輪郭は複数の辺から構成された多角形である。ノズル32の移動軌跡は、辺の両端から直角に引いた一対の線分L,Lの範囲内にある直線軌跡40と、隣同士の直線軌跡40を接続するために方向を変える方向転換軌跡50と、が連続する。方向転換軌跡50では、直線軌跡40よりも、ノズル32を速く移動させる。
【選択図】図2
Description
配線基板にフェースダウンボンディングされた半導体チップの周囲でノズルを移動させ、前記ノズルからアンダーフィル材を連続的に供給して、前記配線基板と前記半導体チップの間に前記アンダーフィル材を充填することを含み、
前記半導体チップの前記配線基板との対向面の輪郭は複数の辺から構成された多角形であり、
前記ノズルの移動軌跡は、前記辺の両端から、前記辺となす角が直角となるように引いた一対の線分の範囲内にある直線軌跡と、隣同士の前記直線軌跡を接続する方向転換軌跡と、が連続し、
前記直線軌跡の少なくとも一部分では、前記方向転換軌跡よりも、前記ノズルを遅く移動させる。本発明によれば、前記直線軌跡の少なくとも一部分では、前記方向転換軌跡よりも、前記ノズルを遅く移動させる、言い換えると方向転換軌跡でノズルを速く移動させるので、方向転換軌跡ではアンダーフィル材の供給量を減らすことができる。方向転換軌跡は、半導体チップの角部に対応しており、従来、角部で最もアンダーフィル材が半導体チップに乗り上げることが多かったが、本発明によって、半導体チップの上に乗り上げないようにアンダーフィル材を供給することができる。
(2)この半導体装置の製造方法において、
前記ノズルの移動方向において前記方向転換軌跡よりも上流に位置する前記直線軌跡は、前記方向転換軌跡に直接接続する接続軌跡と、前記接続軌跡が介在することで下流側の前記方向転換軌跡に直接接続しない非接続軌跡と、を含み、
前記接続軌跡では、前記非接続軌跡よりも、前記ノズルを速く移動させてもよい。
(3)この半導体装置の製造方法において、
前記接続軌跡と前記方向転換軌跡では、前記ノズルを同じ速度で移動させてもよい。
(4)この半導体装置の製造方法において、
前記ノズルの移動方向において前記方向転換軌跡よりも上流に位置する前記直線軌跡は、前記方向転換軌跡に直接接続する接続軌跡と、前記接続軌跡が介在することで下流側の前記方向転換軌跡に直接接続しない非接続軌跡と、を含み、
前記非接続軌跡において、前記方向転換軌跡よりも前記ノズルを遅く移動させてもよい。
Claims (4)
- 配線基板にフェースダウンボンディングされた半導体チップの周囲でノズルを移動させ、前記ノズルからアンダーフィル材を連続的に供給して、前記配線基板と前記半導体チップの間に前記アンダーフィル材を充填することを含み、
前記半導体チップの前記配線基板との対向面の輪郭は複数の辺から構成された多角形であり、
前記ノズルの移動軌跡は、前記辺の両端から、前記辺となす角が直角となるように引いた一対の線分の範囲内にある直線軌跡と、隣同士の前記直線軌跡を接続する方向転換軌跡と、が連続し、
前記直線軌跡の少なくとも一部分では、前記方向転換軌跡よりも、前記ノズルを遅く移動させる半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法において、
前記ノズルの移動方向において前記方向転換軌跡よりも上流に位置する前記直線軌跡は、前記方向転換軌跡に直接接続する接続軌跡と、前記接続軌跡が介在することで下流側の前記方向転換軌跡に直接接続しない非接続軌跡と、を含み、
前記接続軌跡では、前記非接続軌跡よりも、前記ノズルを速く移動させる半導体装置の製造方法。 - 請求項2に記載された半導体装置の製造方法において、
前記接続軌跡と前記方向転換軌跡では、前記ノズルを同じ速度で移動させる半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法において、
前記ノズルの移動方向において前記方向転換軌跡よりも上流に位置する前記直線軌跡は、前記方向転換軌跡に直接接続する接続軌跡と、前記接続軌跡が介在することで下流側の前記方向転換軌跡に直接接続しない非接続軌跡と、を含み、
前記非接続軌跡において、前記方向転換軌跡よりも前記ノズルを遅く移動させる半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006248324A JP4366611B2 (ja) | 2006-09-13 | 2006-09-13 | 半導体装置の製造方法 |
US11/854,597 US7687321B2 (en) | 2006-09-13 | 2007-09-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
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JP2006248324A JP4366611B2 (ja) | 2006-09-13 | 2006-09-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008071883A true JP2008071883A (ja) | 2008-03-27 |
JP4366611B2 JP4366611B2 (ja) | 2009-11-18 |
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JP2006248324A Expired - Fee Related JP4366611B2 (ja) | 2006-09-13 | 2006-09-13 | 半導体装置の製造方法 |
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US (1) | US7687321B2 (ja) |
JP (1) | JP4366611B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011018988A1 (ja) | 2009-08-11 | 2011-02-17 | 武蔵エンジニアリング株式会社 | 液体材料の塗布方法、塗布装置およびプログラム |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4971243B2 (ja) * | 2008-05-15 | 2012-07-11 | 新光電気工業株式会社 | 配線基板 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2637684B2 (ja) | 1993-09-29 | 1997-08-06 | 松下電器産業株式会社 | 半導体装置の封止方法 |
US6379484B2 (en) * | 1996-07-30 | 2002-04-30 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor package |
JPH1050769A (ja) | 1996-07-30 | 1998-02-20 | Toshiba Corp | 半導体パッケージの製造装置および製造方法 |
JP2006216720A (ja) * | 2005-02-02 | 2006-08-17 | Sharp Corp | 半導体装置及びその製造方法 |
-
2006
- 2006-09-13 JP JP2006248324A patent/JP4366611B2/ja not_active Expired - Fee Related
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- 2007-09-13 US US11/854,597 patent/US7687321B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011018988A1 (ja) | 2009-08-11 | 2011-02-17 | 武蔵エンジニアリング株式会社 | 液体材料の塗布方法、塗布装置およびプログラム |
KR20120054629A (ko) | 2009-08-11 | 2012-05-30 | 무사시 엔지니어링 가부시키가이샤 | 액체 재료의 도포 방법, 도포 장치 및 프로그램을 기억한 기억 매체 |
EP2466630A1 (en) * | 2009-08-11 | 2012-06-20 | Musashi Engineering, Inc. | Method for applying liquid material, application device and programme |
CN102714165A (zh) * | 2009-08-11 | 2012-10-03 | 武藏工业株式会社 | 液体材料的涂布方法、涂布装置以及程序 |
EP2466630A4 (en) * | 2009-08-11 | 2014-02-26 | Musashi Engineering Inc | PROCESS FOR APPLYING LIQUID MATERIAL, APPLYING DEVICE AND PROGRAM THEREFOR |
US8703601B2 (en) | 2009-08-11 | 2014-04-22 | Musashi Engineering, Inc. | Method for applying liquid material, application device and program |
CN102714165B (zh) * | 2009-08-11 | 2015-04-15 | 武藏工业株式会社 | 液体材料的涂布方法以及涂布装置 |
KR101700255B1 (ko) | 2009-08-11 | 2017-02-13 | 무사시 엔지니어링 가부시키가이샤 | 액체 재료의 도포 방법, 도포 장치 및 프로그램을 기억한 기억 매체 |
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Publication number | Publication date |
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US7687321B2 (en) | 2010-03-30 |
JP4366611B2 (ja) | 2009-11-18 |
US20080064146A1 (en) | 2008-03-13 |
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