JP2008016837A - 半導体素子のコンタクトプラグの製造方法 - Google Patents
半導体素子のコンタクトプラグの製造方法 Download PDFInfo
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- JP2008016837A JP2008016837A JP2007157324A JP2007157324A JP2008016837A JP 2008016837 A JP2008016837 A JP 2008016837A JP 2007157324 A JP2007157324 A JP 2007157324A JP 2007157324 A JP2007157324 A JP 2007157324A JP 2008016837 A JP2008016837 A JP 2008016837A
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- etching
- storage node
- amorphous carbon
- contact plug
- node contact
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 44
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000002955 isolation Methods 0.000 abstract description 18
- 238000009413 insulation Methods 0.000 abstract 3
- 239000011229 interlayer Substances 0.000 description 21
- 125000006850 spacer group Chemical group 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000001000 micrograph Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】ランディングプラグ23が形成された半導体基板21上に絶縁膜29Aを形成するステップと、絶縁膜29Aの所定領域上に非晶質カーボンハードマスク30Aを形成するステップと、ハードマスク30Aをエッチングバリアにして絶縁膜29Aをエッチングしてランディングプラグ23を露出させるストレージノードコンタクトホール33を形成するステップと、コンタクトホール33に導電物質を埋め込んでストレージノードコンタクトプラグを形成するステップとを含む。
【選択図】図2C
Description
22 第1の層間絶縁膜(ランディングプラグ分離膜)
23 ランディングプラグ
24 第2の層間絶縁膜
25 ビットラインコンタクト
26 ビットラインタングステン膜
27 ビットラインハードマスク
28 ビットラインスペーサ
29 第3の層間絶縁膜
30 非晶質カーボン膜
30A 非晶質カーボンハードマスク
31 SiON膜(反射防止膜)
32 フォトレジストパターン
33 ストレージノードコンタクトホール
34 ストレージノードコンタクトスペーサ
35 ストレージノードコンタクトプラグ
Claims (11)
- ランディングプラグが形成された半導体基板上に絶縁膜を形成するステップと、
前記絶縁膜の所定領域上に非晶質カーボンハードマスクを形成するステップと、
前記非晶質カーボンハードマスクをエッチングバリアとして用い、前記絶縁膜をエッチングして前記ランディングプラグを露出させるストレージノードコンタクトホールを形成するステップと、
前記ストレージノードコンタクトホールに導電物質を埋め込んでストレージノードコンタクトプラグを形成するステップと、
を含むことを特徴とする半導体素子のコンタクトプラグの製造方法。 - 前記絶縁膜のエッチングが、
1.99〜6.67Pa(15〜50mTorr)の範囲の圧力で、1000〜2000Wの範囲のパワーを印加して行われることを特徴とする請求項1に記載の半導体素子のコンタクトプラグの製造方法。 - 前記絶縁膜のエッチングが、
C4F8,C5F8,C4F6及びCH2F2からなるグループの中から選択されたいずれか1つのガスを用いて行われることを特徴とする請求項2に記載の半導体素子のコンタクトプラグの製造方法。 - C4F8,C5F8,C4F6及びCH2F2からなるグループの中から選択されたいずれか1つの前記ガスにAr/O2/CO/N2の混合ガスを添加することを特徴とする請求項3に記載の半導体素子のコンタクトプラグの製造方法。
- 前記ストレージノードコンタクトホールが、
下部の線幅に比べて上部の線幅が広い形状を有することを特徴とする請求項1に記載の半導体素子のコンタクトプラグの製造方法。 - 前記非晶質カーボンハードマスクを形成する前記ステップが、
前記絶縁膜上に非晶質カーボン膜を形成するステップと、
前記非晶質カーボン膜上にフォトレジストパターンを形成するステップと、
前記フォトレジストパターンをエッチングバリアにして前記非晶質カーボン膜をエッチングするステップと、
前記フォトレジストパターンを除去するステップと
を含むことを特徴とする請求項1に記載の半導体素子のコンタクトプラグの製造方法。 - 前記非晶質カーボン膜をエッチングする前記ステップが、
1.33〜26.67Pa(10〜200mTorr)の範囲の圧力で200〜2000Wの範囲のパワーを印加して行われることを特徴とする請求項6に記載の半導体素子のコンタクトプラグの製造方法。 - 前記非晶質カーボン膜をエッチングする前記ステップが、
CF4/CHF3の混合ガスを含むエッチングガスを用いることを特徴とする請求項7に記載の半導体素子のコンタクトプラグの製造方法。 - CF4/CHF3の混合ガスを含む前記エッチングガスが、
O2/N2/Arの混合ガスをさらに添加されていることを特徴とする請求項8に記載の半導体素子のコンタクトプラグの製造方法。 - 前記非晶質カーボン膜が、
1000〜2000Åの範囲の厚さに形成されることを特徴とする請求項6に記載の半導体素子のコンタクトプラグの製造方法。 - 前記非晶質カーボン膜をエッチングする前記ステップが、
前記非晶質カーボン膜のエッチングによって露出した前記絶縁膜を500〜1500Åの範囲の厚さだけさらにエッチングするステップをさらに含むことを特徴とする請求項6に記載の半導体素子のコンタクトプラグの製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060060291A KR100780596B1 (ko) | 2006-06-30 | 2006-06-30 | 반도체 소자의 콘택플러그 제조 방법 |
Publications (1)
Publication Number | Publication Date |
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JP2008016837A true JP2008016837A (ja) | 2008-01-24 |
Family
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Family Applications (1)
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JP2007157324A Ceased JP2008016837A (ja) | 2006-06-30 | 2007-06-14 | 半導体素子のコンタクトプラグの製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7745331B2 (ja) |
JP (1) | JP2008016837A (ja) |
KR (1) | KR100780596B1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009206394A (ja) * | 2008-02-29 | 2009-09-10 | Nippon Zeon Co Ltd | 炭素系ハードマスクの形成方法 |
JP2011142306A (ja) * | 2009-11-30 | 2011-07-21 | Soonwoo Cha | 相変化メモリのためのキーホールフリー傾斜ヒーター |
US9196609B2 (en) | 2013-09-18 | 2015-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
CN109326596A (zh) * | 2017-08-01 | 2019-02-12 | 联华电子股份有限公司 | 具有电容连接垫的半导体结构与电容连接垫的制作方法 |
CN112585728A (zh) * | 2018-08-22 | 2021-03-30 | 东京毅力科创株式会社 | 处理方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7718546B2 (en) * | 2007-06-27 | 2010-05-18 | Sandisk 3D Llc | Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon |
US9117769B2 (en) | 2009-08-27 | 2015-08-25 | Tokyo Electron Limited | Plasma etching method |
JP2011049360A (ja) * | 2009-08-27 | 2011-03-10 | Tokyo Electron Ltd | プラズマエッチング方法 |
US8227339B2 (en) * | 2009-11-02 | 2012-07-24 | International Business Machines Corporation | Creation of vias and trenches with different depths |
KR101752837B1 (ko) * | 2011-02-28 | 2017-07-03 | 삼성전자주식회사 | 반도체 기억 소자 및 반도체 기억 소자의 형성 방법 |
CN103219304A (zh) * | 2013-04-19 | 2013-07-24 | 昆山西钛微电子科技有限公司 | 半导体晶圆级封装结构及其制备方法 |
CN105336667B (zh) * | 2014-06-20 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | 一种半导体器件的制造方法 |
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-
2006
- 2006-06-30 KR KR1020060060291A patent/KR100780596B1/ko not_active IP Right Cessation
- 2006-12-27 US US11/646,062 patent/US7745331B2/en active Active
-
2007
- 2007-06-14 JP JP2007157324A patent/JP2008016837A/ja not_active Ceased
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JP2001308182A (ja) * | 2000-04-27 | 2001-11-02 | Nec Corp | Cr膜とのコンタクトの形成方法 |
JP2002076306A (ja) * | 2000-08-31 | 2002-03-15 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
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Cited By (10)
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JP2009206394A (ja) * | 2008-02-29 | 2009-09-10 | Nippon Zeon Co Ltd | 炭素系ハードマスクの形成方法 |
JP2011142306A (ja) * | 2009-11-30 | 2011-07-21 | Soonwoo Cha | 相変化メモリのためのキーホールフリー傾斜ヒーター |
US9196609B2 (en) | 2013-09-18 | 2015-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
CN109326596A (zh) * | 2017-08-01 | 2019-02-12 | 联华电子股份有限公司 | 具有电容连接垫的半导体结构与电容连接垫的制作方法 |
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CN112585728B (zh) * | 2018-08-22 | 2024-05-17 | 东京毅力科创株式会社 | 处理方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100780596B1 (ko) | 2007-11-29 |
US7745331B2 (en) | 2010-06-29 |
US20080003798A1 (en) | 2008-01-03 |
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