JP2008010729A - 実装基板 - Google Patents

実装基板 Download PDF

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Publication number
JP2008010729A
JP2008010729A JP2006181351A JP2006181351A JP2008010729A JP 2008010729 A JP2008010729 A JP 2008010729A JP 2006181351 A JP2006181351 A JP 2006181351A JP 2006181351 A JP2006181351 A JP 2006181351A JP 2008010729 A JP2008010729 A JP 2008010729A
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Japan
Prior art keywords
mounting
conductive material
layer
copper
wire bonding
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Granted
Application number
JP2006181351A
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English (en)
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JP5051421B2 (ja
Inventor
Hiroyuki Ogiwara
宏之 荻原
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Lincstech Circuit Co Ltd
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Hitachi AIC Inc
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Priority to JP2006181351A priority Critical patent/JP5051421B2/ja
Publication of JP2008010729A publication Critical patent/JP2008010729A/ja
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Publication of JP5051421B2 publication Critical patent/JP5051421B2/ja
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Abstract

【課題】 本発明は、フィルドビア直上領域をはんだボールを配置するだけの領域として用いることなく、より高密度な実装が行える実装基板を提供することを目的とする。
【解決手段】 一方を開放され、他方を閉塞された非貫通穴を有した基板と、上記非貫通穴内に充填される導電性物質と、この導電性物質にワイヤボンディングにより導通される半導体実装部品とを備えた実装基板。
【選択図】 図３

Description

本発明は、ＩＣ等の半導体実装部品を実装させる基板に関する。
近年、電子機器の小型化に伴い、内部の配線基板に対してもより小型とすることが求められ、実装密度を高める要求が多くなっている。そこで、図１に示すような配線板が多く使用されている。
配線板１は、内層配線６及び外層配線５を有した多層板であり、両側の外層配線同士を接続するスルーホール２、内層配線６と外層配線５とを接続するＩＶＨ４を設けている。スルーホール２の周壁には、導電性金属めっきが施され、ＩＶＨ４内には導電性金属を充填することでフィルドビア３としている。
また、フィルドビア３の直上には、他の配線板と接続させるはんだボール７を配置してあり、フィルドビア３の直上領域を用いることで、実装密度を上げている。
特開２００６−１３１８８
しかしながら、図１に示す配線板は、フィルドビア上の領域を使用しているものの、その使用方法が、はんだボールであり、接続対象が限定されてしまう。
本発明は、フィルドビア直上領域をはんだボールを配置するだけの領域として用いることなく、より高密度な実装が行える実装基板を提供することを目的とする。
本発明は、以下のものに関する。
（１）一方を開放され、他方を閉塞された非貫通穴を有した基板と、上記非貫通穴内に充填される導電性物質と、この導電性物質にワイヤボンディングにより導通される半導体実装部品とを備えた実装基板。
（２）項（１）において、導電性物質が銅めっきにより充填される実装基板。
（３）項（１）又は（２）において、導電性物質の表面が、すり鉢状である実装基板。
（４）項（３）において、導電性物質とワイヤボンディングとの接点が、すり鉢状の中心である実装基板。
（５）項（３）において、導電性物質とワイヤボンディングとの接点が、すり鉢状の傾斜部である実装基板。
（６）項（１）乃至（５）の何れかにおいて、半導体実装部品がＬＥＤである実装基板。
（７）項（１）乃至（６）の何れかにおいて、更に、導電性物質とワイヤボンディングとの接点の裏面にはんだボールを配した実装基板。
（８）項（１）乃至（７）の何れかにおいて、ワイヤ及び半導体実装部品をモールドした実装基板。
（９）項（１）乃至（８）の何れかにおいて、複数の実装部品にまたがってモールドした実装基板。
本発明では、フィルドビア上にワイヤボンディングを行うことにより、はんだボールのみを配置していた際に比べ、より高密度な実装を行うことができる。
フィルドビアを銅めっきにて行った場合は、ＩＶＨへの充填と共に、基板表面へも銅めっき層を同時に形成し、配線とすることができる。
フィルドビア表面をすり鉢状とした場合は、平面とした場合に比べ、表面積を大きくすることができ、ワイヤボンディング位置の選択部位が増え、外観から部位が特定しやすく性能試験を行いやすい。
導電性物質とワイヤボンディングとの接点をすり鉢状の中心とした場合は、中心部に平らな部分があるため、ワイヤボンディングを行い易い。
導電性物質とワイヤボンディングとの接点をすり鉢状の傾斜部とした場合は、接点とできる面積が大きくなり、接続信頼性が高くなる。
半導体実装部品をＬＥＤとした場合は、より高密度な実装が可能であることから、複数の半導体実装部品を実装でき、多色化、高輝度化できる。
導電性物質とワイヤボンディングとの接点の裏面にはんだボールを配した場合は、電送距離を短くすることができ、更に、実装基板を小さくすることができる。
ワイヤ及び半導体実装部品をモールドした場合は、ワイヤと半導体実装部品を確実に保護することができる。
複数の実装部品にまたがってモールドした場合は、ダイシングで切断した後の部品の大きさを小さくすることができる。
本発明にて述べる非貫通穴は、一方を開放され、他方を閉塞されていれば良く、特に限定されない。より具体的には、図２に示すように、導通部材である銅により形成される底と、周壁及び開放端を備えたものが好ましく、周壁は、めっきの付きまわり性が良好であるテーパ形状であることが好ましい。
非貫通穴の形成方法は、レーザー加工により行うことができ、先にドリルで孔あけしてから多層化することもできる。
本発明にて述べる導電性物質とは、電気的な導通が確保できるものであれば良く、材質としては、銅、すず、ニッケル、金、銀、鉄及びそれらの合金等を用いることができ、特に電気特性の良好な銅を用いることが好ましい。
非貫通穴への導電性物質の充填方法は、めっき、印刷、ポッティング等を適宜選択でき、特に、配線銅も同時に形成できるめっきにより行うことが好ましい。
導電性物質の表面形状は、特に限定されるものではないが、表面積を大きくするために、すり鉢状とすることが好ましい。
本発明にて述べる半導体実装部品とは、ＬＥＤ、ＩＣチップ、ＬＳＩチップ等を意味する。
本発明にて述べるワイヤボンディングとは、半導体実装部品と、導電性物質との間を電気的に接続可能なワイヤを用いたものであり、具体的な材質としては、金、アルミ、銅等を用いることができる。
導電性物質とワイヤとの接点は、図３（ａ）に示すように導電性物質表面の中央、図３（ｂ）に示すように実装部品を配置する側の端、図３（ｃ）に示すように実装部品を配置する側とは反対の端の何れでも良く、導電性物質表面の中央（ａ）では、平らな部分があるためワイヤボンディングを行い易く、実装部品側端（ｂ）では、ワイヤをも含めた部品実装面積を小さくすることができ、実装部品と反対側（ｃ）では、接点の面積を小さくでき、狭い面積であってもワイヤボンディングを行うことができる。
本発明にて述べるはんだボールとは、電気接続を行うものであり、その部位を特定するものではないが、図４に示すように、導電性物質と、ワイヤボンディングとの接点の裏面であることが好ましく、このように配置することで、伝送距離を短くすることができる。
本発明で述べるモールドとは、半導体実装部品とワイヤとを覆うものであり、具体的には、図５に示すように、半導体実装部品、ワイヤ、及び、ＩＶＨ内に充填された導電性物質を覆うことが好ましい。これは、半導体実装部品及びワイヤを外部環境および衝撃などから保護するためである。
モールドは、合成樹脂により行われ、ＬＥＤ等の発光素子の場合は、合成樹脂として、エポキシ樹脂、アクリル樹脂またはシリコン樹脂など、透明なものを使用する。
モールドは、複数の実装部品にまたがって行い、その後、ダイシングによって分割することで、実装基板の大きさを小さくすることができる。
以下、本発明の１実施例について、図面を用いて説明する。
図６に、本発明の１実施例である、実装基板の要部断面図を示す。実装基板１１は、下位より、はんだボール１２、第４層ソルダレジスト１３、第４層配線銅１４、第３層４層間絶縁層１５、第３層内層配線銅１６、コア基材１７、第２層内層配線銅１８、第１層２層間絶縁層１９、第１層配線銅２０、第１層ソルダレジスト２１、導電性ペースト２２、半導体実装部品２３及びモールド樹脂２４を積層しており、コア基板１７にブラインドビア２５を施し、更に、第１層２層間絶縁層１９及び第３層４層間絶縁層１５に非貫通穴２６を施し、この非貫通穴２６を導電性物質２７で埋め、半導体実装部品２３と導電性物質２７とを金ワイヤ２８でワイヤボンディングしたものである。
図６に示す実装基板の製造方法について、より詳細に説明する。まず、図７を用いて、本発明の実装基板の、前半の製造方法を説明する。
ＭＣＬ−Ｅ−６７９ＦＧ（日立化成工業株式会社製 商品名）の銅箔厚１８μｍ銅張板３０に、直径０．２５ｍｍドリルを用いて貫通孔３１を施し、電解銅めっきで約１０μｍの銅めっきを施してスルーホール３２を形成し、ＰＨＰ９００ＩＲ−１（山栄化学株式会社製 商品名）孔埋め樹脂３３を用いて、スルーホール３２を孔埋めし、１４０℃で４０分加熱して孔埋め樹脂３３を硬化させた。
次に、サブトラクティブ法により第２層内層配線銅１８および第３層内層配線銅１６をパターン形成し、コア基板３４を作製する。
ＧＥＡ−６７９ＦＧ（日立化成工業株式会社製 商品名）プリプレグ３５及び１８μｍＧＰ箔（日本電解株式会社製 商品名）銅箔３６を、コア基板３４の表裏両面に重ね、１８０℃、２ＭＰａの条件で１２０分間積層プレスを行い、多層板３７を得る。
サブトラクティブ法により非貫通穴２６形成部の銅をエッチングした後、炭酸ガスレーザーにより、第１層２層間絶縁層１９及び第３層４層間絶縁層１５に、非貫通穴２６を形成する。
無電解銅めっきで、多層板３７表面及び非貫通穴２６の底３８と周壁３９に、約５μｍの銅めっきを施し、後に電解銅めっきで約３０μｍの銅めっきを施すと共に、非貫通穴２６を銅めっきで充填し、フィルドビア４０得る。
サブトラクティブ法により、第１層配線銅２０及び第４層配線銅１４をパターン形成する。
ＰＳＲ４０００−ＡＵＳ３０３（太陽インキ製造株式会社製 商品名）ソルダレジストを約３０μｍロール塗布し、仮硬化、パターン露光及び現像を行い、第１層ソルダレジスト２１及び第４層ソルダレジスト１３を形成する。
第１層ソルダレジスト２１及び第４層ソルダレジスト１３から露出している、第１層配線銅２０及び第４層配線銅１４に、電解ニッケルめっき４１を５μｍ施し、後に、電解金めっき４２を０．３μｍ施し、配線板４３を得る。
続いて、図８を用いて、本発明の後半の製造方法について説明する。配線板４３の第１層配線銅２０の一部に、ユメックスＨ９６２９（ナミックス株式会社製 商品名）導電性接着剤４４を印刷塗布する。
導電性接着剤４４上に発光素子４５を実装し、後に導電性接着剤４４を１５０℃雰囲気中で約１時間加熱硬化させる。
発光素子４５とフィルドビア４０直上の電解金めっき４２を、田中貴金属工業株式会社製の直径２５μｍ金ワイヤ２８を用いてワイヤボンディングを行う。
フィルドビア４０、発光素子４５及び金ワイヤ２８を覆うように、ＮＴ−３０１Ｈ（日東電工株式会社製 商品名）透明封止剤４６を用いてモールドを行う。
配線板４３の第４層配線銅１４の一部に、デルタラックス５３３（千住金属工業株式会社製 商品名）フラックスを塗布し、直径０．２５エコソルダーボール（千住金属工業株式会社製 商品名）はんだボール１２を重ね、２４０℃、２０秒加熱する。
最後に、フィルドビア４０、発光素子４５及び金ワイヤ２８を切断しない位置で、ダイシングを行い、実装基板４７を得る。
本発明の従来例を示す、実装基板の一部断面図である 本発明における非貫通穴の実施例を示す概略断面図である。 本発明における導電性物質とワイヤとの接点位置を示すものであり、（ａ）は中央接点、（ｂ）は離れた端部接点、（ｃ）は近い端部接点である。 本発明におけるはんだボール配置の位置を示す概略断面図である。 本発明におけるモールドの状態を示す概略断面図である。 本発明の１実施形態を示す、実装基板の断面図である。 図６に示す実装基板の前半製造法を示す概略断面図である。 図６に示す実装基板の後半製造法を示す概略断面図である。
符号の説明
１…配線板、２…スルーホール、３…フィルドビア、４…ＩＶＨ、５…外層配線、６…内層配線、７…はんだボール、
１１…実装基板、１２…はんだボール、１３…第４層ソルダレジスト、１４…第４層配線銅、１５…第３層４層間絶縁層、１６…第３層内層配線銅、１７…コア基材、１８…第２層内層配線銅、１９…第１層２層間絶縁層、２０…第１層配線銅、２１…第１層ソルダレジスト、２２…導電性ペースト、２３…半導体実装部品、２４…モールド樹脂、２５…ブラインドビア、２６…非貫通穴、２７…導電性物質、２８…金ワイヤ、
３０…銅張板、３１…貫通孔、３２…スルーホール、３３…孔埋め樹脂、３４…コア基板、３５…プリプレグ、３６…銅箔、３７…多層板、３８…底、３９…周壁、４０…フィルドビア、４１…電解ニッケルめっき、４２…電解金めっき、４３…配線板、４４…導電性接着剤、４５…発光素子、４６…透明封止剤、４７…実装基板。



Claims (9)

  1. 一方を開放され、他方を閉塞された非貫通穴を有した基板と、上記非貫通穴内に充填される導電性物質と、この導電性物質にワイヤボンディングにより導通される半導体実装部品とを備えた実装基板。
  2. 請求項１において、導電性物質が銅めっきにより充填される実装基板。
  3. 請求項１又は２において、導電性物質の表面が、すり鉢状である実装基板。
  4. 請求項３において、導電性物質とワイヤボンディングとの接点が、すり鉢状の中心である実装基板。
  5. 請求項３において、導電性物質とワイヤボンディングとの接点が、すり鉢状の傾斜部である実装基板。
  6. 請求項１乃至５の何れかにおいて、半導体実装部品がＬＥＤである実装基板。
  7. 請求項１乃至６の何れかにおいて、更に、導電性物質とワイヤボンディングとの接点の裏面にはんだボールを配した実装基板。
  8. 請求項１乃至７の何れかにおいて、ワイヤ及び半導体実装部品をモールドした実装基板。
  9. 請求項１乃至８の何れかにおいて、複数の実装部品にまたがってモールドした実装基板。



JP2006181351A 2006-06-30 2006-06-30 実装基板 Expired - Fee Related JP5051421B2 (ja)

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151737U (ja) * 1984-09-07 1986-04-07
JPH03142940A (ja) * 1989-10-30 1991-06-18 Toshiba Corp ワイヤボンディング方法
JPH09162348A (ja) * 1995-12-12 1997-06-20 Fujitsu Ltd 半導体装置及びその製造方法及びリードフレーム及びその製造方法
JPH10189637A (ja) * 1996-12-25 1998-07-21 Hitachi Ltd 半導体装置
JPH1167838A (ja) * 1997-08-22 1999-03-09 Matsushita Electric Ind Co Ltd バンプ付電子部品の製造方法
JPH11163217A (ja) * 1997-09-08 1999-06-18 Shinko Electric Ind Co Ltd 半導体装置
JP2000223618A (ja) * 1999-02-01 2000-08-11 Fujitsu Ltd 半導体装置
JP2001102484A (ja) * 1999-10-01 2001-04-13 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法並びにキャリア基板及びその製造方法
JP2002176070A (ja) * 2000-12-07 2002-06-21 Sanyo Electric Co Ltd 半導体装置
JP2003133372A (ja) * 2001-10-26 2003-05-09 Toppan Printing Co Ltd 配線回路基板
JP2004006465A (ja) * 2002-05-31 2004-01-08 Renesas Technology Corp 半導体装置の製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151737U (ja) * 1984-09-07 1986-04-07
JPH03142940A (ja) * 1989-10-30 1991-06-18 Toshiba Corp ワイヤボンディング方法
JPH09162348A (ja) * 1995-12-12 1997-06-20 Fujitsu Ltd 半導体装置及びその製造方法及びリードフレーム及びその製造方法
JPH10189637A (ja) * 1996-12-25 1998-07-21 Hitachi Ltd 半導体装置
JPH1167838A (ja) * 1997-08-22 1999-03-09 Matsushita Electric Ind Co Ltd バンプ付電子部品の製造方法
JPH11163217A (ja) * 1997-09-08 1999-06-18 Shinko Electric Ind Co Ltd 半導体装置
JP2000223618A (ja) * 1999-02-01 2000-08-11 Fujitsu Ltd 半導体装置
JP2001102484A (ja) * 1999-10-01 2001-04-13 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法並びにキャリア基板及びその製造方法
JP2002176070A (ja) * 2000-12-07 2002-06-21 Sanyo Electric Co Ltd 半導体装置
JP2003133372A (ja) * 2001-10-26 2003-05-09 Toppan Printing Co Ltd 配線回路基板
JP2004006465A (ja) * 2002-05-31 2004-01-08 Renesas Technology Corp 半導体装置の製造方法

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