JP5051421B2 - 実装基板 - Google Patents
実装基板 Download PDFInfo
- Publication number
- JP5051421B2 JP5051421B2 JP2006181351A JP2006181351A JP5051421B2 JP 5051421 B2 JP5051421 B2 JP 5051421B2 JP 2006181351 A JP2006181351 A JP 2006181351A JP 2006181351 A JP2006181351 A JP 2006181351A JP 5051421 B2 JP5051421 B2 JP 5051421B2
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- JP
- Japan
- Prior art keywords
- mounting
- conductive material
- hole
- layer
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
また、フィルドビア3の直上には、他の配線板と接続させるはんだボール7を配置してあり、フィルドビア3の直上領域を用いることで、実装密度を上げている。
(1)一方を開放され、他方を導通部材に閉塞された非貫通穴を有した基板と、上記基板表面の配線銅となる導電性物質と一体的に形成され、上記非貫通穴内に銅めっきにより充填される導電性物質と、上記非貫通穴内に銅めっきにより充填される導電性物質にワイヤボンディングにより導通される半導体実装部品とを備え、上記非貫通穴内に銅めっきにより充填された導電性物質の表面が、すり鉢状である実装基板。
(2)項(1)において、導電性物質とワイヤボンディングとの接点が、すり鉢状の中心である実装基板。
(3)項(1)において、導電性物質とワイヤボンディングとの接点が、すり鉢状の傾斜部である実装基板。
(4)項(1)乃至(3)の何れかにおいて、半導体実装部品がLEDである実装基板。
(5)項(1)乃至(4)の何れかにおいて、更に、導電性物質とワイヤボンディングとの接点の裏面にはんだボールを配した実装基板。
(6)項(1)乃至(5)の何れかにおいて、ワイヤ及び半導体実装部品をモールドした実装基板。
(7)項(1)乃至(6)の何れかにおいて、複数の実装部品にまたがってモールドした実装基板。
図6に、本発明の1実施例である、実装基板の要部断面図を示す。実装基板11は、下位より、はんだボール12、第4層ソルダレジスト13、第4層配線銅14、第3層4層間絶縁層15、第3層内層配線銅16、コア基材17、第2層内層配線銅18、第1層2層間絶縁層19、第1層配線銅20、第1層ソルダレジスト21、導電性ペースト22、半導体実装部品23及びモールド樹脂24を積層しており、コア基板17にブラインドビア25を施し、更に、第1層2層間絶縁層19及び第3層4層間絶縁層15に非貫通穴26を施し、この非貫通穴26を導電性物質27で埋め、半導体実装部品23と導電性物質27とを金ワイヤ28でワイヤボンディングしたものである。
MCL−E−679FG(日立化成工業株式会社製 商品名)の銅箔厚18μm銅張板30に、直径0.25mmドリルを用いて貫通孔31を施し、電解銅めっきで約10μmの銅めっきを施してスルーホール32を形成し、PHP900IR−1(山栄化学株式会社製 商品名)孔埋め樹脂33を用いて、スルーホール32を孔埋めし、140℃で40分加熱して孔埋め樹脂33を硬化させた。
11…実装基板、12…はんだボール、13…第4層ソルダレジスト、14…第4層配線銅、15…第3層4層間絶縁層、16…第3層内層配線銅、17…コア基材、18…第2層内層配線銅、19…第1層2層間絶縁層、20…第1層配線銅、21…第1層ソルダレジスト、22…導電性ペースト、23…半導体実装部品、24…モールド樹脂、25…ブラインドビア、26…非貫通穴、27…導電性物質、28…金ワイヤ、
30…銅張板、31…貫通孔、32…スルーホール、33…孔埋め樹脂、34…コア基板、35…プリプレグ、36…銅箔、37…多層板、38…底、39…周壁、40…フィルドビア、41…電解ニッケルめっき、42…電解金めっき、43…配線板、44…導電性接着剤、45…発光素子、46…透明封止剤、47…実装基板。
Claims (7)
- 一方を開放され、他方を導通部材に閉塞された非貫通穴を有した基板と、上記基板表面の配線銅となる導電性物質と一体的に形成され、上記非貫通穴内に銅めっきにより充填される導電性物質と、上記非貫通穴内に銅めっきにより充填される導電性物質にワイヤボンディングにより導通される半導体実装部品とを備え、上記非貫通穴内に銅めっきにより充填された導電性物質の表面が、すり鉢状である実装基板。
- 請求項1において、導電性物質とワイヤボンディングとの接点が、すり鉢状の中心である実装基板。
- 請求項1において、導電性物質とワイヤボンディングとの接点が、すり鉢状の傾斜部である実装基板。
- 請求項1乃至3の何れかにおいて、半導体実装部品がLEDである実装基板。
- 請求項1乃至4の何れかにおいて、更に、導電性物質とワイヤボンディングとの接点の裏面にはんだボールを配した実装基板。
- 請求項1乃至5の何れかにおいて、ワイヤ及び半導体実装部品をモールドした実装基板。
- 請求項1乃至6の何れかにおいて、複数の実装部品にまたがってモールドした実装基板。
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JP2006181351A JP5051421B2 (ja) | 2006-06-30 | 2006-06-30 | 実装基板 |
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JP2006181351A JP5051421B2 (ja) | 2006-06-30 | 2006-06-30 | 実装基板 |
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JP2008010729A JP2008010729A (ja) | 2008-01-17 |
JP5051421B2 true JP5051421B2 (ja) | 2012-10-17 |
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Family Cites Families (11)
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JPS6151737U (ja) * | 1984-09-07 | 1986-04-07 | ||
JPH03142940A (ja) * | 1989-10-30 | 1991-06-18 | Toshiba Corp | ワイヤボンディング方法 |
JP3007833B2 (ja) * | 1995-12-12 | 2000-02-07 | 富士通株式会社 | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 |
JPH10189637A (ja) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | 半導体装置 |
JPH1167838A (ja) * | 1997-08-22 | 1999-03-09 | Matsushita Electric Ind Co Ltd | バンプ付電子部品の製造方法 |
JPH11163217A (ja) * | 1997-09-08 | 1999-06-18 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2000223618A (ja) * | 1999-02-01 | 2000-08-11 | Fujitsu Ltd | 半導体装置 |
JP3691993B2 (ja) * | 1999-10-01 | 2005-09-07 | 新光電気工業株式会社 | 半導体装置及びその製造方法並びにキャリア基板及びその製造方法 |
JP2002176070A (ja) * | 2000-12-07 | 2002-06-21 | Sanyo Electric Co Ltd | 半導体装置 |
JP2003133372A (ja) * | 2001-10-26 | 2003-05-09 | Toppan Printing Co Ltd | 配線回路基板 |
JP2004006465A (ja) * | 2002-05-31 | 2004-01-08 | Renesas Technology Corp | 半導体装置の製造方法 |
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