JP2007527112A5 - - Google Patents

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Publication number
JP2007527112A5
JP2007527112A5 JP2006544148A JP2006544148A JP2007527112A5 JP 2007527112 A5 JP2007527112 A5 JP 2007527112A5 JP 2006544148 A JP2006544148 A JP 2006544148A JP 2006544148 A JP2006544148 A JP 2006544148A JP 2007527112 A5 JP2007527112 A5 JP 2007527112A5
Authority
JP
Japan
Prior art keywords
pad
layer
operatively connected
runner
discrete power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006544148A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007527112A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2004/044097 external-priority patent/WO2005062998A2/en
Publication of JP2007527112A publication Critical patent/JP2007527112A/ja
Publication of JP2007527112A5 publication Critical patent/JP2007527112A5/ja
Pending legal-status Critical Current

Links

JP2006544148A 2003-12-12 2004-12-11 直接的なダイの取付けのための金属相互接続システムおよび方法 Pending JP2007527112A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US52916603P 2003-12-12 2003-12-12
US54470204P 2004-02-12 2004-02-12
PCT/US2004/044097 WO2005062998A2 (en) 2003-12-12 2004-12-11 Metal interconnect system and method for direct die attachment

Publications (2)

Publication Number Publication Date
JP2007527112A JP2007527112A (ja) 2007-09-20
JP2007527112A5 true JP2007527112A5 (enExample) 2007-11-08

Family

ID=34704266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006544148A Pending JP2007527112A (ja) 2003-12-12 2004-12-11 直接的なダイの取付けのための金属相互接続システムおよび方法

Country Status (3)

Country Link
US (1) US20080296690A1 (enExample)
JP (1) JP2007527112A (enExample)
WO (2) WO2005059957A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070257375A1 (en) * 2006-05-02 2007-11-08 Roland James P Increased interconnect density electronic package and method of fabrication
DE102006050087A1 (de) 2006-10-24 2008-04-30 Austriamicrosystems Ag Halbleiterkörper und Verfahren zum Entwurf eines Halbleiterkörpers mit einer Anschlussleitung
US8400784B2 (en) 2009-08-10 2013-03-19 Silergy Technology Flip chip package for monolithic switching regulator
US8344504B2 (en) 2010-07-29 2013-01-01 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar and moisture barrier
US8314472B2 (en) 2010-07-29 2012-11-20 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar
US8536707B2 (en) 2011-11-29 2013-09-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor structure comprising moisture barrier and conductive redistribution layer
TWI869690B (zh) * 2022-07-08 2025-01-11 聯華電子股份有限公司 銅柱凸塊結構及其製作方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02118931A (ja) * 1988-10-27 1990-05-07 Seiko Epson Corp 光ディスクスタンパ検査装置
EP1918991B1 (en) * 1996-08-27 2017-04-05 Nippon Steel & Sumitomo Metal Corporation Semiconductor device provided with low melting point metal bumps
US6507070B1 (en) * 1996-11-25 2003-01-14 Semiconductor Components Industries Llc Semiconductor device and method of making
FR2759493B1 (fr) * 1997-02-12 2001-01-26 Motorola Semiconducteurs Dispositif de puissance a semiconducteur
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
JP3638085B2 (ja) * 1998-08-17 2005-04-13 富士通株式会社 半導体装置
US6130141A (en) * 1998-10-14 2000-10-10 Lucent Technologies Inc. Flip chip metallization
US6261944B1 (en) * 1998-11-24 2001-07-17 Vantis Corporation Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
JP5156155B2 (ja) * 1999-10-13 2013-03-06 アプライド マテリアルズ インコーポレイテッド 半導体集積回路を製造する方法
US6620720B1 (en) * 2000-04-10 2003-09-16 Agere Systems Inc Interconnections to copper IC's
WO2002007312A2 (en) * 2000-07-13 2002-01-24 Isothermal Systems Research, Inc. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
US6717241B1 (en) * 2000-08-31 2004-04-06 Micron Technology, Inc. Magnetic shielding for integrated circuits
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
JP4972842B2 (ja) * 2001-05-11 2012-07-11 富士電機株式会社 半導体装置
US6618846B2 (en) * 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
US6630715B2 (en) * 2001-10-01 2003-10-07 International Business Machines Corporation Asymmetrical MOSFET layout for high currents and high speed operation
US6674157B2 (en) * 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
US6617655B1 (en) * 2002-04-05 2003-09-09 Fairchild Semiconductor Corporation MOSFET device with multiple gate contacts offset from gate contact area and over source area
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
US6972464B2 (en) * 2002-10-08 2005-12-06 Great Wall Semiconductor Corporation Power MOSFET
TWI244184B (en) * 2002-11-12 2005-11-21 Siliconware Precision Industries Co Ltd Semiconductor device with under bump metallurgy and method for fabricating the same
US6897561B2 (en) * 2003-06-06 2005-05-24 Semiconductor Components Industries, Llc Semiconductor power device having a diamond shaped metal interconnect scheme
WO2005057626A2 (en) * 2003-12-04 2005-06-23 Great Wall Semiconductor Corporation System and method to reduce metal series resistance of bumped chip

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