JP2007518269A5 - - Google Patents

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Publication number
JP2007518269A5
JP2007518269A5 JP2006549303A JP2006549303A JP2007518269A5 JP 2007518269 A5 JP2007518269 A5 JP 2007518269A5 JP 2006549303 A JP2006549303 A JP 2006549303A JP 2006549303 A JP2006549303 A JP 2006549303A JP 2007518269 A5 JP2007518269 A5 JP 2007518269A5
Authority
JP
Japan
Prior art keywords
metal layer
disposed
semiconductor structure
pad area
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006549303A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007518269A (ja
Filing date
Publication date
Priority claimed from US10/758,148 external-priority patent/US20050151265A1/en
Application filed filed Critical
Publication of JP2007518269A publication Critical patent/JP2007518269A/ja
Publication of JP2007518269A5 publication Critical patent/JP2007518269A5/ja
Pending legal-status Critical Current

Links

JP2006549303A 2004-01-14 2004-12-17 パッド下に素子を備える手法によるウェハの有効利用 Pending JP2007518269A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/758,148 US20050151265A1 (en) 2004-01-14 2004-01-14 Efficient use of wafer area with device under the pad approach
PCT/US2004/042879 WO2005071749A1 (en) 2004-01-14 2004-12-17 Efficient use of wafer area with device under the pad approach

Publications (2)

Publication Number Publication Date
JP2007518269A JP2007518269A (ja) 2007-07-05
JP2007518269A5 true JP2007518269A5 (https=) 2007-10-11

Family

ID=34740122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006549303A Pending JP2007518269A (ja) 2004-01-14 2004-12-17 パッド下に素子を備える手法によるウェハの有効利用

Country Status (7)

Country Link
US (1) US20050151265A1 (https=)
EP (1) EP1709685A1 (https=)
JP (1) JP2007518269A (https=)
KR (1) KR20060130105A (https=)
CN (1) CN1910752A (https=)
TW (1) TW200529370A (https=)
WO (1) WO2005071749A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115321B2 (en) * 2009-04-30 2012-02-14 Lsi Corporation Separate probe and bond regions of an integrated circuit
CN103390647A (zh) * 2012-05-10 2013-11-13 无锡华润上华半导体有限公司 一种功率mos器件结构
CN110491849B (zh) * 2019-07-18 2024-11-08 珠海零边界集成电路有限公司 芯片、输入输出结构和垫层

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63166273A (ja) * 1986-12-27 1988-07-09 Tdk Corp 縦形半導体装置
JPH06275794A (ja) * 1993-03-18 1994-09-30 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
EP0637840A1 (en) 1993-08-05 1995-02-08 AT&T Corp. Integrated circuit with active devices under bond pads
US7067442B1 (en) * 1995-12-26 2006-06-27 Micron Technology, Inc. Method to avoid threshold voltage shift in thicker dielectric films
JP3157715B2 (ja) * 1996-05-30 2001-04-16 山形日本電気株式会社 半導体集積回路
JPH10335627A (ja) * 1997-05-27 1998-12-18 Sony Corp 固体撮像装置
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
TW445616B (en) 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
JP3505433B2 (ja) 1999-05-21 2004-03-08 三洋電機株式会社 半導体装置
US7199039B2 (en) * 2003-05-19 2007-04-03 Intel Corporation Interconnect routing over semiconductor for editing through the back side of an integrated circuit
JP4492926B2 (ja) * 2003-11-28 2010-06-30 ルネサスエレクトロニクス株式会社 半導体装置

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