JP2007514310A - 可塑的に変形可能な不可逆的ストレージ媒体と、このような一媒体を製造する方法 - Google Patents
可塑的に変形可能な不可逆的ストレージ媒体と、このような一媒体を製造する方法 Download PDFInfo
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- JP2007514310A JP2007514310A JP2006543577A JP2006543577A JP2007514310A JP 2007514310 A JP2007514310 A JP 2007514310A JP 2006543577 A JP2006543577 A JP 2006543577A JP 2006543577 A JP2006543577 A JP 2006543577A JP 2007514310 A JP2007514310 A JP 2007514310A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000002427 irreversible effect Effects 0.000 title claims abstract description 17
- 238000003860 storage Methods 0.000 title claims description 36
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 230000015654 memory Effects 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 1
- 239000011888 foil Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Adornments (AREA)
- Pens And Brushes (AREA)
- Mechanical Pencils And Projecting And Retracting Systems Therefor, And Multi-System Writing Instruments (AREA)
Abstract
Description
Claims (7)
- メモリ・セル(3)のアレイを備える不可逆的ストレージ媒体であって、各メモリ・セル(3)が、第1の導体(1)と第2の導体(2)との間に配列されたアクティブ層(8)の1つのゾーン(10)を備え、前記メモリ・セル(3)に記憶されるバイナリ情報が、対応する前記ゾーン(10)の導電状態によって決定されるストレージ媒体を製造するための方法であって、
初期の絶縁状態にあるアクティブ層(8)を有するブランク・ストレージ媒体のアセンブリと、
記憶されるべき前記情報に対応するスタンピング・パターンを有するスタンピング・ダイ(17)の製造と、
前記スタンピング・ダイ(17)を使用して、局在化された可塑性変形(4)により、前記アクティブ層(8)の所定のゾーン(10)を導電性にする、前記ストレージ媒体のスタンピングと、
を備えることを特徴とする方法。 - 前記アクティブ層(8)が、帯電されたレジンによって形成されることを特徴とする、請求項1に記載の方法。
- ブランク・ストレージ媒体のアセンブリが、逐次的に、
基板(5)上への第1の導電層(11)と、2層の逆導電形にドーピングされた半導体層(6,7)との堆積と、
前記第1の導電層(11)と、前記2層の半導体層(6,7)とによって形成されたスタックをエッチングして、並列な複数のストリップ(13)の第1のアレイを取得することと、
並列な複数のストリップ(13)の前記第1のアレイの前記複数のストリップ(13)間のスペースを充てんして、並列な複数のストリップ(13)の前記第1のアレイの前記複数のストリップ(13)との共通な平面をもたらすことと、
前記共通な平面上への前記アクティブ層(8)の堆積と、
前記アクティブ層(8)上への第2の導電層の堆積と、
前記第2の導電層をエッチングして、複数のストリップ(13)の前記第1のアレイの前記複数のストリップ(13)に対して直角をなす並列な複数のストリップの第2のアレイを取得することと、
並列な複数のストリップの前記第2のアレイの前記複数のストリップの間のスペースを充てんすることと、
を含むことを特徴とする、請求項1および2の一項に記載の方法。 - 並列な複数のストリップの前記第1のアレイおよび/または第2のアレイの複数のストリップの間のスペースが、平坦化レジン(12,9)を使用した技法により充てんされることを特徴とする、請求項3に記載の方法。
- 並列な複数のストリップの前記第1のアレイおよび/または第2のアレイの複数のストリップの間のスペースが、機械的化学研磨ステップにより充てんされることを特徴とする、請求項3に記載の方法。
- 前記スタンピング・ダイ(17)の製造が、逐次的に、
仲介基板(15)上へのフォトレジスト(14)の堆積と、
前記フォトレジスト(14)中における、前記スタンピング・パターンに対応する構成を有する複数の基本ゾーン(16)のアレイのエッチングと、
前記仲介基板(15)および前記フォトレジスト(14)上への、前記スタンピング・ダイ(17)を構成する金属の電解析出と、
前記仲介基板(15)からの前記スタンピング・ダイ(17)の剥離と、
前記スタンピング・ダイ(17)からのフォトレジスト(14)の残留物の除去と、
を含むことを特徴とする、請求項1乃至5のいずれか一項に記載の方法。 - 請求項1乃至6のいずれか一項に記載の方法により取得されることを特徴とする不可逆的ストレージ媒体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0314625A FR2863767B1 (fr) | 2003-12-12 | 2003-12-12 | Support memoire irreversible a deformation plastique et procede de realisation d'un tel support |
PCT/FR2004/003091 WO2005067050A1 (fr) | 2003-12-12 | 2004-12-02 | Support memoire irreversible à deformation plastique et procede de realisation d’un tel support |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007514310A true JP2007514310A (ja) | 2007-05-31 |
JP4499112B2 JP4499112B2 (ja) | 2010-07-07 |
Family
ID=34610633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006543577A Expired - Fee Related JP4499112B2 (ja) | 2003-12-12 | 2004-12-02 | 可塑的に変形可能な不可逆的ストレージ媒体と、このような一媒体を製造する方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7279418B2 (ja) |
EP (1) | EP1692723B1 (ja) |
JP (1) | JP4499112B2 (ja) |
AT (1) | ATE472825T1 (ja) |
DE (1) | DE602004027942D1 (ja) |
FR (1) | FR2863767B1 (ja) |
WO (1) | WO2005067050A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2880177B1 (fr) * | 2004-12-23 | 2007-05-18 | Commissariat Energie Atomique | Memoire pmc ayant un temps de retention et une vitesse d'ecriture ameliores |
FR2922368A1 (fr) * | 2007-10-16 | 2009-04-17 | Commissariat Energie Atomique | Procede de fabrication d'une memoire cbram ayant une fiabilite amelioree |
FR2968451B1 (fr) * | 2010-12-03 | 2013-04-12 | Commissariat Energie Atomique | Polymere comprenant localement des zones conductrices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59106147A (ja) * | 1982-12-10 | 1984-06-19 | Sanyo Electric Co Ltd | マスクrom |
JPH0442570A (ja) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | 半導体装置 |
JPH0582757A (ja) * | 1991-02-19 | 1993-04-02 | Mitsubishi Electric Corp | マスクromおよびその製造方法 |
JPH06334139A (ja) * | 1993-05-18 | 1994-12-02 | Sony Corp | 読出し専用メモリとその製造方法 |
JPH08330355A (ja) * | 1995-03-24 | 1996-12-13 | Shinko Electric Ind Co Ltd | 半導体装置 |
WO2000049652A1 (fr) * | 1999-02-18 | 2000-08-24 | Seiko Epson Corporation | Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4396998A (en) * | 1980-08-27 | 1983-08-02 | Mobay Chemical Corporation | Thermally reprogrammable memory array and a thermally reprogrammable memory cell therefor |
KR960010736B1 (ko) * | 1991-02-19 | 1996-08-07 | 미쓰비시뎅끼 가부시끼가이샤 | 마스크 rom 및 그 제조방법 |
KR100218996B1 (ko) | 1995-03-24 | 1999-09-01 | 모기 쥰이찌 | 반도체장치 |
JP3463777B2 (ja) | 1995-09-28 | 2003-11-05 | 日鉱金属株式会社 | 電気音響変換器用リードフレーム材及び電気音響変換器 |
KR100274333B1 (ko) * | 1996-01-19 | 2001-01-15 | 모기 쥰이찌 | 도체층부착 이방성 도전시트 및 이를 사용한 배선기판 |
NO972803D0 (no) * | 1997-06-17 | 1997-06-17 | Opticom As | Elektrisk adresserbar logisk innretning, fremgangsmåte til elektrisk adressering av samme og anvendelse av innretning og fremgangsmåte |
US6351406B1 (en) | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
JP2002100689A (ja) * | 2000-09-22 | 2002-04-05 | Toshiba Corp | 不揮発性半導体記憶装置 |
-
2003
- 2003-12-12 FR FR0314625A patent/FR2863767B1/fr not_active Expired - Fee Related
-
2004
- 2004-12-02 EP EP04805611A patent/EP1692723B1/fr not_active Not-in-force
- 2004-12-02 US US10/579,623 patent/US7279418B2/en not_active Expired - Fee Related
- 2004-12-02 DE DE602004027942T patent/DE602004027942D1/de active Active
- 2004-12-02 JP JP2006543577A patent/JP4499112B2/ja not_active Expired - Fee Related
- 2004-12-02 AT AT04805611T patent/ATE472825T1/de not_active IP Right Cessation
- 2004-12-02 WO PCT/FR2004/003091 patent/WO2005067050A1/fr active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59106147A (ja) * | 1982-12-10 | 1984-06-19 | Sanyo Electric Co Ltd | マスクrom |
JPH0442570A (ja) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | 半導体装置 |
JPH0582757A (ja) * | 1991-02-19 | 1993-04-02 | Mitsubishi Electric Corp | マスクromおよびその製造方法 |
JPH06334139A (ja) * | 1993-05-18 | 1994-12-02 | Sony Corp | 読出し専用メモリとその製造方法 |
JPH08330355A (ja) * | 1995-03-24 | 1996-12-13 | Shinko Electric Ind Co Ltd | 半導体装置 |
WO2000049652A1 (fr) * | 1999-02-18 | 2000-08-24 | Seiko Epson Corporation | Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique |
Also Published As
Publication number | Publication date |
---|---|
WO2005067050A1 (fr) | 2005-07-21 |
JP4499112B2 (ja) | 2010-07-07 |
EP1692723B1 (fr) | 2010-06-30 |
US20070072384A1 (en) | 2007-03-29 |
ATE472825T1 (de) | 2010-07-15 |
EP1692723A1 (fr) | 2006-08-23 |
FR2863767B1 (fr) | 2006-06-09 |
US7279418B2 (en) | 2007-10-09 |
DE602004027942D1 (de) | 2010-08-12 |
FR2863767A1 (fr) | 2005-06-17 |
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