JP2007514185A5 - - Google Patents
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- Publication number
- JP2007514185A5 JP2007514185A5 JP2006539748A JP2006539748A JP2007514185A5 JP 2007514185 A5 JP2007514185 A5 JP 2007514185A5 JP 2006539748 A JP2006539748 A JP 2006539748A JP 2006539748 A JP2006539748 A JP 2006539748A JP 2007514185 A5 JP2007514185 A5 JP 2007514185A5
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- substrate
- printing
- predetermined
- providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 1
Claims (3)
- 基板上にパターンを作製する方法であって：
(a)前記基板上に第1のパターンをプリントする工程；及び、
(b)前記第1のパターンに対して所定の方法で意図的にずらされている第2の実質的に同様なパターンをプリントする工程であり、前記第1及び第2のパターンの組み合わせにより前記基板上に画成された要素の最終的なサイズが連続的、系統的かつ所定の変動を有し、前記画成された少なくとも2つの要素がそれぞれ異なるサイズを有するように、前記変動が所定のずれと一致しているようなパターンプリント工程；
を有する方法。 - 請求項1に記載の方法であって、
工程(b)はイメージセンサに使用される構造の素子の提供を有することを特徴とする方法。 - 請求項2に記載の方法であって、
工程(b)はアパーチャとしての前記素子の提供を有することを特徴とする方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/706,200 US6870168B1 (en) | 2003-11-12 | 2003-11-12 | Varying feature size in resist across the chip without the artifact of “grid-snapping” from the mask writing tool |
| PCT/US2004/037354 WO2005047976A2 (en) | 2003-11-12 | 2004-11-09 | Varying feature size in resist |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007514185A JP2007514185A (ja) | 2007-05-31 |
| JP2007514185A5 true JP2007514185A5 (ja) | 2007-11-29 |
Family
ID=34274830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006539748A Pending JP2007514185A (ja) | 2003-11-12 | 2004-11-09 | レジスト内でのパーツのサイズ変動 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6870168B1 (ja) |
| EP (1) | EP1682941B1 (ja) |
| JP (1) | JP2007514185A (ja) |
| DE (1) | DE602004014013D1 (ja) |
| WO (1) | WO2005047976A2 (ja) |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538105A (en) * | 1981-12-07 | 1985-08-27 | The Perkin-Elmer Corporation | Overlay test wafer |
| JPS61102738A (ja) * | 1984-10-26 | 1986-05-21 | Fujitsu Ltd | レジスト膜パタ−ンの形成方法 |
| JPH01258419A (ja) * | 1988-04-08 | 1989-10-16 | Hitachi Ltd | パターン形成方法 |
| US5103101A (en) | 1991-03-04 | 1992-04-07 | Etec Systems, Inc. | Multiphase printing for E-beam lithography |
| US5773836A (en) | 1996-10-28 | 1998-06-30 | International Business Machines Corporation | Method for correcting placement errors in a lithography system |
| US5905020A (en) | 1996-12-20 | 1999-05-18 | Intel Corporation | Method and apparatus for reducing the critical dimension difference of features printed on a substrate |
| JP2000114156A (ja) * | 1998-10-09 | 2000-04-21 | Toshiba Corp | 露光装置および露光方法 |
| JP2000133563A (ja) * | 1998-10-22 | 2000-05-12 | Nikon Corp | 露光方法及び露光装置 |
| US6278123B1 (en) | 1999-04-07 | 2001-08-21 | Intel Corporation | Reducing the critical dimension difference of features printed on a substrate |
| JP3635979B2 (ja) * | 1999-04-09 | 2005-04-06 | セイコーエプソン株式会社 | 照明光学系および投写型表示装置 |
| US6335151B1 (en) * | 1999-06-18 | 2002-01-01 | International Business Machines Corporation | Micro-surface fabrication process |
| US6331711B1 (en) | 1999-08-06 | 2001-12-18 | Etec Systems, Inc. | Correction for systematic, low spatial frequency critical dimension variations in lithography |
| US6322934B1 (en) * | 1999-09-30 | 2001-11-27 | Lucent Technologies Inc. | Method for making integrated circuits including features with a relatively small critical dimension |
| US7084905B1 (en) * | 2000-02-23 | 2006-08-01 | The Trustees Of Columbia University In The City Of New York | Method and apparatus for obtaining high dynamic range images |
| US20020045105A1 (en) * | 2000-07-05 | 2002-04-18 | Brown David R. | High quality lithographic processing |
| US6813046B1 (en) * | 2000-11-07 | 2004-11-02 | Eastman Kodak Company | Method and apparatus for exposure control for a sparsely sampled extended dynamic range image sensing device |
| TWI237849B (en) * | 2001-11-19 | 2005-08-11 | Nanya Technology Corp | Method of utilizing multi-exposure to form isolated lines |
-
2003
- 2003-11-12 US US10/706,200 patent/US6870168B1/en not_active Expired - Lifetime
-
2004
- 2004-11-09 WO PCT/US2004/037354 patent/WO2005047976A2/en active Application Filing
- 2004-11-09 JP JP2006539748A patent/JP2007514185A/ja active Pending
- 2004-11-09 EP EP04810605A patent/EP1682941B1/en active Active
- 2004-11-09 DE DE602004014013T patent/DE602004014013D1/de active Active
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