JP2007510308A - 二重ゲートトランジスタ半導体製造プロセス用の限定スペーサ - Google Patents

二重ゲートトランジスタ半導体製造プロセス用の限定スペーサ Download PDF

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Publication number
JP2007510308A
JP2007510308A JP2006538154A JP2006538154A JP2007510308A JP 2007510308 A JP2007510308 A JP 2007510308A JP 2006538154 A JP2006538154 A JP 2006538154A JP 2006538154 A JP2006538154 A JP 2006538154A JP 2007510308 A JP2007510308 A JP 2007510308A
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Japan
Prior art keywords
gate electrode
forming
capping layer
silicon
dielectric
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JP2006538154A
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English (en)
Japanese (ja)
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JP2007510308A5 (enExample
Inventor
マシュー、レオ
アール． モーラ、ロード
グエン、ビック−エン
エー． スティーブンズ、タブ
エム． ヴァンドーレン、アン
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007510308A publication Critical patent/JP2007510308A/ja
Publication of JP2007510308A5 publication Critical patent/JP2007510308A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2006538154A 2003-10-28 2004-10-20 二重ゲートトランジスタ半導体製造プロセス用の限定スペーサ Pending JP2007510308A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/695,163 US6951783B2 (en) 2003-10-28 2003-10-28 Confined spacers for double gate transistor semiconductor fabrication process
PCT/US2004/035349 WO2005045892A2 (en) 2003-10-28 2004-10-20 Confined spacers for double gate transistor semiconductor fabrication process

Publications (2)

Publication Number Publication Date
JP2007510308A true JP2007510308A (ja) 2007-04-19
JP2007510308A5 JP2007510308A5 (enExample) 2007-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006538154A Pending JP2007510308A (ja) 2003-10-28 2004-10-20 二重ゲートトランジスタ半導体製造プロセス用の限定スペーサ

Country Status (6)

Country Link
US (1) US6951783B2 (enExample)
EP (1) EP1683186A4 (enExample)
JP (1) JP2007510308A (enExample)
CN (1) CN1875456A (enExample)
TW (1) TWI350000B (enExample)
WO (1) WO2005045892A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013046065A (ja) * 2011-08-19 2013-03-04 Altera Corp バッファ付きフィンｆｅｔデバイス
US10062779B2 (en) 2015-05-22 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

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US7354831B2 (en) * 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
US7341902B2 (en) * 2006-04-21 2008-03-11 International Business Machines Corporation Finfet/trigate stress-memorization method
US7442590B2 (en) * 2006-04-27 2008-10-28 Freescale Semiconductor, Inc Method for forming a semiconductor device having a fin and structure thereof
US20070257322A1 (en) * 2006-05-08 2007-11-08 Freescale Semiconductor, Inc. Hybrid Transistor Structure and a Method for Making the Same
EP1863072A1 (en) * 2006-05-29 2007-12-05 Interuniversitair Microelektronica Centrum ( Imec) Method for modulating the effective work function
EP1863097A1 (en) * 2006-05-29 2007-12-05 Interuniversitair Microelektronica Centrum ( Imec) Method for modulating the effective work function
US20080029827A1 (en) * 2006-08-04 2008-02-07 Ibrahim Ban Double gate transistor, method of manufacturing same, and system containing same
US7691690B2 (en) * 2007-01-12 2010-04-06 International Business Machines Corporation Methods for forming dual fully silicided gates over fins of FinFet devices
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8258035B2 (en) * 2007-05-04 2012-09-04 Freescale Semiconductor, Inc. Method to improve source/drain parasitics in vertical devices
US7476578B1 (en) 2007-07-12 2009-01-13 International Business Machines Corporation Process for finFET spacer formation
US8174055B2 (en) 2010-02-17 2012-05-08 Globalfoundries Inc. Formation of FinFET gate spacer
US8835261B2 (en) 2011-03-14 2014-09-16 International Business Machines Corporation Field effect transistor structure and method of forming same
US9548213B2 (en) 2014-02-25 2017-01-17 International Business Machines Corporation Dielectric isolated fin with improved fin profile
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US9558950B1 (en) 2015-08-19 2017-01-31 International Business Machines Corporation Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy
US9472649B1 (en) 2015-12-09 2016-10-18 The United States Of America As Represented By The Secretary Of The Air Force Fabrication method for multi-zoned and short channel thin film transistors

Citations (4)

* Cited by examiner, † Cited by third party
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JP2002110963A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2003528448A (ja) * 2000-03-13 2003-09-24 インフィネオン テクノロジーズ アクチェンゲゼルシャフト フィン電界効果トランジスタおよびフィン電界効果トランジスタを作製する方法
JP2003298051A (ja) * 2002-01-30 2003-10-17 Soko Lee ダブルゲートｆｅｔ素子及びその製造方法

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US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
CN1320641C (zh) * 2002-12-19 2007-06-06 国际商业机器公司 形成隔离层的方法和鳍片场效应晶体管

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2003528448A (ja) * 2000-03-13 2003-09-24 インフィネオン テクノロジーズ アクチェンゲゼルシャフト フィン電界効果トランジスタおよびフィン電界効果トランジスタを作製する方法
JP2002110963A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2003298051A (ja) * 2002-01-30 2003-10-17 Soko Lee ダブルゲートｆｅｔ素子及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013046065A (ja) * 2011-08-19 2013-03-04 Altera Corp バッファ付きフィンｆｅｔデバイス
US10062779B2 (en) 2015-05-22 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TWI350000B (en) 2011-10-01
WO2005045892A9 (en) 2006-06-22
EP1683186A2 (en) 2006-07-26
WO2005045892A3 (en) 2005-09-15
US20050101069A1 (en) 2005-05-12
TW200524160A (en) 2005-07-16
CN1875456A (zh) 2006-12-06
US6951783B2 (en) 2005-10-04
WO2005045892A2 (en) 2005-05-19
EP1683186A4 (en) 2010-09-22

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