CN1875456A - 用于双栅极晶体管半导体制造方法的限制性间隔件 - Google Patents

用于双栅极晶体管半导体制造方法的限制性间隔件 Download PDF

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Publication number
CN1875456A
CN1875456A CNA2004800317887A CN200480031788A CN1875456A CN 1875456 A CN1875456 A CN 1875456A CN A2004800317887 A CNA2004800317887 A CN A2004800317887A CN 200480031788 A CN200480031788 A CN 200480031788A CN 1875456 A CN1875456 A CN 1875456A
Authority
CN
China
Prior art keywords
fin
gate electrode
cap layer
dielectric
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800317887A
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English (en)
Chinese (zh)
Inventor
雷奥·马修
罗德·R·莫拉
比奇-延·源
塔博·A·斯蒂芬斯
安妮·M·万多恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1875456A publication Critical patent/CN1875456A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
CNA2004800317887A 2003-10-28 2004-10-20 用于双栅极晶体管半导体制造方法的限制性间隔件 Pending CN1875456A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/695,163 US6951783B2 (en) 2003-10-28 2003-10-28 Confined spacers for double gate transistor semiconductor fabrication process
US10/695,163 2003-10-28

Publications (1)

Publication Number Publication Date
CN1875456A true CN1875456A (zh) 2006-12-06

Family

ID=34549969

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800317887A Pending CN1875456A (zh) 2003-10-28 2004-10-20 用于双栅极晶体管半导体制造方法的限制性间隔件

Country Status (6)

Country Link
US (1) US6951783B2 (enExample)
EP (1) EP1683186A4 (enExample)
JP (1) JP2007510308A (enExample)
CN (1) CN1875456A (enExample)
TW (1) TWI350000B (enExample)
WO (1) WO2005045892A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956692A (zh) * 2011-08-19 2013-03-06 阿尔特拉公司 缓冲型finFET器件

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US7354831B2 (en) * 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
US7341902B2 (en) * 2006-04-21 2008-03-11 International Business Machines Corporation Finfet/trigate stress-memorization method
US7442590B2 (en) * 2006-04-27 2008-10-28 Freescale Semiconductor, Inc Method for forming a semiconductor device having a fin and structure thereof
US20070257322A1 (en) * 2006-05-08 2007-11-08 Freescale Semiconductor, Inc. Hybrid Transistor Structure and a Method for Making the Same
EP1863072A1 (en) * 2006-05-29 2007-12-05 Interuniversitair Microelektronica Centrum ( Imec) Method for modulating the effective work function
EP1863097A1 (en) * 2006-05-29 2007-12-05 Interuniversitair Microelektronica Centrum ( Imec) Method for modulating the effective work function
US20080029827A1 (en) * 2006-08-04 2008-02-07 Ibrahim Ban Double gate transistor, method of manufacturing same, and system containing same
US7691690B2 (en) * 2007-01-12 2010-04-06 International Business Machines Corporation Methods for forming dual fully silicided gates over fins of FinFet devices
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8258035B2 (en) * 2007-05-04 2012-09-04 Freescale Semiconductor, Inc. Method to improve source/drain parasitics in vertical devices
US7476578B1 (en) 2007-07-12 2009-01-13 International Business Machines Corporation Process for finFET spacer formation
US8174055B2 (en) 2010-02-17 2012-05-08 Globalfoundries Inc. Formation of FinFET gate spacer
US8835261B2 (en) 2011-03-14 2014-09-16 International Business Machines Corporation Field effect transistor structure and method of forming same
US9548213B2 (en) 2014-02-25 2017-01-17 International Business Machines Corporation Dielectric isolated fin with improved fin profile
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US10062779B2 (en) 2015-05-22 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US9558950B1 (en) 2015-08-19 2017-01-31 International Business Machines Corporation Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy
US9472649B1 (en) 2015-12-09 2016-10-18 The United States Of America As Represented By The Secretary Of The Air Force Fabrication method for multi-zoned and short channel thin film transistors

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US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
DE10012112C2 (de) * 2000-03-13 2002-01-10 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
KR100458288B1 (ko) * 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
CN1320641C (zh) * 2002-12-19 2007-06-06 国际商业机器公司 形成隔离层的方法和鳍片场效应晶体管

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956692A (zh) * 2011-08-19 2013-03-06 阿尔特拉公司 缓冲型finFET器件
CN102956692B (zh) * 2011-08-19 2016-12-21 阿尔特拉公司 缓冲型finFET器件

Also Published As

Publication number Publication date
JP2007510308A (ja) 2007-04-19
TWI350000B (en) 2011-10-01
WO2005045892A9 (en) 2006-06-22
EP1683186A2 (en) 2006-07-26
WO2005045892A3 (en) 2005-09-15
US20050101069A1 (en) 2005-05-12
TW200524160A (en) 2005-07-16
US6951783B2 (en) 2005-10-04
WO2005045892A2 (en) 2005-05-19
EP1683186A4 (en) 2010-09-22

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