JP2007295132A - データ発生装置 - Google Patents
データ発生装置 Download PDFInfo
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- JP2007295132A JP2007295132A JP2006118524A JP2006118524A JP2007295132A JP 2007295132 A JP2007295132 A JP 2007295132A JP 2006118524 A JP2006118524 A JP 2006118524A JP 2006118524 A JP2006118524 A JP 2006118524A JP 2007295132 A JP2007295132 A JP 2007295132A
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- data
- clock
- trigger signal
- parallel
- parallel data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Abstract
【解決手段】メモリ54は、分周クロックD_CLKに従って並列データを供給する。アドレス・カウンタ52は、トリガ信号が到着するまでは同じアドレスをメモリ54供給し、トリガ信号が到着するとアドレスを進める。16進カウンタ62は、分周クロックよりも高速なクロックCLKをカウントし、分周クロックの周期毎にカウント値が循環する。トリガ情報ラッチ64は、トリガ信号を受けたときのカウンタ62のカウント値をラッチし、MUX58に供給する。MUX58は、ラッチ・カウント値に応じて、第1及び第2入力端子第1及び第2入力端子I1及びI2に入力された合計32ビットの並列データから、選択的に16ビットの並列データを生成する。並直列変換回路60は、MUX58からの組み替え並列データをクロックCLKに従って直列データに変換する。
【選択図】図6
Description
52 アドレス・カウンタ
54 メモリ
56 ラッチ
58 マルチプレクサ
60 並直列変換回路
62 16進カウンタ
64 トリガ情報ラッチ
Claims (3)
- 第1クロックに従って並列データを供給する記憶手段と、
上記記憶手段にアドレスを供給するアドレス供給手段と、
上記第1クロックよりも高速な第2クロックをカウントし、上記第1クロックの周期毎にカウント値が循環するカウンタ手段と、
トリガ信号を受けたときの上記カウンタ手段のカウント値を保持するラッチ手段と、
上記第1クロックに従って連続して読み出された上記並列データから上記カウント値に応じてデータを組み替えた組み替え並列データを生成するデータ組み替え手段と、
上記組み替え並列データを並直列変換する並直列変換手段とを具えるデータ発生装置。 - 上記トリガ信号を受ける前においては、上記アドレス供給手段が同じアドレスを上記記憶手段に供給することを特徴とする請求項1記載のデータ発生装置。
- 第1クロックに従って記憶手段から並列データを読み出す機能と、
トリガ信号を受けるまで同じアドレスを上記記憶手段に供給し、上記トリガ信号を受けると上記アドレスを進めるアドレス供給機能と、
上記第1クロックよりも高速な第2クロックをカウントし、上記第1クロックの周期毎にカウント値が循環するカウンタ機能と、
上記トリガ信号を受けたときの上記カウント値を保持するラッチ機能と、
上記第1クロックに従って連続して読み出された上記並列データから上記カウント値に応じてデータを組み替えた組み替え並列データを生成するデータ組み替え機能と、
上記組み替え並列データを並直列変換する並直列変換機能とを具えるデータ発生装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006118524A JP4192229B2 (ja) | 2006-04-21 | 2006-04-21 | データ発生装置 |
US11/738,485 US7436725B2 (en) | 2006-04-21 | 2007-04-21 | Data generator having stable duration from trigger arrival to data output start |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006118524A JP4192229B2 (ja) | 2006-04-21 | 2006-04-21 | データ発生装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007295132A true JP2007295132A (ja) | 2007-11-08 |
JP4192229B2 JP4192229B2 (ja) | 2008-12-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006118524A Active JP4192229B2 (ja) | 2006-04-21 | 2006-04-21 | データ発生装置 |
Country Status (2)
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US (1) | US7436725B2 (ja) |
JP (1) | JP4192229B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7436725B2 (en) * | 2006-04-21 | 2008-10-14 | Tektronix International Sales Gmbh | Data generator having stable duration from trigger arrival to data output start |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4474532B2 (ja) * | 2007-12-27 | 2010-06-09 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | 信号発生システム |
DE102015202505A1 (de) * | 2014-12-04 | 2016-06-09 | Rohde & Schwarz Gmbh & Co. Kg | Funktionsgenerator zum Bereitstellen elektrischer Signale |
CN113285695B (zh) * | 2021-07-26 | 2021-10-29 | 浙江芯昇电子技术有限公司 | 一种高频时钟调相电路及其实现方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60233741A (ja) * | 1984-05-07 | 1985-11-20 | Sony Tektronix Corp | デジタル・パタ−ン発生器 |
JP4192228B2 (ja) * | 2005-02-24 | 2008-12-10 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | データ発生装置 |
JP4192229B2 (ja) * | 2006-04-21 | 2008-12-10 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | データ発生装置 |
-
2006
- 2006-04-21 JP JP2006118524A patent/JP4192229B2/ja active Active
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2007
- 2007-04-21 US US11/738,485 patent/US7436725B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7436725B2 (en) * | 2006-04-21 | 2008-10-14 | Tektronix International Sales Gmbh | Data generator having stable duration from trigger arrival to data output start |
Also Published As
Publication number | Publication date |
---|---|
JP4192229B2 (ja) | 2008-12-10 |
US20070247927A1 (en) | 2007-10-25 |
US7436725B2 (en) | 2008-10-14 |
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