JP2007128950A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP2007128950A JP2007128950A JP2005318143A JP2005318143A JP2007128950A JP 2007128950 A JP2007128950 A JP 2007128950A JP 2005318143 A JP2005318143 A JP 2005318143A JP 2005318143 A JP2005318143 A JP 2005318143A JP 2007128950 A JP2007128950 A JP 2007128950A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
Abstract
【解決手段】 第1の配線群81の各配線は、BL方向に比較的短く延びて形成されており、各半導体素子のそれぞれに含まれるMOS84のゲート電極85を挟んだ各一方の電極に接続されている。第2の配線群82の各配線は、WL方向に延びた配線を分割したような位置関係で形成されており、各半導体装置のそれぞれに対応して順に設けられている。第2の配線群82の各配線には、第1の配線群81に含まれる配線のうち対応する各半導体素子に接続されたものが接続されている。第3の配線群83の各配線はBL方向に延びており、第2の配線群82の異なる配線にそれぞれ接続されている。
【選択図】図10
Description
20;大区画アレイ領域、21;周辺回路領域、23;中区画アレイ領域、
24;X−DEC領域、25;Y−DEC領域、26;デコーダ・クロス領域、
31;MAT領域、32;S.A.領域、33;SWD領域、34;クロス領域、
41〜48;第1〜第8の素子レイアウト領域、51;BLEQ、52;SHR、
53;Y−Switch、54;NchS.A.、55;PchS.A.、
56;SHR、57;BLEQ、61;CS−Driv.(OD)、62;CS−EQ、
63;CS−Driv.(Restore)、64;LI/O−EQ、
65;CS−Driv.(GND)、70;SWD−Driv.(0〜m)、
71;I/O−Switch、72;S.A.−ActDriv.、
73;BLEQ−Driv.、74;SHR−Driv.、75;FX−Driv.、
76;BLEQ−Driv.、77;SHR−Driv.、78;FX−Driv.、
81〜83;第1〜第3の配線群、84;MOS、85;ゲート電極、86;分割配線、
91;第1のMOS、92;第2のMOS、93;第3のMOS、
109〜113;第9〜第13の素子レイアウト領域、
114;第14の素子レイアウト領域、115;第15の素子レイアウト領域。
Claims (8)
- メモリ・アレイ領域及び回路領域を有する半導体素子層と配線層とを備える半導体記憶装置であって、
前記メモリ・アレイ領域は、互いに直交する第1の方向及び第2の方向により規定される面内に設けられ、
前記回路領域は、前記メモリ・アレイ領域に対して前記第1の方向に設けられており、前記第2の方向に並ぶ異機能の半導体素子をもつ第1の素子レイアウト領域と、前記第2の方向に並ぶ同機能の半導体素子をもつ第2の素子レイアウト領域とを含み、
前記配線層は、前記第1の素子レイアウト領域に設けられた半導体素子に電位を与え前記第1の方向に延びた電位供給線を有する、
半導体記憶装置。 - 前記第1の素子レイアウト領域は、第1の半導体素子と第2の半導体素子とをもち、
前記電位供給線は、第1の電位供給線と第2の電位供給線とをもち、
前記配線層は、前記第1の半導体素子と前記第1の電位供給線との間に接続されて前記第2の方向に延びた第1の分割配線と、前記第2の半導体素子と前記第2の電位供給線との間に接続されて前記第2の方向に延びた第2の分割配線とを有する、請求項1の半導体記憶装置。 - 前記第1の分割配線と前記第2の分割配線とは、同一直線上において前記第2の方向に並んで形成されている、請求項2の半導体記憶装置。
- 前記配線層は、前記第1の半導体素子と前記第1の分割配線との間に接続されて前記第1の方向に延びた第1の配線と、第2の半導体素子と前記第2の分割配線との間に接続されて前記第1の方向に延びた第2の配線とを有する、請求項3の半導体記憶装置。
- 前記配線層は、前記第1の配線及び前記第2の配線を含む第1の配線層と、前記第1の分割配線及び前記第2の分割配線を含む第2の配線層と、前記電位供給線を含む第3の配線層とを有する、請求項4の半導体記憶装置。
- 前記第2の方向に延びる第5の配線と、
前記第2の方向に延びる第6の配線とを備え、
前記第1の半導体素子は、前記第3の配線と前記第5の配線との間の接続をスイッチングするトランジスタを含み、
前記第2の半導体素子は、前記第4の配線と前記第6の配線との間の接続をスイッチングするトランジスタを含む、請求項1から請求項5のいずれかの半導体記憶装置。 - 前記第5の配線は、前記第2の素子レイアウト領域がもつ複数の半導体素子に接続され、前記第6の配線は、他の前記第2の素子レイアウト領域がもつ複数の半導体素子に接続されている、請求項1から請求項6のいずれかの半導体記憶装置。
- 前記回路領域は、センス・アンプ領域、サブ・ワード領域、Xデコーダ領域、又は、Yデコーダ領域である請求項1から請求項7のいずれかの半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005318143A JP4874627B2 (ja) | 2005-11-01 | 2005-11-01 | 半導体記憶装置 |
US11/588,328 US7414874B2 (en) | 2005-11-01 | 2006-10-27 | Semiconductor memory device |
CNB2006101428623A CN100541660C (zh) | 2005-11-01 | 2006-10-30 | 半导体存储器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005318143A JP4874627B2 (ja) | 2005-11-01 | 2005-11-01 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007128950A true JP2007128950A (ja) | 2007-05-24 |
JP4874627B2 JP4874627B2 (ja) | 2012-02-15 |
Family
ID=37995102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005318143A Expired - Fee Related JP4874627B2 (ja) | 2005-11-01 | 2005-11-01 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7414874B2 (ja) |
JP (1) | JP4874627B2 (ja) |
CN (1) | CN100541660C (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20100042072A (ko) * | 2008-10-15 | 2010-04-23 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR102660229B1 (ko) * | 2016-12-14 | 2024-04-25 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 서브 워드라인 드라이버 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000058785A (ja) * | 1998-08-07 | 2000-02-25 | Hitachi Ltd | ダイナミック型ram |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6314042B1 (en) * | 1998-05-22 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Fast accessible semiconductor memory device |
JP2000243085A (ja) | 1999-02-22 | 2000-09-08 | Hitachi Ltd | 半導体装置 |
US6535415B2 (en) | 1999-02-22 | 2003-03-18 | Hitachi, Ltd. | Semiconductor device |
JP2001084791A (ja) * | 1999-07-12 | 2001-03-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4149170B2 (ja) * | 2002-01-22 | 2008-09-10 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP2005101466A (ja) * | 2003-09-26 | 2005-04-14 | Renesas Technology Corp | 半導体記憶装置 |
-
2005
- 2005-11-01 JP JP2005318143A patent/JP4874627B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-27 US US11/588,328 patent/US7414874B2/en active Active
- 2006-10-30 CN CNB2006101428623A patent/CN100541660C/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000058785A (ja) * | 1998-08-07 | 2000-02-25 | Hitachi Ltd | ダイナミック型ram |
Also Published As
Publication number | Publication date |
---|---|
JP4874627B2 (ja) | 2012-02-15 |
US7414874B2 (en) | 2008-08-19 |
CN100541660C (zh) | 2009-09-16 |
CN1959844A (zh) | 2007-05-09 |
US20070096156A1 (en) | 2007-05-03 |
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