JP2007088238A - 半導体装置の製造方法およびシリコン窒化膜またはシリコン酸化膜の表面処理方法 - Google Patents
半導体装置の製造方法およびシリコン窒化膜またはシリコン酸化膜の表面処理方法 Download PDFInfo
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- JP2007088238A JP2007088238A JP2005275594A JP2005275594A JP2007088238A JP 2007088238 A JP2007088238 A JP 2007088238A JP 2005275594 A JP2005275594 A JP 2005275594A JP 2005275594 A JP2005275594 A JP 2005275594A JP 2007088238 A JP2007088238 A JP 2007088238A
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- film
- silicon oxide
- silicon nitride
- etching
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 title description 5
- 229920001296 polysiloxane Polymers 0.000 title 2
- 238000005530 etching Methods 0.000 claims abstract description 97
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 87
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 72
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 72
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 71
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 44
- 238000001039 wet etching Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 84
- 239000002184 metal Substances 0.000 claims description 84
- 238000005121 nitriding Methods 0.000 claims description 18
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 9
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- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000004381 surface treatment Methods 0.000 claims description 4
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- -1 NH 3 Chemical compound 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910003855 HfAlO Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- HCSAHSWQCOXVDM-UHFFFAOYSA-N [SiH3][SiH3].[Cl].[Cl].[Cl].[Cl].[Cl].[Cl] Chemical compound [SiH3][SiH3].[Cl].[Cl].[Cl].[Cl].[Cl].[Cl] HCSAHSWQCOXVDM-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910021472 group 8 element Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 150000002829 nitrogen Chemical class 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
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- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Abstract
【解決手段】半導体基板にエッチング対象膜を形成する工程と、エッチング対象膜の上にシリコン窒化膜またはシリコン酸化膜を形成する工程と、シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程と、シリコン窒化膜またはシリコン酸化膜を選択的にエッチング除去してエッチングマスクとする工程と、シリコン酸化膜またはシリコン酸化膜のエッチング残渣をウェットエッチングにより除去する工程と、エッチングマスクを介してエッチング対象膜をウェットエッチングする工程と、エッチングマスクを除去する工程とを有する。
【選択図】なし
Description
Samavedam et al., IEDM Tech. Digest, p.443, 2002
まず、本発明の第1実施形態について説明する。
図1〜12は、本発明の第1実施形態に係る方法を説明するための工程断面図である。まず、図1に示すように、シリコンを主体とする半導体基板201中に素子分離領域202およびn型ウェル203およびp型ウェル204を形成する。
次に、本発明の第2実施形態について説明する。
図15〜図26は、本発明の第2実施形態に係る方法を説明するための工程断面図である。まず、図15に示すように、シリコンを主体とする半導体基板301中に素子分離領域302及びn型ウェル303及びp型ウェル304、シリコン酸化膜305を形成する。
202;素子分離領域
203;n型ウェル
204;p型ウェル
205;ゲート絶縁膜
206;p型MISFETのゲート電極を構成する金属膜
207;エッチングマスク材
207′;エッチングマスク
207″;残渣
208;レジストマスク
209;n型MISFETのゲート電極を構成する金属膜
210;ゲート電極の抵抗を低減するための金属膜
211;キャップ膜
212;レジストパターン
213;p型MISFETのゲート電極
214;n型MISFETのゲート電極
215;p型MISFETのエクステンション
216;n型MISFETのエクステンション
217;ゲート側壁
218;p型MISFETのソース・ドレイン
219;n型MISFETのソース・ドレイン
301;半導体基板
302;素子分離領域
303;n型ウェル
304;p型ウェル
305;シリコン酸化膜
306;ダミーゲート電極
307;ゲート側壁
308;p型MISFETのエクステンション
309;p型MISFETのソース/ドレイン
310;n型MISFETのエクステンション
311;n型MISFETのソース/ドレイン
312;シリコン窒化膜
313;層間絶縁膜
314;溝
315;ゲート絶縁膜
316;p型MISFETのゲート電極を構成する金属膜
317;エッチングマスク材
317′;エッチングマスク
317″;残渣
318;レジストマスク
319;n型MISFETのゲート電極を構成する金属膜
320;ゲート電極の抵抗を低減するための金属膜
Claims (7)
- 半導体基板にエッチング対象膜を形成する工程と、
前記エッチング対象膜の上にシリコン窒化膜またはシリコン酸化膜を形成する工程と、
前記シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程と、
前記シリコン窒化膜またはシリコン酸化膜を選択的にエッチング除去してエッチングマスクとする工程と、
前記シリコン窒化膜またはシリコン酸化膜のエッチング残渣をウェットエッチングにより除去する工程と、
前記エッチングマスクを介してエッチング対象膜をウェットエッチングする工程と、
前記エッチングマスクを除去する工程とを有することを特徴とする半導体装置の製造方法。 - 半導体基板中に素子分離領域と第1導電型の領域と第2導電型の領域を形成する工程と、
前記半導体基板全面にゲート絶縁膜を堆積する工程と、
基板の全面に第1の金属膜を形成する工程と、
基板の全面にシリコン窒化膜またはシリコン酸化膜を堆積する工程と、
シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程と、
前記第1導電型領域のゲート電極を形成する領域を被覆するように前記シリコン窒化膜またはシリコン酸化膜からなる領域を形成する工程と、
前記第2の導電型領域に残存した前記シリコン窒化膜またはシリコン酸化膜をウェットエッチングにより除去する工程と、
前記シリコン窒化膜またはシリコン酸化膜からなる領域外に露出した第1の金属膜をウェットエッチングで除去し、ゲート絶縁膜を露出させる工程と、
前記第1導電型領域のゲート電極を形成する領域を被覆するように形成した前記シリコン窒化膜またはシリコン酸化膜からなる領域を除去する工程と、
第1の金属膜表面およびゲート絶縁膜を被覆して基板全面に第2の金属膜を形成する工程と、
第1の金属膜と第2の金属膜と第3の金属膜とをパターニングし、ゲート電極を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - シリコン窒化膜またはシリコン酸化膜は、HCD(Hexa Chloro Disilane)をシリコン原料として堆積したものであることを特徴とする、請求項1または請求項2に記載の半導体装置の製造方法。
- シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程はプラズマ窒化により行うことを特徴とする、請求項1から請求項3のいずれか1項に記載の半導体装置の製造方法。
- シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程はイオン注入により行うことを特徴とする、請求項1から請求項3のいずれか1項に記載の半導体装置の製造方法。
- シリコン窒化膜またはシリコン酸化膜の表面に窒素を導入する工程は窒素を含む気体中での加熱処理により行うことを特徴とする、請求項1から請求項3のいずれか1項に記載の半導体装置の製造方法。
- シリコン窒化膜またはシリコン酸化膜の表面をプラズマ窒化処理して表面に窒素を導入し、表面でウェットエッチングレートが低く、内部で高いエッチングレートに傾斜をもったシリコン窒化膜またはシリコン酸化膜の表面処理方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010573A (ja) * | 2008-06-30 | 2010-01-14 | Hitachi High-Technologies Corp | 半導体加工方法 |
JP2017504205A (ja) * | 2013-12-31 | 2017-02-02 | 日本テキサス・インスツルメンツ株式会社 | TiNゲートを備えた高k/金属ゲートCMOSトランジスタ |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090267349A1 (en) | 2008-04-23 | 2009-10-29 | Spitzauer Michael P | Production Processes, Systems, Methods, and Apparatuses |
US8058119B2 (en) | 2008-08-27 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device scheme of HKMG gate-last process |
US7927943B2 (en) * | 2008-09-12 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for tuning a work function of high-k metal gate devices |
US8980706B2 (en) * | 2008-09-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double treatment on hard mask for gate N/P patterning |
US7871915B2 (en) * | 2008-09-26 | 2011-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming metal gates in a gate last process |
US8222132B2 (en) * | 2008-11-14 | 2012-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabricating high-K/metal gate devices in a gate last process |
JP5329294B2 (ja) * | 2009-04-30 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20110042728A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | Semiconductor device with enhanced stress by gates stress liner |
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JP5660205B2 (ja) * | 2011-04-25 | 2015-01-28 | 東京エレクトロン株式会社 | 成膜方法 |
FR2979166A1 (fr) * | 2011-08-16 | 2013-02-22 | St Microelectronics Crolles 2 | Procede de fabrication d'un transistor mos |
US8772114B2 (en) * | 2012-03-30 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate semiconductor device and method of fabricating thereof |
US9385044B2 (en) * | 2012-12-31 | 2016-07-05 | Texas Instruments Incorporated | Replacement gate process |
CN104217954A (zh) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003068701A (ja) * | 2001-08-08 | 2003-03-07 | Huabang Electronic Co Ltd | 窒化ケイ素のウェットエッチング率を減少させる方法 |
JP2003100868A (ja) * | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2005142539A (ja) * | 2003-10-17 | 2005-06-02 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2007035740A (ja) * | 2005-07-25 | 2007-02-08 | Tokyo Electron Ltd | 成膜方法、成膜装置及び記憶媒体 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4252749B2 (ja) * | 2001-12-13 | 2009-04-08 | 忠弘 大見 | 基板処理方法および基板処理装置 |
US20030153149A1 (en) * | 2002-02-08 | 2003-08-14 | Zhong Dong | Floating gate nitridation |
US7122222B2 (en) * | 2003-01-23 | 2006-10-17 | Air Products And Chemicals, Inc. | Precursors for depositing silicon containing films and processes thereof |
US7524707B2 (en) * | 2005-08-23 | 2009-04-28 | Freescale Semiconductor, Inc. | Modified hybrid orientation technology |
TWI267926B (en) * | 2005-09-23 | 2006-12-01 | Ind Tech Res Inst | A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate |
US7465669B2 (en) * | 2005-11-12 | 2008-12-16 | Applied Materials, Inc. | Method of fabricating a silicon nitride stack |
US20070129273A1 (en) * | 2005-12-07 | 2007-06-07 | Clark Philip G | In situ fluoride ion-generating compositions and uses thereof |
-
2005
- 2005-09-22 JP JP2005275594A patent/JP4854245B2/ja not_active Expired - Fee Related
-
2006
- 2006-09-20 US US11/523,566 patent/US7622340B2/en not_active Expired - Fee Related
- 2006-09-21 TW TW095134967A patent/TW200731410A/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003068701A (ja) * | 2001-08-08 | 2003-03-07 | Huabang Electronic Co Ltd | 窒化ケイ素のウェットエッチング率を減少させる方法 |
JP2003100868A (ja) * | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2005142539A (ja) * | 2003-10-17 | 2005-06-02 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2007035740A (ja) * | 2005-07-25 | 2007-02-08 | Tokyo Electron Ltd | 成膜方法、成膜装置及び記憶媒体 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010573A (ja) * | 2008-06-30 | 2010-01-14 | Hitachi High-Technologies Corp | 半導体加工方法 |
TWI485771B (zh) * | 2008-06-30 | 2015-05-21 | Hitachi High Tech Corp | Semiconductor processing methods |
JP2017504205A (ja) * | 2013-12-31 | 2017-02-02 | 日本テキサス・インスツルメンツ株式会社 | TiNゲートを備えた高k/金属ゲートCMOSトランジスタ |
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