CN108346577B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN108346577B
CN108346577B CN201710045041.6A CN201710045041A CN108346577B CN 108346577 B CN108346577 B CN 108346577B CN 201710045041 A CN201710045041 A CN 201710045041A CN 108346577 B CN108346577 B CN 108346577B
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gate
dielectric layer
layer
metal
forming
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CN108346577A (zh
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张青淳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

本申请涉及半导体器件及其制造方法。其中一个实施例提供了一种半导体器件的制造方法，其包括：在半导体衬底上形成具有高介电常数的栅极电介质层，其中所述栅极电介质层至少表面经过了氮化处理或者氧化处理；以及在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管。

Description

半导体器件及其制造方法
技术领域
本申请涉及半导体器件及其制造方法。
背景技术
随着半导体器件尺寸不断地缩小，最近的互补金属氧化物半导体(CMOS)器件使用高介电常数(high-k)材料作为栅极电介质层，并且使用金属作为栅极电极(HKMG)。
对于NMOS和PMOS，期望的金属栅极的功函数差别较大，分别是约4.1eV和约5.1eV。在现有技术中，为了获得适合于NMOS和PMOS的金属栅极的功函数，一般在NMOS和PMOS中分别使用不同类型(不同功函数)的金属材料来作为金属栅极。然而，这增加了对材料选择和相关工艺的挑战和限制。另外，在其中NMOS与PMOS具有互连的栅极并且挨得比较近的电路(例如，静态随机存取存储器(SRAM))中，NMOS和PMOS之间不同类型的金属栅极材料非常容易交叉扩散，从而导致阈值电压异常。
因此，希望确保金属栅极的适当功函数。另外，在CMOS的情况下，还希望形成具有双功函数的金属栅极，并且双功函数的金属栅极不会交叉扩散。
此外，希望能够使半导体器件获得更低的等效氧化物厚度(EOT)，并且能够减小栅极泄漏电流。在当前工艺中，栅极电介质层一般包括界面层(IL)和高介电常数电介质层。为了获得更低的EOT，需要减小IL和/或高介电常数电介质层的物理厚度。然而，这会导致增大的栅极泄漏电流。因此希望在不减小栅极电介质层的物理厚度的情况下获得更低的EOT。
发明内容
鉴于上述问题，本发明的发明人经过深入研究发现，通过对栅极电介质层的与金属栅极接触的表面执行不同的处理，可以影响栅极电介质层与金属栅极之间的界面，从而能够调节金属栅极的有效功函数。具体地，对栅极电介质层的表面执行氮化处理，可以降低金属栅极的有效功函数；而对栅极电介质层的表面执行氧化处理，可以提高金属栅极的有效功函数。因此，可以通过简单地对栅极电介质层的表面执行相应处理，就能获得期望的栅极功函数。这使得能够更自由地选择金属栅极的材料和相关工艺。
例如，在MOS器件采用硅作为半导体材料的情况下，通过对栅极电介质层的表面进行氮化处理，可以容易地将金属栅极功函数设置为适用于NMOS的约4.1eV。而且在对整个栅极电介质层都进行氮化处理的情况下，还可以提高栅极电介质层的介电常数，从而减小NMOS和PMOS的EOT，使得栅极泄漏变小。此外，通过对栅极电介质层的表面进行氧化处理，可以容易地将金属栅极功函数设置为适用于PMOS的约5.1eV。
由于可以通过对栅极电介质层的至少表面分别进行氮化处理和氧化处理来分别设置NMOS金属栅极和PMOS金属栅极的功函数，因此在制造CMOS的情况下，可以使用相同的金属栅极材料作为NMOS和PMOS两者的栅极。这避免了NMOS和PMOS的金属栅极材料之间的交叉扩散，并且使栅极沟槽填充和随后的平坦化工艺更加简化。
由此，在一个方面，本发明提供了一种半导体器件的制造方法，其包括：在半导体衬底上形成具有高介电常数的栅极电介质层，其中所述栅极电介质层至少表面经过了氮化处理或者氧化处理；以及在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管。
在本发明的另一个方面，提供了一种半导体器件，其包括位于半导体衬底上的晶体管，所述晶体管包括：在所述半导体衬底上的具有高介电常数的栅极电介质层以及在栅极电介质层上的金属栅极；所述晶体管为NMOS晶体管，且所述栅极电介质层为至少表面经过氮化处理的电介质层；或者，所述晶体管为PMOS晶体管，且所述栅极电介质层为至少表面经过氧化处理的电介质层。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得更为清楚。
附图说明
图1示出了根据本发明的第一实施例的半导体器件制造方法的流程图。
图2示出了根据本发明的第二实施例的半导体器件制造方法的流程图。
图3示出了根据本发明的第三实施例的半导体器件制造方法的流程图。
图4A-4F分别示出了在根据本发明的第三实施例来制造CMOS器件的一个方法示例的各个步骤处的器件截面示意图。
应当理解，这些附图仅仅是示例性的，而不是限制本发明的范围。在附图中，各组成部分并未严格按比例或严格按实际形状示出，其中的某些组成部分(例如，层或部件)可以被相对于其他的一些放大，以便更加清楚地说明本发明的原理。并且，那些可能导致使得本发明的要点模糊的细节并未在附图中示出。
具体实施方式
本发明提供了通过对栅极电介质层表面的不同处理来形成具有不同功函数的金属栅极的半导体器件的方法和结构。半导体器件及其制造方法以示例性的方式示出，来说明本发明中公开的结构和方法的不同实施例。然而，本领域技术人员将会理解，它们仅仅说明可以用来实施的本发明的示例性方式，而不是穷尽的方式。另外，结合本发明的各个方面给出的每一个示例应当是说明性的而非限制性的。此外，附图不必按比例绘制，一些特征可能被放大以示出具体组件的细节。
<第一实施例>
图1示出了根据本发明的第一实施例的半导体器件制造方法的流程图100。
在步骤110处，在半导体衬底上形成具有高介电常数的栅极电介质层，其中所述栅极电介质层至少表面经过了氮化处理或者氧化处理。
其中半导体衬底由适合于半导体器件的任何半导体材料(诸如Si、SiC、SiGe等)制成。半导体衬底中可以形成其它的器件构件，例如，隔离(诸如浅沟槽隔离(STI))、阱和/或在早期处理步骤中形成的其它构件。
另外可选地，可以在形成栅极电介质层之前，通过热生长或沉积等方式在半导体衬底上形成界面层(诸如，SiO2)以改善高介电常数的栅极电介质层与半导体衬底之间的界面状态。
可以通过诸如化学气相沉积(CVD)等各种方法来形成栅极电介质层。栅极电介质层可以由诸如HfO2、TiO2或ZrO2等的高介电常数的电介质材料形成。
可以仅对栅极电介质层的表面进行氮化处理或者氧化处理，来调节后续形成的半导体器件的金属栅极的有效功函数。或者，可以使栅极电介质层的整个层都经过氮化处理，以便在调节金属栅极的有效功函数的同时还减小MOS器件的EOT。
可以采用各种方式来对栅极电介质层的至少表面进行氮化处理或者氧化处理。下文将描述的第二和第三实施例分别采用了不同的方式来实现该氮化处理或者氧化处理。但是本发明不限于此，只要能实现该氮化处理或者氧化处理即可。
接着，在步骤120处，在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管。
由于能够通过使栅极电介质层的表面经受氮化处理或者氧化处理来调节得到期望的栅极功函数，因此能够更自由地选择形成金属栅极的材料和相关工艺。
可以通过典型的替代栅极工艺流程来形成金属栅极。金属栅极可以是单层金属或多层金属堆叠。然后优选地通过CMP工艺来使金属栅极平坦化。
在一种实现方式中，可以在该半导体衬底上形成CMOS器件，即形成PMOS晶体管和NMOS晶体管两者，并且所述NMOS晶体管的栅极电介质层至少表面经过了氮化处理，所述PMOS晶体管的栅极电介质层至少表面经过了氧化处理。此时，所述NMOS晶体管的金属栅极和所述PMOS晶体管的金属栅极可以由相同的金属材料形成。该金属材料可以为带隙居中(mid-gap)的金属材料。带隙居中的金属材料指的是金属功函数处于半导体材料的能带的导带底与价带顶的中间附近的金属。对于半导体衬底为Si的半导体器件，带隙居中的金属材料指的是金属功函数在约4.6eV处的金属材料。该种金属材料例如可以是TiN或TaN等。由于可以使用相同的金属栅极材料作为NMOS和PMOS两者的栅极，因此能够避免NMOS和PMOS的金属栅极材料之间的交叉扩散，并且使栅极沟槽填充和随后的平坦化工艺更加简化。
此外，在形成CMOS器件的情况下，既要实行氧化处理又要实行氮化处理。可以根据需要确定氧化处理和氮化处理的执行顺序。也就是说，可以先执行氮化处理再执行氧化处理，也可以先执行氧化处理再执行氮化处理。优选地，可以对PMOS晶体管的栅极电介质层先整个进行氮化处理以提高介电常数，然后对该栅极电介质层的表面实行氧化处理来调节栅极功函数。
<第二实施例>
图2示出了根据本发明的第二实施例的半导体器件制造方法的流程图200。第二实施例的制造方法是上述第一实施例的一种具体实现方式。在该部分中未具体讨论的技术细节均可以参考第一实施例的相应内容。
在步骤210处，在半导体衬底上沉积具有高介电常数的电介质材料层，其中在所述沉积过程中，对电介质材料层的至少表面掺杂氮或氧以实行氮化处理或者氧化处理，从而形成了至少表面经氮化处理或氧化处理的栅极电介质层。可以采用诸如CVD等的各种方法来沉积电介质材料层。该电介质材料层可以包括诸如HfO2、TiO2或ZrO2等材料。
步骤220与步骤120类似，在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管。具体细节参见上面关于步骤120的记载，不再赘述。
根据本发明的第二实施例，可以在沉积栅极电介质层的同时实现表面的氮化处理或者氧化处理，因此可以不增加额外的工艺步骤，简化制造流程。
<第三实施例>
图3示出了根据本发明的第三实施例的半导体器件制造方法的流程图300。第三实施例的制造方法是上述第一实施例的另一种具体实现方式。在该部分中未具体讨论的技术细节均可以参考第一实施例的相应内容。
在步骤311处，在半导体衬底上沉积具有高介电常数的电介质材料层。可以采用诸如CVD等的各种方法来沉积电介质材料层。该电介质材料层可以包括诸如HfO2、TiO2或ZrO2等材料。
在步骤312处，对电介质材料层的至少表面进行氮化处理或者氧化处理，从而形成了至少表面经氮化处理或氧化处理的栅极电介质层。
优选地，氮化处理可以包括解耦合等离子体氮化(DPN)或在氨气环境中快速热退火等。优选地，氮化处理的温度低于750℃。氮化处理的工艺参数与栅极电介质层的材料、金属栅极材料以及相应的厚度等相关。通过适当的氮化处理，可以将用于NMOS的金属栅极功函数设置为大约4.1eV。
优选地，氧化处理可以包括在含氧环境中快速热退火、解耦合等离子体氧化(DPO)或臭氧处理等。氧化处理的温度优选地低于400℃。氧化处理的工艺参数也与栅极电介质层和金属栅极的材料性质和厚度等相关。通过适当的氧化处理，可以将用于PMOS的金属栅极功函数设置为大约5.1eV。
步骤320与步骤120类似，在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管。具体细节参见上面关于步骤120的记载，不再赘述。
在采用替代栅极工艺的CMOS器件制造的情况下，本实施例的一个优选方法可以包括：在半导体衬底上沉积具有高介电常数的电介质材料层；对整个电介质材料层进行氮化处理；在经氮化的电介质材料层上形成PMOS晶体管的第一伪栅和NMOS晶体管的第二伪栅；在第一和第二伪栅的两侧、在半导体衬底中分别形成PMOS晶体管和NMOS晶体管的源极区和漏极区；去除第一伪栅，然后对电介质材料层的位于第一伪栅下方的部分的至少表面进行氧化处理，从而形成PMOS晶体管的至少表面经氧化处理的栅极电介质层；在PMOS晶体管的栅极电介质层上形成用于PMOS晶体管的金属栅极；去除第二伪栅，电介质材料层的位于第二伪栅下方的部分即为NMOS晶体管的栅极电介质层；在NMOS晶体管的栅极电介质层上形成用于NMOS晶体管的金属栅极。
相比于第二实施例，第三实施例的方法对于制造CMOS器件的情况特别有利。具体而言，在制造CMOS器件时，第二实施例的制造方法由于需要在栅极电介质层的沉积过程中针对NMOS和PMOS分别进行氮和氧的掺杂，因此要求新增光刻步骤，而光刻及相关步骤可能降低栅极电介质层的质量。而第三实施例不会引入额外的在栅极电介质层上实行的光刻步骤。
<具体示例>
为了更完整全面地理解本发明，下面将以CMOS器件为例详细描述第三实施例的半导体器件制造方法的一个具体示例。请注意，这个示例并不意图构成对本发明的限制。例如，本发明并不仅限于所示出的MOS器件的具体结构，而是对具有类似结构和工作原理的MOS器件都适用。
图4A-4F分别示出了在该方法示例的各个步骤处的器件截面示意图。
在图4A中，衬底401可以是任何半导体材料，包括但不限于Si、Ge、SiGe等。衬底401也可以是SOI。在半导体衬底中用于形成NMOS晶体管的部分和用于形成PMOS晶体管的部分之间存在浅沟槽隔离(STI)403或者任何其它合适的结构，以使得NMOS和PMOS结构能够物理地隔离。衬底401中还可以具有前期形成的其它结构，为了不混淆本发明，在此并未示出。可以通过化学气相沉积等方法来在半导体衬底401上形成具有高介电常数的电介质材料层402。电介质材料层402可以包括但不限于HfO2或TiO2或者适当的三元化合物。可选地，可以在电介质材料层402和半导体衬底401之间形成界面层，来改善电介质材料层402与半导体衬底401之间的界面。
在图4B中，在沉积电介质材料层402之后对其整个执行氮化处理，从而形成经氮化的电介质材料层402’。氮化处理例如可以通过与前述第三实施例中相同的工艺来执行。通过该氮化处理，可以将金属栅极的有效功函数调节为适用于NMOS的约4.1eV。此外，通过该氮化处理，可以增大电介质材料层402的介电常数，从而减小EOT，并且减小NMOS和PMOS晶体管的栅极泄漏。
在图4C中，执行典型的替代栅工艺。具体地，在经氮化的电介质材料层402’上形成PMOS和NMOS晶体管的伪栅406，伪栅406是限定了后来形成的操作NMOS和PMOS晶体管的金属栅极的几何形状的结构，其中随后所述伪栅406被去除并在其位置形成操作NMOS和PMOS晶体管的栅极结构，如下面进一步描述的。可以使用在本领域中已知的常规方法(例如沉积、光刻图案化和刻蚀)来在电介质材料层402’上形成伪栅406。在一种实现方式中，伪栅406可以是多晶硅层，在伪栅406与电介质材料层402’之间可以存在帽层来作为随后去除伪栅406时的停止层。形成帽层的材料可以与随后形成金属栅极的材料相同。
优选地，在伪栅406的两侧形成间隔物(未图示)，间隔物通常由电介质材料构成。可以使用覆盖层沉积和各向异性回刻等本领域已知的技术来形成间隔物。随后在伪栅406的两侧，优选地在间隔物的两侧，在衬底401中形成NMOS晶体管的源极区和漏极区404，以及PMOS晶体管的源极区和漏极区405。
源极区和漏极区404以及源极区和漏极区405可以通过离子注入/退火处理或任何其它合适的方式来形成。优选地，可以通过嵌入的SiGe来形成源极区和漏极区405。本领域技术人员将理解，除了如图示出的工艺和结构之外，本发明还包括形成半导体器件必需的其它任何工艺和结构。
在图4D中，去除PMOS晶体管的伪栅406，然后对下方的电介质材料层部分的表面执行氧化处理，从而形成PMOS晶体管的表面经氧化处理的栅极电介质层402”。氧化处理例如可以通过与前述第三实施例中相同的工艺来执行。在一种实现方式中，可以通过以下步骤来执行去除PMOS晶体管的伪栅和进行氧化处理的过程：首先，沉积层间电介质层(ILD)407，可选地沉积接触刻蚀停止层(CESL)，并对其进行平坦化以露出伪栅406的表面。使用图案化的硬掩模408来暴露PMOS晶体管的伪栅区域，同时覆盖NMOS区域。优选通过湿法和/或干法刻蚀各向异性地去除PMOS的伪栅406来形成腔409。在伪栅406与电介质材料层402’直接接触的实施方式中，去除PMOS晶体管的伪栅406后暴露出经氮化的电介质材料层402’。可替换地，在伪栅406与电介质材料层402’之间存在帽层的实施方式中，刻蚀伪栅406以露出帽层表面。随后对半导体器件执行氧化处理，以使得PMOS晶体管的伪栅406下方的电介质材料层402’的表面被氧化。对于刻蚀伪栅406以露出帽层表面的实施例，帽层的厚度优选为不超过
Figure BDA0001215964650000091
从而使得氧化处理中的氧化剂可以穿透帽层到达与电介质材料层的界面。从而形成了表面经氧化处理的栅极电介质层402”。
在图4E中，在腔409中，在PMOS晶体管的栅极电介质层上沉积金属栅极材料。沉积金属栅极材料之后，进行CMP来从每个结构的顶部(即，间隔物和ILD层上)去除金属残余物，从而形成用于PMOS晶体管的金属栅极410。
随后，如图4F所示，使用常规方法刻蚀NMOS晶体管的伪栅，下方露出的电介质材料层部分即为NMOS晶体管的栅极电介质层。然后，沉积金属栅极材料，再执行CMP工艺，从而形成用于NMOS晶体管的金属栅极411。可以使用为满足PMOS和NMOS晶体管所需的栅极功函数和栅极泄漏规范所需的任何金属来形成金属栅极410和411，以实现优化的性能。优选地，PMOS和NMOS晶体管可以使用相同的金属栅极材料，这可以避免NMOS和PMOS晶体管的金属栅极之间的交叉扩散。优选地，该金属栅极材料可以是带隙居中的金属材料，这可以包括TiN、TaN等中的一者或组合。金属栅极可以包括单层结构，或者金属堆叠的结构。金属栅极可以通过任何常规的沉积技术沉积，包括但不限于原子层沉积(ALD)、化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、分子束外延(MBE)、物理气相沉积、溅射、电镀、蒸发、旋压涂敷、离子束沉积、电子束沉积或者这些方法的任意组合。
可替换地，在图4D的工艺之后，可以不执行图4E的工艺，而是先去除NMOS的伪栅406，随后沉积金属栅极材料并且进行CMP，从而同时形成NMOS和PMOS晶体管的金属栅极。通过此工艺，可以使NMOS晶体管的金属栅极和PMOS晶体管的金属栅极由相同的金属材料形成，而且简化了栅极沟槽填充和随后的平坦化工艺。
虽然已经就优选的实施例具体地图示和描述了本发明，但本领域普通技术人员将理解，可以进行形式和细节的上述和其他的变化而不偏离本发明的精神和范围。因此，本发明不限于所描述和图示的确切形式和细节，而是包含所有落入所附权利要求的范围内的技术方案。

Claims (16)

1.一种半导体器件的制造方法，其特征在于，包括：
在半导体衬底上形成具有高介电常数的栅极电介质层，其中所述栅极电介质层至少表面经过了氮化处理或者氧化处理；以及
在栅极电介质层的经氮化处理的表面上形成金属栅极，从而形成NMOS晶体管；或者
在栅极电介质层的经氧化处理的表面上形成金属栅极，从而形成PMOS晶体管；
其中，所述半导体器件包括所述PMOS晶体管和所述NMOS晶体管两者，并且所述NMOS晶体管的栅极电介质层至少表面经过了氮化处理，所述PMOS晶体管的栅极电介质层至少表面经过了氧化处理，其中所述NMOS晶体管的金属栅极和所述PMOS晶体管的金属栅极由相同的金属材料形成。
2.根据权利要求1所述的方法，其特征在于，所述栅极电介质层的整个层都经过了氮化处理。
3.根据权利要求1所述的方法，其特征在于，所述在半导体衬底上形成具有高介电常数的栅极电介质层的步骤包括：
在半导体衬底上沉积具有高介电常数的电介质材料层，以及
对电介质材料层的至少表面进行氮化处理或者氧化处理，从而形成所述栅极电介质层。
4.根据权利要求3所述的方法，其特征在于，
所述氮化处理包括解耦合等离子体氮化或在氨气环境中快速热退火；或者
所述氧化处理包括在含氧环境中快速热退火、解耦合等离子体氧化或臭氧处理。
5.根据权利要求3所述的方法，其特征在于，
所述氮化处理的温度低于750℃；或者
所述氧化处理的温度低于400℃。
6.根据权利要求1所述的方法，其特征在于，所述在半导体衬底上形成具有高介电常数的栅极电介质层的步骤包括：
在半导体衬底上沉积具有高介电常数的电介质材料层，其中在所述沉积过程中，对电介质材料层的至少表面掺杂氮或氧以实行氮化处理或者氧化处理，从而形成所述栅极电介质层。
7.根据权利要求1所述的方法，其特征在于，所述栅极电介质层包括HfO2或TiO2。
8.根据权利要求1所述的方法，其特征在于，所述金属材料为带隙居中的金属材料。
9.根据权利要求8所述的方法，其特征在于，所述金属材料包括TiN或TaN。
10.根据权利要求1所述的方法，其特征在于，所述形成栅极电介质层的步骤以及形成金属栅极的步骤包括：
在半导体衬底上沉积具有高介电常数的电介质材料层；
对整个电介质材料层进行氮化处理；
在经氮化的电介质材料层上形成PMOS晶体管的第一伪栅和NMOS晶体管的第二伪栅；
在第一和第二伪栅的两侧、在半导体衬底中分别形成PMOS晶体管和NMOS晶体管的源极区和漏极区；
去除第一伪栅，然后对电介质材料层的位于第一伪栅下方的部分的至少表面进行氧化处理，从而形成PMOS晶体管的至少表面经氧化处理的栅极电介质层；
在PMOS晶体管的栅极电介质层上形成用于PMOS晶体管的金属栅极；
去除第二伪栅，电介质材料层的位于第二伪栅下方的部分即为NMOS晶体管的栅极电介质层；
在NMOS晶体管的栅极电介质层上形成用于NMOS晶体管的金属栅极。
11.根据权利要求10所述的方法，其特征在于，在电介质材料层与第一伪栅之间形成有厚度不超过
Figure FDA0002813692360000031
的帽层，并且去除第一伪栅、然后对电介质材料层的位于第一伪栅下方的部分的至少表面进行氧化处理的步骤包括：
去除第一伪栅，以露出帽层；
透过帽层对电介质材料层的位于第一伪栅下方的部分的至少表面执行氧化处理。
12.一种半导体器件，其特征在于，包括位于半导体衬底上的晶体管，所述晶体管包括：在所述半导体衬底上的具有高介电常数的栅极电介质层；以及在栅极电介质层上的金属栅极；
所述晶体管为NMOS晶体管，且所述栅极电介质层为至少表面经过氮化处理的电介质层；或者，
所述晶体管为PMOS晶体管，且所述栅极电介质层为至少表面经过氧化处理的电介质层；
其中，所述半导体器件包括所述PMOS晶体管和所述NMOS晶体管，所述PMOS晶体管的金属栅极和所述NMOS晶体管的金属栅极由相同的金属材料形成。
13.根据权利要求12所述的半导体器件，其特征在于，所述NMOS晶体管的栅极电介质层为整层都经过氮化处理的电介质层。
14.根据权利要求12所述的半导体器件，其特征在于，所述金属材料为带隙居中的金属材料。
15.根据权利要求14所述的半导体器件，其特征在于，所述金属材料包括TiN或TaN。
16.根据权利要求12所述的半导体器件，其特征在于，所述栅极电介质层包括HfO2或TiO2。
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