JP2007081329A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2007081329A JP2007081329A JP2005270772A JP2005270772A JP2007081329A JP 2007081329 A JP2007081329 A JP 2007081329A JP 2005270772 A JP2005270772 A JP 2005270772A JP 2005270772 A JP2005270772 A JP 2005270772A JP 2007081329 A JP2007081329 A JP 2007081329A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000007772 electrode material Substances 0.000 claims description 29
- 238000010030 laminating Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 abstract description 43
- 238000009792 diffusion process Methods 0.000 abstract description 15
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 129
- 238000000034 method Methods 0.000 description 35
- 239000010410 layer Substances 0.000 description 31
- 238000004519 manufacturing process Methods 0.000 description 24
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 12
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910003855 HfAlO Inorganic materials 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910010037 TiAlN Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910004140 HfO Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Abstract
【解決手段】たとえば、Si基板11の表面上には、素子領域となるFin12が設けられている。Fin12には、ソース・ドレイン拡散層23a,23bが形成されている。ソース・ドレイン拡散層23a,23bの相互間には、チャネル部が形成されている。このチャネル部に対応する、上記Fin12の一部を覆うようにしてゲート電極部21が設けられている。ゲート電極部21は、第1の仕事関数を有する第1のゲート電極21a上に、第1のゲート電極21aとは異なる、第2の仕事関数を有する第2のゲート電極21bを積層してなる構成とされている。
【選択図】 図1
Description
Masaki Kondo et al.,"A FinFET Design Based on Three−Dimensional Process and Device Simulations",Toshiba Corporation,IEEE,2003.
図1は、本発明の第1の実施形態にしたがった半導体装置(Fin−FET)の基本構成を示すものである。なお、同図(a)は斜視図であり、同図(b)は平面図、同図(c)は図(a)のIc−Ic線に沿う断面図、同図(d)は図(a)のId−Id線に沿う断面図、同図(e)は図(a)のIe−Ie線に沿う断面図である。ここでは、基板の一部を所望の形状に加工することによって、Finが形成されてなる場合について説明する。また、ゲート電極部の形成に、電極材料としてメタルを用いるようにした場合について説明する。
図17は、本発明の第2の実施形態にしたがった半導体装置(Fin−FET)の基本構成を示すものである。なお、同図(a)は斜視図であり、同図(b)は平面図、同図(c)は図(a)のIIc−IIc線に沿う断面図、同図(d)は図(a)のIId−IId線に沿う断面図、同図(e)は図(a)のIIe−IIe線に沿う断面図である。ここでは、第1のゲート電極を、少なくともFinに隣接する、第2のゲート電極の一部に対応して設けるようにした場合について説明する。また、第1の実施形態に示したFin−FET(図1(a)〜(e)参照)と同一部分には同一符号を付し、詳しい説明は割愛する。
図21は、本発明の第3の実施形態にしたがった半導体装置(Fin−FET)の基本構成を示すものである。なお、同図(a)は斜視図であり、同図(b)は平面図、同図(c)は図(a)のIIIc−IIIc線に沿う断面図、同図(d)は図(a)のIIId−IIId線に沿う断面図、同図(e)は図(a)のIIIe−IIIe線に沿う断面図である。ここでは、基板の上面に選択エピタキシャル成長法により選択的にFinが形成されてなる場合について説明する。また、第1の実施形態に示したFin−FET(図1(a)〜(e)参照)と同一部分には同一符号を付し、詳しい説明は割愛する。
Claims (5)
- 半導体基板と、
前記半導体基板上に形成され、長手方向と短手方向を有するフィン型形の半導体層と、
ゲート絶縁膜を介して、前記半導体層の前記短手方向の側面に形成されたゲート電極部と、
前記半導体層内の前記ゲート絶縁層に隣接する位置に形成されたチャネル部と、
前記半導体層の前記チャネル部に対し前記長手方向に隣接して形成されたソース・ドレイン領域と
を備え、
前記ゲート電極部は、異なる仕事関数を有する複数の電極材料を積層してなることを特徴とする半導体装置。 - 前記ゲート電極部は、少なくとも第1のゲート電極と、この第1のゲート電極上に形成された第2のゲート電極とから構成され、
前記第1のゲート電極におけるしきい値は、前記第2のゲート電極におけるしきい値よりも大きいことを特徴とする請求項1に記載の半導体装置。 - 前記半導体装置はnチャネル型MOSFETであって、
前記第1のゲート電極の仕事関数は、前記第2のゲート電極の仕事関数よりも大きいことを特徴とする請求項2に記載の半導体装置。 - 前記半導体装置はpチャネル型MOSFETであって、
前記第1のゲート電極の仕事関数は、前記第2のゲート電極の仕事関数よりも小さいことを特徴とする請求項2に記載の半導体装置。 - 前記ゲート電極部は、前記第1のゲート電極と前記第2のゲート電極との間に、さらに、前記第1の電極材料と前記第2の電極材料との中間の仕事関数を有する第3の電極材料を用いて形成される第3のゲート電極が設けられていることを特徴とする請求項2乃至4のいずれか1項に記載の半導体装置。
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Application Number | Priority Date | Filing Date | Title |
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JP2005270772A JP4921755B2 (ja) | 2005-09-16 | 2005-09-16 | 半導体装置 |
US11/495,885 US7868395B2 (en) | 2005-09-16 | 2006-07-31 | Metal insulator semiconductor field effect transistor having fin structure |
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JP2005270772A JP4921755B2 (ja) | 2005-09-16 | 2005-09-16 | 半導体装置 |
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JP2007081329A true JP2007081329A (ja) | 2007-03-29 |
JP4921755B2 JP4921755B2 (ja) | 2012-04-25 |
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Cited By (8)
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JP2009060104A (ja) * | 2007-08-31 | 2009-03-19 | Samsung Electronics Co Ltd | ピン電界効果トランジスタ及びその製造方法 |
JP2009123760A (ja) * | 2007-11-12 | 2009-06-04 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2009267021A (ja) * | 2008-04-24 | 2009-11-12 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2010034468A (ja) * | 2008-07-31 | 2010-02-12 | Renesas Technology Corp | 半導体装置及びその製造方法 |
KR20170048324A (ko) * | 2014-08-29 | 2017-05-08 | 인텔 코포레이션 | 고 종횡비의 좁은 구조체들을 다수의 금속 층들로 채우기 위한 기술 및 관련 구성들 |
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US20090061611A1 (en) * | 2007-08-30 | 2009-03-05 | Willy Rachmady | Fabricating dual layer gate electrodes having polysilicon and a workfunction metal |
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US8263451B2 (en) * | 2010-02-26 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy profile engineering for FinFETs |
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US8932918B2 (en) | 2012-08-29 | 2015-01-13 | International Business Machines Corporation | FinFET with self-aligned punchthrough stopper |
CN103811343B (zh) * | 2012-11-09 | 2016-12-21 | 中国科学院微电子研究所 | FinFET及其制造方法 |
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US9276114B2 (en) * | 2013-02-01 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with dual workfunction gate structure |
US8940602B2 (en) * | 2013-04-11 | 2015-01-27 | International Business Machines Corporation | Self-aligned structure for bulk FinFET |
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JP2019050314A (ja) * | 2017-09-11 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US11227932B2 (en) * | 2018-05-16 | 2022-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with a fin top hardmask |
US11757021B2 (en) * | 2020-08-18 | 2023-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with fin-top hard mask and methods for fabrication thereof |
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- 2005-09-16 JP JP2005270772A patent/JP4921755B2/ja not_active Expired - Fee Related
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- 2006-07-31 US US11/495,885 patent/US7868395B2/en active Active
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JPH08139325A (ja) * | 1994-09-14 | 1996-05-31 | Toshiba Corp | 半導体装置 |
JP2004281845A (ja) * | 2003-03-18 | 2004-10-07 | Toshiba Corp | 半導体装置およびその製造方法 |
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US7868395B2 (en) | 2011-01-11 |
US20070063224A1 (en) | 2007-03-22 |
JP4921755B2 (ja) | 2012-04-25 |
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