JP2006527914A - 絶縁体上シリコン型構造およびその製造方法並びに集積回路 - Google Patents

絶縁体上シリコン型構造およびその製造方法並びに集積回路 Download PDF

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Publication number
JP2006527914A
JP2006527914A JP2006515959A JP2006515959A JP2006527914A JP 2006527914 A JP2006527914 A JP 2006527914A JP 2006515959 A JP2006515959 A JP 2006515959A JP 2006515959 A JP2006515959 A JP 2006515959A JP 2006527914 A JP2006527914 A JP 2006527914A
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JP
Japan
Prior art keywords
insulator
silicon
contact portion
groove
substrate contact
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Pending
Application number
JP2006515959A
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English (en)
Japanese (ja)
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JP2006527914A5 (enExample
Inventor
タグ カン，ウー
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2006527914A publication Critical patent/JP2006527914A/ja
Publication of JP2006527914A5 publication Critical patent/JP2006527914A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/378—Contact regions to the substrate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
JP2006515959A 2003-06-16 2004-06-16 絶縁体上シリコン型構造およびその製造方法並びに集積回路 Pending JP2006527914A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/463,023 US6930357B2 (en) 2003-06-16 2003-06-16 Active SOI structure with a body contact through an insulator
PCT/EP2004/006498 WO2004112127A1 (en) 2003-06-16 2004-06-16 Soi shaped structure

Publications (2)

Publication Number Publication Date
JP2006527914A true JP2006527914A (ja) 2006-12-07
JP2006527914A5 JP2006527914A5 (enExample) 2010-03-11

Family

ID=33511523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006515959A Pending JP2006527914A (ja) 2003-06-16 2004-06-16 絶縁体上シリコン型構造およびその製造方法並びに集積回路

Country Status (5)

Country Link
US (1) US6930357B2 (enExample)
EP (1) EP1634327A1 (enExample)
JP (1) JP2006527914A (enExample)
CN (1) CN100373594C (enExample)
WO (1) WO2004112127A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527692A (ja) * 2005-01-03 2008-07-24 フリースケール セミコンダクター インコーポレイテッド リセス型ソース／ドレイン領域をｓｏｉウェハに含む半導体形成プロセス

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116623A (ja) * 2003-10-03 2005-04-28 Nec Electronics Corp 半導体装置およびその製造方法
US7186622B2 (en) * 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US7298009B2 (en) * 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
US8530355B2 (en) * 2005-12-23 2013-09-10 Infineon Technologies Ag Mixed orientation semiconductor device and method
KR100703033B1 (ko) * 2006-03-22 2007-04-09 삼성전자주식회사 반도체 장치 및 그 제조 방법
US7989893B2 (en) * 2008-08-28 2011-08-02 International Business Machines Corporation SOI body contact using E-DRAM technology
CN101694846B (zh) * 2009-10-14 2011-08-31 上海宏力半导体制造有限公司 一种soi级联双管mos晶体管结构
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US10079248B2 (en) * 2016-11-18 2018-09-18 Globalfoundries Inc. Field-effect transistors with a buried body contact

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247151A (ja) * 1985-08-26 1987-02-28 インテル・コ−ポレ−シヨン 相互接続部を基板に形成する方法
JPS63237560A (ja) * 1987-03-26 1988-10-04 Nec Corp 絶縁ゲ−ト電界効果トランジスタおよびその製造方法
JPH11307771A (ja) * 1998-04-23 1999-11-05 Toshiba Corp 半導体装置及びその製造方法
JP2002190599A (ja) * 2000-12-20 2002-07-05 Toshiba Corp 半導体装置及びその製造方法
US20020163041A1 (en) * 2000-03-30 2002-11-07 Min-Su Kim Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate

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US4763183A (en) * 1984-08-01 1988-08-09 American Telephone And Telegraph Co., At&T Bell Laboratories Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method
DE3851649T2 (de) * 1987-03-20 1995-05-04 Nippon Electric Co Aus einer Vielzahl von Eintransistorzellen bestehende dynamische Speichervorrichtung mit wahlfreiem Zugriff.
US5593912A (en) * 1994-10-06 1997-01-14 International Business Machines Corporation SOI trench DRAM cell for 256 MB DRAM and beyond
US5606188A (en) * 1995-04-26 1997-02-25 International Business Machines Corporation Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory
JPH09283766A (ja) 1996-04-18 1997-10-31 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100268419B1 (ko) * 1998-08-14 2000-10-16 윤종용 고집적 반도체 메모리 장치 및 그의 제조 방법
US6245663B1 (en) * 1998-09-30 2001-06-12 Conexant Systems, Inc. IC interconnect structures and methods for making same
KR100350575B1 (ko) * 1999-11-05 2002-08-28 주식회사 하이닉스반도체 소오스-바디-기판이 접촉된 이중막 실리콘 소자 및 제조방법
WO2001043198A2 (en) 1999-12-13 2001-06-14 Infineon Technologies North America Corp. Source/drain-on-insulator (s/doi) field effect transistor using silicon nitride and silicon oxide and method of fabrication
US6429099B1 (en) * 2000-01-05 2002-08-06 International Business Machines Corporation Implementing contacts for bodies of semiconductor-on-insulator transistors
US6174754B1 (en) * 2000-03-17 2001-01-16 Taiwan Semiconductor Manufacturing Company Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors
US6284594B1 (en) * 2000-05-30 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure
US6469350B1 (en) * 2001-10-26 2002-10-22 International Business Machines Corporation Active well schemes for SOI technology
US7067235B2 (en) * 2002-01-15 2006-06-27 Ming Huan Tsai Bi-layer photoresist dry development and reactive ion etch method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247151A (ja) * 1985-08-26 1987-02-28 インテル・コ−ポレ−シヨン 相互接続部を基板に形成する方法
JPS63237560A (ja) * 1987-03-26 1988-10-04 Nec Corp 絶縁ゲ−ト電界効果トランジスタおよびその製造方法
JPH11307771A (ja) * 1998-04-23 1999-11-05 Toshiba Corp 半導体装置及びその製造方法
US20020163041A1 (en) * 2000-03-30 2002-11-07 Min-Su Kim Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate
JP2002190599A (ja) * 2000-12-20 2002-07-05 Toshiba Corp 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527692A (ja) * 2005-01-03 2008-07-24 フリースケール セミコンダクター インコーポレイテッド リセス型ソース／ドレイン領域をｓｏｉウェハに含む半導体形成プロセス

Also Published As

Publication number Publication date
CN1809920A (zh) 2006-07-26
US20040253773A1 (en) 2004-12-16
CN100373594C (zh) 2008-03-05
EP1634327A1 (en) 2006-03-15
WO2004112127A1 (en) 2004-12-23
US6930357B2 (en) 2005-08-16

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