JP2006523960A5 - - Google Patents

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Publication number
JP2006523960A5
JP2006523960A5 JP2006510101A JP2006510101A JP2006523960A5 JP 2006523960 A5 JP2006523960 A5 JP 2006523960A5 JP 2006510101 A JP2006510101 A JP 2006510101A JP 2006510101 A JP2006510101 A JP 2006510101A JP 2006523960 A5 JP2006523960 A5 JP 2006523960A5
Authority
JP
Japan
Prior art keywords
substrate
transverse
thermal expansion
processing
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006510101A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006523960A (ja
Filing date
Publication date
Priority claimed from US10/418,870 external-priority patent/US6884645B2/en
Application filed filed Critical
Publication of JP2006523960A publication Critical patent/JP2006523960A/ja
Publication of JP2006523960A5 publication Critical patent/JP2006523960A5/ja
Pending legal-status Critical Current

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JP2006510101A 2003-04-18 2004-04-16 整合した熱膨張係数を有する複合基体上の付着されたウエハ構造を有する装置構造を処理する方法 Pending JP2006523960A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/418,870 US6884645B2 (en) 2003-04-18 2003-04-18 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion
PCT/US2004/011712 WO2004095554A2 (en) 2003-04-18 2004-04-16 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion

Publications (2)

Publication Number Publication Date
JP2006523960A JP2006523960A (ja) 2006-10-19
JP2006523960A5 true JP2006523960A5 (enExample) 2007-02-22

Family

ID=33159201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006510101A Pending JP2006523960A (ja) 2003-04-18 2004-04-16 整合した熱膨張係数を有する複合基体上の付着されたウエハ構造を有する装置構造を処理する方法

Country Status (5)

Country Link
US (1) US6884645B2 (enExample)
EP (1) EP1552548A2 (enExample)
JP (1) JP2006523960A (enExample)
TW (1) TWI251353B (enExample)
WO (1) WO2004095554A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612895B2 (en) * 2007-05-18 2009-11-03 Suss Microtec Inc Apparatus and method for in-situ monitoring of wafer bonding time
DE102009007625A1 (de) 2008-11-14 2010-05-20 Osram Opto Semiconductors Gmbh Verbundsubstrat für einen Halbleiterchip
CN113376403B (zh) * 2021-05-12 2023-02-28 北京航天控制仪器研究所 一种有冗余功能的mems加速度计检测模块及其制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153445A (en) 1981-03-17 1982-09-22 Nec Corp Sos semiconductor substrate
JPH0770472B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体基板の製造方法
JPH01189909A (ja) * 1988-01-26 1989-07-31 Nippon Telegr & Teleph Corp <Ntt> 複合半導体基板
US5365088A (en) * 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH04171811A (ja) * 1990-11-05 1992-06-19 Olympus Optical Co Ltd 半導体装置
US5308980A (en) * 1991-02-20 1994-05-03 Amber Engineering, Inc. Thermal mismatch accommodated infrared detector hybrid array
JP2669368B2 (ja) * 1994-03-16 1997-10-27 日本電気株式会社 Ｓｉ基板上化合物半導体積層構造の製造方法
US5585624A (en) * 1995-03-23 1996-12-17 Rockwell International Corporation Apparatus and method for mounting and stabilizing a hybrid focal plane array
US5610389A (en) * 1995-03-23 1997-03-11 Rockwell International Corporation Stabilized hybrid focal plane array structure
JP2671859B2 (ja) * 1995-04-14 1997-11-05 日本電気株式会社 赤外線検出素子及びその製造方法
US5714760A (en) * 1995-06-07 1998-02-03 Boeing North American, Inc. Imbalanced layered composite focal plane array structure
US5846850A (en) * 1995-09-05 1998-12-08 Raytheon Ti Systems, Inc. Double sided interdiffusion process and structure for a double layer heterojunction focal plane array
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6045614A (en) * 1996-03-14 2000-04-04 Raytheon Company Method for epitaxial growth of twin-free, (111)-oriented II-VI alloy films on silicon substrates
JP3480297B2 (ja) * 1997-10-10 2003-12-15 豊田合成株式会社 半導体素子
US6320206B1 (en) * 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6498113B1 (en) * 2001-06-04 2002-12-24 Cbl Technologies, Inc. Free standing substrates by laser-induced decoherency and regrowth
JP2003218031A (ja) * 2002-01-28 2003-07-31 Toshiba Ceramics Co Ltd 半導体ウェーハの製造方法
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates

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