TWI251353B - Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion - Google Patents

Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion Download PDF

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Publication number
TWI251353B
TWI251353B TW093129734A TW93129734A TWI251353B TW I251353 B TWI251353 B TW I251353B TW 093129734 A TW093129734 A TW 093129734A TW 93129734 A TW93129734 A TW 93129734A TW I251353 B TWI251353 B TW I251353B
Authority
TW
Taiwan
Prior art keywords
wafer
thermal expansion
layer
substrate
preparing
Prior art date
Application number
TW093129734A
Other languages
English (en)
Chinese (zh)
Other versions
TW200611423A (en
Inventor
Jeffrey M Peterson
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Application granted granted Critical
Publication of TWI251353B publication Critical patent/TWI251353B/zh
Publication of TW200611423A publication Critical patent/TW200611423A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
TW093129734A 2003-04-18 2004-09-30 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion TWI251353B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/418,870 US6884645B2 (en) 2003-04-18 2003-04-18 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion

Publications (2)

Publication Number Publication Date
TWI251353B true TWI251353B (en) 2006-03-11
TW200611423A TW200611423A (en) 2006-04-01

Family

ID=33159201

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093129734A TWI251353B (en) 2003-04-18 2004-09-30 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion

Country Status (5)

Country Link
US (1) US6884645B2 (enExample)
EP (1) EP1552548A2 (enExample)
JP (1) JP2006523960A (enExample)
TW (1) TWI251353B (enExample)
WO (1) WO2004095554A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612895B2 (en) * 2007-05-18 2009-11-03 Suss Microtec Inc Apparatus and method for in-situ monitoring of wafer bonding time
DE102009007625A1 (de) 2008-11-14 2010-05-20 Osram Opto Semiconductors Gmbh Verbundsubstrat für einen Halbleiterchip
CN113376403B (zh) * 2021-05-12 2023-02-28 北京航天控制仪器研究所 一种有冗余功能的mems加速度计检测模块及其制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153445A (en) 1981-03-17 1982-09-22 Nec Corp Sos semiconductor substrate
JPH0770472B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体基板の製造方法
JPH01189909A (ja) * 1988-01-26 1989-07-31 Nippon Telegr & Teleph Corp <Ntt> 複合半導体基板
US5365088A (en) * 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH04171811A (ja) * 1990-11-05 1992-06-19 Olympus Optical Co Ltd 半導体装置
US5308980A (en) * 1991-02-20 1994-05-03 Amber Engineering, Inc. Thermal mismatch accommodated infrared detector hybrid array
JP2669368B2 (ja) * 1994-03-16 1997-10-27 日本電気株式会社 Ｓｉ基板上化合物半導体積層構造の製造方法
US5585624A (en) * 1995-03-23 1996-12-17 Rockwell International Corporation Apparatus and method for mounting and stabilizing a hybrid focal plane array
US5610389A (en) * 1995-03-23 1997-03-11 Rockwell International Corporation Stabilized hybrid focal plane array structure
JP2671859B2 (ja) * 1995-04-14 1997-11-05 日本電気株式会社 赤外線検出素子及びその製造方法
US5714760A (en) * 1995-06-07 1998-02-03 Boeing North American, Inc. Imbalanced layered composite focal plane array structure
US5846850A (en) * 1995-09-05 1998-12-08 Raytheon Ti Systems, Inc. Double sided interdiffusion process and structure for a double layer heterojunction focal plane array
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6045614A (en) * 1996-03-14 2000-04-04 Raytheon Company Method for epitaxial growth of twin-free, (111)-oriented II-VI alloy films on silicon substrates
JP3480297B2 (ja) * 1997-10-10 2003-12-15 豊田合成株式会社 半導体素子
US6320206B1 (en) * 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6498113B1 (en) * 2001-06-04 2002-12-24 Cbl Technologies, Inc. Free standing substrates by laser-induced decoherency and regrowth
JP2003218031A (ja) * 2002-01-28 2003-07-31 Toshiba Ceramics Co Ltd 半導体ウェーハの製造方法
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates

Also Published As

Publication number Publication date
EP1552548A2 (en) 2005-07-13
WO2004095554A3 (en) 2004-12-23
WO2004095554A2 (en) 2004-11-04
JP2006523960A (ja) 2006-10-19
US6884645B2 (en) 2005-04-26
US20040209440A1 (en) 2004-10-21
TW200611423A (en) 2006-04-01

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