JP2006509375A5 - - Google Patents
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- Publication number
- JP2006509375A5 JP2006509375A5 JP2004559293A JP2004559293A JP2006509375A5 JP 2006509375 A5 JP2006509375 A5 JP 2006509375A5 JP 2004559293 A JP2004559293 A JP 2004559293A JP 2004559293 A JP2004559293 A JP 2004559293A JP 2006509375 A5 JP2006509375 A5 JP 2006509375A5
- Authority
- JP
- Japan
- Prior art keywords
- nitride layer
- layer
- patterned
- millitorr
- chf
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 claims 8
- 239000004065 semiconductor Substances 0.000 claims 3
- 210000002381 Plasma Anatomy 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Claims (7)
- 半導体構造体の製造方法であって、
窒化層をプラズマによりエッチングして、パターン形成された窒化層を形成する工程を含み、
前記窒化層は半導体基板上にあり、
１９３ナノメートルのフォトレジスト層が前記窒化層上にあり、
前記プラズマは少なくとも１０ミリトルの圧力においてＣＦ4及びＣＨＦ3を含むガス混合物から調製される、
ことを特徴とする、前記方法。 - 前記ガス混合物は、ＣＦ4：ＣＨＦ3比が１０：１から１：３であることを特徴とする請求項１に記載の方法。
- 前記圧力は１５から４５ミリトルであることを特徴とする請求項１に記載の方法。
- 前記パターン形成された窒化層は９ナノメートル以下のラインエッジ粗さを有することを特徴とする請求項１に記載の方法。
- 前記パターン形成された窒化層は、６ナノメートル以下のラインエッジ粗さであることを特徴とする請求項１に記載の方法。
- ケイ素を含むゲート層が、前記窒化層と前記半導体基板との間にあることを特徴とする請求項１に記載の方法。
- 金属層が、前記窒化層と前記ゲート層との間にあることを特徴とする請求項６に記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/314,380 US7229929B2 (en) | 2002-12-06 | 2002-12-06 | Multi-layer gate stack |
| PCT/US2003/038631 WO2004053936A2 (en) | 2002-12-06 | 2003-12-04 | Multi-layer gate stack |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006509375A JP2006509375A (ja) | 2006-03-16 |
| JP2006509375A5 true JP2006509375A5 (ja) | 2007-01-25 |
Family
ID=32468458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004559293A Pending JP2006509375A (ja) | 2002-12-06 | 2003-12-04 | 多層ゲートスタック |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7229929B2 (ja) |
| JP (1) | JP2006509375A (ja) |
| KR (1) | KR20050085415A (ja) |
| AU (1) | AU2003300819A1 (ja) |
| WO (1) | WO2004053936A2 (ja) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7229929B2 (en) * | 2002-12-06 | 2007-06-12 | Cypress Semiconductor Corporation | Multi-layer gate stack |
| US20040217006A1 (en) * | 2003-03-18 | 2004-11-04 | Small Robert J. | Residue removers for electrohydrodynamic cleaning of semiconductors |
| US7371637B2 (en) * | 2003-09-26 | 2008-05-13 | Cypress Semiconductor Corporation | Oxide-nitride stack gate dielectric |
| US7153780B2 (en) * | 2004-03-24 | 2006-12-26 | Intel Corporation | Method and apparatus for self-aligned MOS patterning |
| US7351663B1 (en) * | 2004-06-25 | 2008-04-01 | Cypress Semiconductor Corporation | Removing whisker defects |
| KR100753138B1 (ko) * | 2006-09-29 | 2007-08-30 | 주식회사 하이닉스반도체 | 반도체 소자 제조방법 |
| US8252640B1 (en) | 2006-11-02 | 2012-08-28 | Kapre Ravindra M | Polycrystalline silicon activation RTA |
| JP2008218867A (ja) * | 2007-03-07 | 2008-09-18 | Elpida Memory Inc | 半導体装置の製造方法 |
| US7951728B2 (en) | 2007-09-24 | 2011-05-31 | Applied Materials, Inc. | Method of improving oxide growth rate of selective oxidation processes |
| US9406530B2 (en) | 2014-03-27 | 2016-08-02 | International Business Machines Corporation | Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping |
| US10204960B2 (en) * | 2015-09-17 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming polysilicon gate structure in image sensor device |
| US20170330764A1 (en) * | 2016-05-12 | 2017-11-16 | Lam Research Corporation | Methods and apparatuses for controlling transitions between continuous wave and pulsing plasmas |
| US10566211B2 (en) | 2016-08-30 | 2020-02-18 | Lam Research Corporation | Continuous and pulsed RF plasma for etching metals |
| US9865473B1 (en) * | 2016-11-15 | 2018-01-09 | Globalfoundries Inc. | Methods of forming semiconductor devices using semi-bidirectional patterning and islands |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW320749B (ja) * | 1994-09-22 | 1997-11-21 | Tokyo Electron Co Ltd | |
| US5817579A (en) * | 1997-04-09 | 1998-10-06 | Vanguard International Semiconductor Corporation | Two step plasma etch method for forming self aligned contact |
| JP3902835B2 (ja) * | 1997-06-27 | 2007-04-11 | 東京応化工業株式会社 | ポジ型ホトレジスト組成物 |
| US6635185B2 (en) * | 1997-12-31 | 2003-10-21 | Alliedsignal Inc. | Method of etching and cleaning using fluorinated carbonyl compounds |
| US6107135A (en) * | 1998-02-11 | 2000-08-22 | Kabushiki Kaisha Toshiba | Method of making a semiconductor memory device having a buried plate electrode |
| US6342452B1 (en) * | 1999-05-20 | 2002-01-29 | International Business Machines Corporation | Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask |
| JP3320685B2 (ja) * | 1999-06-02 | 2002-09-03 | 株式会社半導体先端テクノロジーズ | 微細パターン形成方法 |
| US6740566B2 (en) * | 1999-09-17 | 2004-05-25 | Advanced Micro Devices, Inc. | Ultra-thin resist shallow trench process using high selectivity nitride etch |
| US6258677B1 (en) * | 1999-10-01 | 2001-07-10 | Chartered Seminconductor Manufacturing Ltd. | Method of fabricating wedge isolation transistors |
| US6897120B2 (en) * | 2001-01-03 | 2005-05-24 | Micron Technology, Inc. | Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate |
| JP4530552B2 (ja) * | 2001-01-29 | 2010-08-25 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| US6624068B2 (en) * | 2001-08-24 | 2003-09-23 | Texas Instruments Incorporated | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography |
| US6451647B1 (en) * | 2002-03-18 | 2002-09-17 | Advanced Micro Devices, Inc. | Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual |
| US20040087153A1 (en) * | 2002-10-31 | 2004-05-06 | Yan Du | Method of etching a silicon-containing dielectric material |
| US7229929B2 (en) * | 2002-12-06 | 2007-06-12 | Cypress Semiconductor Corporation | Multi-layer gate stack |
-
2002
- 2002-12-06 US US10/314,380 patent/US7229929B2/en not_active Expired - Lifetime
-
2003
- 2003-12-04 JP JP2004559293A patent/JP2006509375A/ja active Pending
- 2003-12-04 KR KR1020057010280A patent/KR20050085415A/ko not_active Application Discontinuation
- 2003-12-04 AU AU2003300819A patent/AU2003300819A1/en not_active Abandoned
- 2003-12-04 WO PCT/US2003/038631 patent/WO2004053936A2/en active Application Filing
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