JP2006332179A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006332179A JP2006332179A JP2005150938A JP2005150938A JP2006332179A JP 2006332179 A JP2006332179 A JP 2006332179A JP 2005150938 A JP2005150938 A JP 2005150938A JP 2005150938 A JP2005150938 A JP 2005150938A JP 2006332179 A JP2006332179 A JP 2006332179A
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- film
- metal element
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- insulating film
- silicon
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Abstract
【解決手段】 CMISFETを構成するnチャネル型MISFET40とpチャネル型MISFET41は、ゲート絶縁膜14,15が酸窒化シリコン膜からなり、ゲート電極23,24が、ゲート絶縁膜14,15上に位置するシリコン膜を含んでいる。ゲート電極23,24とゲート絶縁膜14,15との界面近傍に、1×1013〜5×1014原子/cm2の面密度でHfのような金属元素が導入されている。nチャネル型MISFET40とpチャネル型MISFET41のチャネル領域の不純物濃度は、1.2×1018/cm3以下に制御されている。
【選択図】 図11
Description
本実施の形態の半導体装置およびその製造方法を図面を参照して説明する。
図1は、本実施の形態の半導体装置の製造工程を示す工程フロー図である。図2〜図4、図6、図7、図9〜図12は、本実施の形態の半導体装置の製造工程中の要部断面図である。図5は、酸化シリコン膜11上に金属元素12aを微量堆積した状態を模式的に示す部分拡大断面図(要部断面図)である。図8は、酸窒化シリコン膜13上にシリコン膜21を形成した状態を模式的に示す部分拡大断面図(要部断面図)である。なお、図1には、半導体装置の製造工程のうち、ゲート絶縁膜形成用の絶縁膜(酸化シリコン膜11)の形成工程からゲート電極(ゲート電極23,24)の形成工程までの工程フローが示されている。
本実施の形態では、同一の半導体基板1上に複数種類(2種類以上)の膜厚を有する多水準ゲート絶縁膜を形成し、ゲート絶縁膜と、ゲート絶縁膜とSiゲート電極との界面に面密度が1×1013〜5×1014原子/cm2の金属元素12aを導入しており、その金属元素12aの面密度が全てのゲート絶縁膜で同じである。
本実施の形態では、同一の半導体基板1上に形成された、ゲート絶縁膜の膜厚がほぼ等しく、しきい電圧が異なる2種類のCMISFETについて、ゲート絶縁膜とSiゲート電極との界面に導入する金属の量によってしきい電圧を調整する半導体装置の製造方法について説明する。ここでは、ゲート絶縁膜の膜厚が1.8nmで、電源電圧が1.2Vであり、しきい電圧の絶対値が0.25Vと0.5Vに調整された2種類のCMISFET61,62と、ゲート絶縁膜の膜厚が7.0nmで、電源電圧が3.3VのCMISFET63との合計3種類のCMISFET61,62,63を同時に形成する場合を例に挙げて、説明する。
上記実施の形態1〜3では、ゲート絶縁膜形成用の酸化シリコン膜上に金属元素12aを金属酸化物などとして堆積することで、ゲート絶縁膜とSiゲート電極との界面に金属元素12a(例えばHf)を導入していた。本実施の形態では、酸化シリコン膜または酸窒化シリコン膜上にSiゲート電極を形成した後に、金属元素12aをイオン注入法によって導入することにより、ゲート絶縁膜とSiゲート電極の界面に金属元素12a(例えばHf)を導入する。
本実施の形態では、上記実施の形態4で説明したイオン注入によって金属(例えばHf)を導入する手法を、同一の半導体基板1上に複数種類(2種類以上)の膜厚を有する多水準ゲート絶縁膜を有するCMISFETに適用した場合について説明する。
1A nチャネル型MISFET形成領域
1B pチャネル型MISFET形成領域
2 素子分離領域
3,3a,3b,3c,3d,3e,3g,3h,3j p型ウエル
4,4a,4b,4c,4d,4e,4g,4h,4j チャネル領域
5,5a,5b,5c,5d,5e,5g,5h,5j n型ウエル
6,6a,6b,6c,6d,6e,6g,6h,6j チャネル領域
10A,10B,10C,10D,10E,10G,10H,10J 領域
11,11a,11b,11c,11d,11e,11g,11h,11j 酸化シリコン膜
12 金属元素堆積処理
12a 金属元素
12b 元素
12c イオン注入
13,13a,13b,13c,13d,13e,13f,13g,13h,13j 酸窒化シリコン膜
14,14a,14b,14c,14d,14e,14f,14g,14h,14j,15,15a,15b,15c,15d,15e,15f,15g,15h,15j ゲート絶縁膜
21,21a,21b シリコン膜
23,23a,23b,23c,23d,23e,23f,23g,23h,23j,24,24a,24b,24c,24d,24e,24f,24g,24h,24j ゲート電極
25,25a,25b,25c,25d,25e,25g,25h,25j n−型半導体領域
26 p型半導体領域
27,27a,27b,27c,27d,27e,27g,27h,27j p−型半導体領域
28 n型半導体領域
30 サイドウォール
31,31a,31b,31c,31d,31e,31g,31h,31j n+型半導体領域
32,32a,32b,32c,32d,32e,32g,32h,32j p+型半導体領域
33 金属シリサイド層
40,40a,40b,40c,40d,40e,40f,40g,40h,40j MISFET
41,41a,41b,41c,41d,41e,41f,41g,41h,41j MISFET
51 絶縁膜
52 コンタクトホール
53 プラグ
53a バリア膜
53b 高融点金属膜
54 配線
54a 窒化チタン膜
54b アルミニウム膜
54c 窒化チタン膜
60a,60b,61,62,63,81,82,83 CMISFET
71 絶縁膜
85 フォトレジスト層
Claims (20)
- 半導体基板と、
前記半導体基板に形成されたnチャネル型の第1のMISFETと、
前記半導体基板に形成されたpチャネル型の第2のMISFETとを備え、
前記第1および第2のMISFETのゲート絶縁膜は、酸化シリコン膜または酸窒化シリコン膜からなり、
前記第1および第2のMISFETのゲート電極は、前記ゲート絶縁膜上に位置するシリコン膜を含み、
前記第1および第2のMISFETの前記ゲート電極と前記ゲート絶縁膜との界面近傍に、1×1013〜5×1014原子/cm2の面密度で金属元素が導入されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1および第2のMISFETのチャネル領域の不純物濃度が、1.2×1018/cm3以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記金属元素が、結晶シリコンのバンドギャップの内部にドナー準位とアクセプター準位の両方を形成できる金属元素であることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記金属元素が、Hf、Zr、Pt、MoまたはWであることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記金属元素が、結晶シリコンのバンドギャップの内部にアクセプター準位を形成できる第1金属元素と、結晶シリコンのバンドギャップの内部にドナー準位を形成できる第2金属元素とを含むことを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第1金属元素が、Hf、Zr、Pt、Mo、W、NiまたはAlであり、
前記第2金属元素が、Hf、Zr、Pt、Mo、W、TiまたはTaであることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1のMISFETのゲート電極とゲート絶縁膜との界面近傍に導入された前記金属元素は、結晶シリコンのバンドギャップの内部にアクセプター準位を形成できる金属元素であり、
前記第2のMISFETのゲート電極とゲート絶縁膜との界面近傍に導入された前記金属元素は、結晶シリコンのバンドギャップの内部にドナー準位を形成できる金属元素であることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板に形成され、それぞれ膜厚が異なるゲート絶縁膜を有する複数のCMISFETとを備え、
前記複数のCMISFETのゲート絶縁膜は、酸化シリコン膜または酸窒化シリコン膜からなり、
前記複数のCMISFETのゲート電極は、前記ゲート絶縁膜上に位置するシリコン膜を含み、
前記複数のCMISFETの前記ゲート電極と前記ゲート絶縁膜との界面近傍に、1×1013〜5×1014原子/cm2の面密度で金属元素が導入されていることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板に形成された第1のCMISFETと、
前記半導体基板に形成された第2のCMISFETとを備え、
前記第1および第2のCMISFETのゲート絶縁膜は、酸化シリコン膜または酸窒化シリコン膜からなり、
前記第1および第2のCMISFETのゲート電極は、前記ゲート絶縁膜上に位置するシリコン膜を含み、
前記第1のCMISFETのゲート電極とゲート絶縁膜との界面近傍に、1×1013〜5×1014原子/cm2の面密度で金属元素が導入され、
前記第2のCMISFETのゲート電極とゲート絶縁膜との界面近傍には、金属元素が導入されていないか、あるいは前記第1のCMISFETよりも少ない面密度で金属元素が導入されていることを特徴とする半導体装置。 - nチャネル型の第1のMISFETとpチャネル型の第2のMISFETとを有する半導体装置の製造方法であって、
(a)半導体基板を準備する工程と、
(b)前記半導体基板上に前記第1および第2のMISFETのゲート絶縁膜形成用の第1絶縁膜を、酸化シリコン膜または酸窒化シリコン膜により形成する工程と、
(c)前記第1絶縁膜上に、金属元素を堆積する工程と、
(d)前記(c)工程後、前記第1絶縁膜上に前記第1および第2のMISFETのゲート電極形成用のシリコン膜を形成する工程と、
(e)前記シリコン膜をパターニングして前記第1および第2のMISFETのゲート電極を形成する工程と、
を有し、
前記(c)工程では、前記金属元素の面密度が1×1013〜5×1014原子/cm2の範囲内となるように、前記第1絶縁膜上に前記金属元素を堆積することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第1絶縁膜が酸化シリコン膜からなり、
前記(c)工程後、前記(d)工程前に、
(c1)前記第1絶縁膜に窒素を導入して前記第1絶縁膜を酸窒化シリコン膜にする工程、
を更に有することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第1および第2のMISFETのチャネル領域の不純物濃度が、1.2×1018/cm3以下であることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(c)工程では、前記金属元素とシリコンと酸素との化合物を前記第1絶縁膜上にCVD法を用いて堆積することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記金属元素が、結晶シリコンのバンドギャップの内部にドナー準位とアクセプター準位の両方を形成できる金属元素であることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記金属元素が、結晶シリコンのバンドギャップの内部にアクセプター準位を形成できる第1金属元素と、結晶シリコンのバンドギャップの内部にドナー準位を形成できる第2金属元素とを含むことを特徴とする半導体装置の製造方法。 - nチャネル型の第1のMISFETとpチャネル型の第2のMISFETとを有する半導体装置の製造方法であって、
(a)半導体基板を準備する工程と、
(b)前記半導体基板上に前記第1および第2のMISFETのゲート絶縁膜形成用の第1絶縁膜を、酸化シリコン膜または酸窒化シリコン膜により形成する工程と、
(c)前記第1絶縁膜上に前記第1および第2のMISFETのゲート電極形成用のシリコン膜を形成する工程と、
(d)前記シリコン膜と前記第1絶縁膜との界面近傍に金属元素をイオン注入する工程と、
を有することを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
(e)前記シリコン膜をパターニングして前記第1および第2のMISFETのゲート電極を形成する工程、
を更に有し、
前記第1および第2のMISFETのゲート電極と前記第1および第2のMISFETのゲート絶縁膜との界面近傍に1×1013〜5×1014原子/cm2の面密度で前記金属元素が導入されていることを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記第1および第2のMISFETのチャネル領域の不純物濃度が、1.2×1018/cm3以下であることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記金属元素が、結晶シリコンのバンドギャップの内部にドナー準位とアクセプター準位の両方を形成できる金属元素であることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記金属元素が、結晶シリコンのバンドギャップの内部にアクセプター準位を形成できる第1金属元素と、結晶シリコンのバンドギャップの内部にドナー準位を形成できる第2金属元素とを含むことを特徴とする半導体装置の製造方法。
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JP2012019016A (ja) * | 2010-07-07 | 2012-01-26 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP2012186281A (ja) * | 2011-03-04 | 2012-09-27 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2013118323A (ja) * | 2011-12-05 | 2013-06-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
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JP2016046439A (ja) * | 2014-08-25 | 2016-04-04 | 株式会社東芝 | 半導体装置およびその製造方法 |
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US7872298B2 (en) | 2006-08-03 | 2011-01-18 | Renesas Electronics Corporation | Split-gate type memory device |
US7935597B2 (en) | 2006-08-03 | 2011-05-03 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
JP2009181978A (ja) * | 2008-01-29 | 2009-08-13 | Sony Corp | 半導体装置およびその製造方法 |
JP2009239002A (ja) * | 2008-03-27 | 2009-10-15 | Fujitsu Ltd | 半導体装置の製造方法 |
US8476128B2 (en) | 2009-01-09 | 2013-07-02 | Kabushiki Kaisha Toshiba | Semiconductor device having insulated gate field effect transistors and method of fabricating the same |
JP2012019016A (ja) * | 2010-07-07 | 2012-01-26 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP2012186281A (ja) * | 2011-03-04 | 2012-09-27 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2013118323A (ja) * | 2011-12-05 | 2013-06-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8809959B2 (en) | 2011-12-05 | 2014-08-19 | Renesas Electronics Corporation | Semiconductor device and a manufacturing method thereof |
US9054102B2 (en) | 2011-12-05 | 2015-06-09 | Renesas Electronics Corporation | Semiconductor device and a manufacturing method thereof |
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TW200707708A (en) | 2007-02-16 |
US7915686B2 (en) | 2011-03-29 |
JP4860183B2 (ja) | 2012-01-25 |
TWI387096B (zh) | 2013-02-21 |
CN1870267A (zh) | 2006-11-29 |
KR101237153B1 (ko) | 2013-02-25 |
US8823110B2 (en) | 2014-09-02 |
US20060267116A1 (en) | 2006-11-30 |
US8501558B2 (en) | 2013-08-06 |
CN103354238A (zh) | 2013-10-16 |
KR20060121725A (ko) | 2006-11-29 |
US20110111566A1 (en) | 2011-05-12 |
US20130341727A1 (en) | 2013-12-26 |
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