JP2006324666A5 - - Google Patents

Download PDF

Info

Publication number
JP2006324666A5
JP2006324666A5 JP2006136761A JP2006136761A JP2006324666A5 JP 2006324666 A5 JP2006324666 A5 JP 2006324666A5 JP 2006136761 A JP2006136761 A JP 2006136761A JP 2006136761 A JP2006136761 A JP 2006136761A JP 2006324666 A5 JP2006324666 A5 JP 2006324666A5
Authority
JP
Japan
Prior art keywords
package
offset
base
base substrate
mold cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006136761A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006324666A (ja
JP5052037B2 (ja
Filing date
Publication date
Priority claimed from US11/383,407 external-priority patent/US7746656B2/en
Application filed filed Critical
Publication of JP2006324666A publication Critical patent/JP2006324666A/ja
Publication of JP2006324666A5 publication Critical patent/JP2006324666A5/ja
Application granted granted Critical
Publication of JP5052037B2 publication Critical patent/JP5052037B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2006136761A 2005-05-16 2006-05-16 オフセット集積回路パッケージオンパッケージ積層システム Active JP5052037B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US59488705P 2005-05-16 2005-05-16
US60/594,887 2005-05-16
US11/383,407 US7746656B2 (en) 2005-05-16 2006-05-15 Offset integrated circuit package-on-package stacking system
US11/383,407 2006-05-15

Publications (3)

Publication Number Publication Date
JP2006324666A JP2006324666A (ja) 2006-11-30
JP2006324666A5 true JP2006324666A5 (enExample) 2011-07-14
JP5052037B2 JP5052037B2 (ja) 2012-10-17

Family

ID=37418900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006136761A Active JP5052037B2 (ja) 2005-05-16 2006-05-16 オフセット集積回路パッケージオンパッケージ積層システム

Country Status (4)

Country Link
US (1) US7746656B2 (enExample)
JP (1) JP5052037B2 (enExample)
KR (1) KR101130330B1 (enExample)
TW (1) TWI381515B (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4828202B2 (ja) * 2005-10-20 2011-11-30 ルネサスエレクトロニクス株式会社 モジュール半導体装置
JP2007116027A (ja) * 2005-10-24 2007-05-10 Elpida Memory Inc 半導体装置の製造方法および半導体装置
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US8043343B2 (en) * 2007-06-28 2011-10-25 Zimmer Spine, Inc. Stabilization system and method
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
US7872340B2 (en) * 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
CN101562952B (zh) * 2008-04-18 2012-04-11 富葵精密组件(深圳)有限公司 线路基板、线路基板的制作方法及电路板的制作方法
KR20100009055A (ko) * 2008-07-17 2010-01-27 삼성전자주식회사 좁은 폭의 쏘우라인을 위한 인쇄회로기판 및 이를 포함하는반도체 패키지
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US8406004B2 (en) 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US7968995B2 (en) * 2009-06-11 2011-06-28 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8518749B2 (en) 2009-06-22 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US9287249B2 (en) * 2012-04-11 2016-03-15 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US9029234B2 (en) 2012-05-15 2015-05-12 International Business Machines Corporation Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking
US9041176B2 (en) 2012-10-08 2015-05-26 Qualcomm Incorporated Hybrid semiconductor module structure
KR20160123890A (ko) 2015-04-17 2016-10-26 에스케이하이닉스 주식회사 검증용 인터포저
JP2017022352A (ja) * 2015-07-15 2017-01-26 富士通株式会社 半導体装置

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5579207A (en) 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
JPH08222692A (ja) 1995-02-09 1996-08-30 Hitachi Ltd 複合形半導体装置およびその実装構造体並びにその実装方法
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US5748452A (en) 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US5986209A (en) 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
JP3644662B2 (ja) 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
JP2000208698A (ja) 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
US6207474B1 (en) 1998-03-09 2001-03-27 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
JP3767246B2 (ja) 1999-05-26 2006-04-19 富士通株式会社 複合モジュール及びプリント回路基板ユニット
JP2001044362A (ja) 1999-07-27 2001-02-16 Mitsubishi Electric Corp 半導体装置の実装構造および実装方法
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US6605875B2 (en) 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
JP2001267473A (ja) * 2000-03-17 2001-09-28 Hitachi Ltd 半導体装置およびその製造方法
US6731009B1 (en) 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
US6518659B1 (en) 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6667544B1 (en) 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US7423336B2 (en) 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
JP4601892B2 (ja) 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
US20040021230A1 (en) 2002-08-05 2004-02-05 Macronix International Co., Ltd. Ultra thin stacking packaging device
JP2004071947A (ja) 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置
KR100480437B1 (ko) * 2002-10-24 2005-04-07 삼성전자주식회사 반도체 칩 패키지 적층 모듈
US6798057B2 (en) 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP4110992B2 (ja) 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4408636B2 (ja) 2003-02-28 2010-02-03 三洋電機株式会社 回路装置およびその製造方法
JP4069771B2 (ja) * 2003-03-17 2008-04-02 セイコーエプソン株式会社 半導体装置、電子機器および半導体装置の製造方法
TW576549U (en) 2003-04-04 2004-02-11 Advanced Semiconductor Eng Multi-chip package combining wire-bonding and flip-chip configuration
US6853064B2 (en) * 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
JP3951966B2 (ja) 2003-05-30 2007-08-01 セイコーエプソン株式会社 半導体装置
JP4324773B2 (ja) 2003-09-24 2009-09-02 セイコーエプソン株式会社 半導体装置の製造方法
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
JP2005123463A (ja) * 2003-10-17 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器
US7095104B2 (en) 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
US7091581B1 (en) * 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
JP2006186136A (ja) * 2004-12-28 2006-07-13 Toshiba Corp 両面部品実装回路基板及びその製造方法
US7312519B2 (en) 2006-01-12 2007-12-25 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7420269B2 (en) 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7772683B2 (en) 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7635913B2 (en) 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

Similar Documents

Publication Publication Date Title
JP5052037B2 (ja) オフセット集積回路パッケージオンパッケージ積層システム
JP2006324666A5 (enExample)
US6861288B2 (en) Stacked semiconductor packages and method for the fabrication thereof
TWI499032B (zh) 積體電路層疊封裝件堆疊系統
US8541872B2 (en) Integrated circuit package system with package stacking and method of manufacture thereof
US8232658B2 (en) Stackable integrated circuit package system with multiple interconnect interface
US8004093B2 (en) Integrated circuit package stacking system
JP4402074B2 (ja) オフセット集積回路パッケージオンパッケージ積層システムおよびその製造方法
US7312519B2 (en) Stacked integrated circuit package-in-package system
US7388280B2 (en) Package stacking lead frame system
US7915724B2 (en) Integrated circuit packaging system with base structure device
US8124451B2 (en) Integrated circuit packaging system with interposer
US8247894B2 (en) Integrated circuit package system with step mold recess
US8633100B2 (en) Method of manufacturing integrated circuit packaging system with support structure
US20110089552A1 (en) Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof
US20070001296A1 (en) Bump for overhang device
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
KR20090063090A (ko) 플래시-방지 구조체를 구비한 오프셋 적층형 집적회로 패키지 시스템
US20080315406A1 (en) Integrated circuit package system with cavity substrate
US7683467B2 (en) Integrated circuit package system employing structural support
US7759783B2 (en) Integrated circuit package system employing thin profile techniques
US7727816B2 (en) Integrated circuit package system with offset stacked die