JP2006319264A - Method for manufacturing memory element, and method for manufacturing storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a memory element having proper characteristics by suppressing variation in characteristics such as the threshold voltage in storing/reading/writing information. <P>SOLUTION: A thin film 2 for memory is sandwiched between a first electrode 1 and a second electrode 4 and the thin film 2 contains a rare earth oxide layer. When a memory element 10 containing any one element selected from Ag, Cu and Zn is manufactured in the thin film 2 for memory or in a layer 3 touching the thin film 2, the thin film 2 for memory is formed by reactive sputtering method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a memory element capable of recording information, and a method for manufacturing a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, flash memories, FeRAMs (ferroelectric memories), MRAMs (magnetic storage elements), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.
Accordingly, extensive research and product development have been conducted on the various types of nonvolatile memories described above.

However, the various nonvolatile memories described above have advantages and disadvantages.
Flash memory has a high degree of integration, but is disadvantageous in terms of operation speed.
FeRAM is limited in microfabrication for high integration and has a problem in the manufacturing process.
MRAM has a problem of power consumption.

Therefore, a new type of storage element has been proposed that is particularly advantageous for the limit of microfabrication of the memory element.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. By diffusing, electrical characteristics such as resistance value or capacitance of the ionic conductor change.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, more specifically, a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Ag, Cu, and Zn (see Patent Document 1).

Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104)

  In the configuration of the memory element described above, the threshold voltage when the resistance value of the memory element transitions and the variation of the threshold voltage, the initial resistance value of the memory element, the resistance value such as the resistance value of the high resistance state after the transition, and the Variations have a significant effect on memory operating characteristics.

In the structure of the memory element described above, for example, when manufacturing a large-capacity memory having a large-scale cell array, so-called “writing” that transitions from a high-resistance state to a low-resistance state to prevent erroneous recording. The threshold value of the operation, or conversely, the threshold value of the so-called “erase” operation for transitioning from the low resistance state to the high resistance state needs to be kept within a certain range. If it is out of a certain range, writing and erasing errors are caused.
These threshold values vary even in the same memory element due to repeated writing / erasing, or the threshold voltage changes with each repetition, or the threshold voltage for writing is different for each memory element (that is, for each memory cell of the memory). If there are variations in threshold values, such as different values, stable memory operation becomes difficult.
In addition, when the threshold voltage is too high, high-speed operation becomes difficult, or the voltage drive range of the selection MOS transistor for selecting the memory cell is exceeded, and the operation becomes impossible. Exists.

  In order to solve the above-described problems, the present invention makes it possible to manufacture a storage element and a storage device having appropriate characteristics by suppressing variation in characteristics such as threshold voltage in recording, reading, and writing of information. The present invention provides a method for manufacturing a memory element and a method for manufacturing a memory device.

The method for manufacturing a memory element according to the present invention includes a memory thin film sandwiched between a first electrode and a second electrode, and the memory thin film includes an oxide layer containing a rare earth element. In manufacturing a memory element in which any element selected from Ag, Cu, Zn is contained in the memory thin film or a layer in contact with the memory thin film, an oxide layer containing a rare earth element Is formed by a reactive sputtering method using a rare earth metal target.
A method for manufacturing a memory device according to the present invention includes the memory element, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. When manufacturing the memory device, the memory element is manufactured by the method for manufacturing the memory element of the present invention.

  In the memory element according to the manufacturing method of the present invention, the memory thin film is sandwiched between the first electrode and the second electrode, and the memory thin film has an oxide layer containing a rare earth element. The resistance state of the memory thin film is changed by the configuration in which any element selected from Ag, Cu, and Zn is contained in the memory thin film or the layer in contact with the memory thin film. It is possible to record information by using this.

Specifically, for example, when a positive potential is applied to one electrode side and a voltage is applied to the memory element, Ag, Cu and Zn are ionized and diffused into the memory thin film, and at the other electrode side part The resistance value of the memory thin film is lowered by being deposited in combination with electrons or by forming an impurity level in the insulating film that remains in the memory thin film, so that information can be written. become.
Further, from this state, when a negative potential is applied to one electrode side and a negative voltage is applied to the memory element, Ag, Cu, Zn deposited on the other electrode side is ionized again to return to the original state. By returning, the resistance value of the memory thin film returns to its original high state, and the resistance value of the memory element also increases, so that the recorded information can be erased.

  And since the memory thin film has an oxide layer containing a rare earth element, the resistance value in the high resistance state can be made relatively high. In addition, since rare earth elements are thermally stable, information can be recorded stably with a very small current.

According to the method for manufacturing a memory element of the present invention described above, an oxide layer containing a rare earth element is formed by a reactive sputtering method using a rare earth element metal target. Can be formed with a substantially uniform oxidation state.
Thereby, the nonuniformity of the oxide layer of the memory thin film can be reduced.
In the memory element according to the present invention, the threshold voltage when the resistance value changes due to the ionization behavior excited by the applied voltage and the operation of ions greatly depends on the thickness of the oxide layer and the formation conditions thereof. By reducing the non-uniformity of the oxide layer of the memory thin film, it is possible to suppress variations in threshold voltage during writing and erasing of the memory element.
As a result, a memory element having excellent repetitive characteristics of writing and erasing operations can be manufactured.

  In addition, in a memory device having a large number of memory cells including memory elements, it is possible to suppress variations in threshold voltages for recording and erasing by reducing non-uniformity of the oxide layer in the memory elements of each memory cell. Become.

According to the present invention described above, it is possible to suppress variations in threshold voltage in writing and erasing to the storage element by reducing non-uniformity of the oxide layer of the memory thin film. A memory element and a memory device having characteristics can be manufactured stably and with high yield.
In addition, since it becomes possible to reduce variations in threshold voltage, it is possible to reduce the occurrence of errors in writing and erasing information, so that a storage device capable of stable memory operation can be realized. It becomes possible.
In addition, since a memory element having excellent repetitive characteristics of writing and erasing operations can be manufactured, a memory device having excellent information retention durability and high reliability can be realized.

Furthermore, the memory element according to the present invention can be manufactured by materials and manufacturing methods used in a normal MOS logic circuit manufacturing process.
Therefore, according to the present invention, a storage element and a storage device having appropriate characteristics can be manufactured at a low cost, and an inexpensive storage device can be provided.

FIG. 1 shows a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element according to the manufacturing method of the present invention.
In the memory element 10, for example, a lower electrode 1 that is a connection portion with a CMOS circuit portion is formed on a silicon substrate (see FIG. 2) on which a CMOS circuit is formed. A thin film 2 is formed, a layer 3 containing Ag, Cu, and Zn is formed on the memory thin film 2, and an upper electrode 4 is formed thereon.

For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.
In addition, when using an electrode material such as Cu that can be multiplied by ion conduction in an electric field, the Cu electrode is coated with a material that is difficult to ionize or thermally diffuse such as W, WN, TiN, and TaN. Also good.

The memory thin film 2 includes one or more kinds of rare earth elements selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y among rare earth elements. A thin film made of an oxide of an element (hereinafter referred to as a rare earth oxide thin film) is used.
Since this rare earth oxide thin film 2 is usually an insulating material, it is thinned to a thickness of 0.5 nm to 3 nm, for example, so that a current can flow.
The composition of oxygen in the rare earth oxide thin film 2 is usually a composition of RE ₂ O ₃ with respect to the rare earth element (RE). Here, the composition is an amorphous film having an electrical conductivity lower than the conductivity of the semiconductor region. Since it is sufficient if it has properties, it is not necessarily limited to such a composition. For example, REOx (0.5 <x ≦ 1.5) may be used.

  In addition, the rare earth oxide thin film 2 includes, for example, other than rare earth elements such as Ge, Si, Te, S, Se, Sb, Ti, W, Cu, Ag, Zn, Fe, Co, P, N, and H. An element may be contained in advance.

  The rare earth oxide thin film 2 made of the above-described material has a characteristic that impedance changes when a voltage pulse or a current pulse is applied.

The layer 3 on the rare earth oxide thin film (memory thin film) includes at least one of Ag, Cu, and Zn, that is, a metal element that serves as an ion source to be described later. Hereinafter, the layer 3 is referred to as an ion source layer 3.
The ion source layer 3 includes, for example, GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, etc. containing Ag, Cu, Zn containing a chalcogenide element of Te, Se, S, a film, an Ag film, and an Ag alloy. A film, a Cu film, a Cu alloy film, a Zn film, a Zn alloy film, or the like can be used.
For example, when a GeTeCu film is used for the ion source layer 3, the film thickness may be set to 5 nm to 50 nm, for example. In addition to the above composition, a composition containing a rare earth element used for the rare earth oxide thin film 2, for example, CuGeTeGd may be used.

  Further, as shown in FIG. 1, the ion layer 3 may have a stacked structure of a layer 3A containing a chalcogenide element and a layer 3B supplementing a necessary ion source element (Ag, Cu, Zn). For example, in the case where the layer 3B that supplements Ag, Cu, and Zn is provided, the thickness of the layer 3B may be set to 2 nm to 30 nm, for example.

  As with the lower electrode 1, a normal semiconductor wiring material is used for the upper electrode 4.

  The memory element 10 of this embodiment can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 3 containing Ag, Cu, and Zn, and a positive voltage is applied to the memory element 10 so that the lower electrode 1 side becomes negative. . As a result, Ag, Cu, Zn is ionized from the ion source layer 3 and diffuses in the rare earth oxide thin film 2 and is combined with electrons on the lower electrode 1 side to be deposited, or the rare earth oxide thin film 2 It stays diffused inside.
Then, a current path containing a large amount of Ag, Cu, Zn is formed inside the rare earth oxide thin film 2 or a large number of defects due to Ag, Cu, Zn are formed inside the rare earth oxide thin film 2, thereby The resistance value of the oxide thin film 2 becomes low. Each layer other than the rare earth oxide thin film 2 originally has a lower resistance value than the resistance value of the rare earth oxide thin film 2 before recording. The resistance value can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to an erasable storage device, so-called RAM or EEPROM, etc., but in the erasing process, the ion source layer 3 containing Ag, Cu, Zn, for example, is negatively charged. A negative voltage is applied to the memory element 10 by applying a potential (−potential) so that the lower electrode 1 side becomes positive. As a result, Ag, Cu, and Zn constituting the current path or impurity level formed in the rare earth oxide thin film 2 are ionized, move in the rare earth oxide thin film 2, and return to the ion source layer 3 side. .
Then, the current path or defect due to Ag, Cu, Zn disappears from within the rare earth oxide thin film 2, and the resistance value of the rare earth oxide thin film 2 increases. Since each layer other than the rare earth oxide thin film 2 originally has a low resistance value, by increasing the resistance value of the rare earth oxide thin film 2, the resistance value of the entire memory element 10 can also be increased.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  The rare earth oxide thin film 2 is preferably made of a material exhibiting a high resistance value in an initial state before recording and a state after erasing.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording, rather than the cell size of the memory element 10 and the material composition of the rare earth oxide thin film 2, and the initial resistance. When the value is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio of the initial resistance value to the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance after recording is It is sufficient if the value is 50Ω, or the resistance value before recording is 100 kΩ and the resistance value after recording is 50 kΩ, and the initial resistance value of the rare earth oxide thin film 2 is set to satisfy such a condition. Is done. The resistance value of the rare earth oxide thin film 2 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials.

  According to the configuration of the memory element 10 of the above-described form, the rare earth oxide thin film 2 made of an oxide containing a rare earth element and the ion source layer containing Ag, Cu, Zn between the lower electrode 1 and the upper electrode 6. For example, when a positive voltage (+ potential) is applied to the ion source layer 3 side including Ag, Cu, and Zn so that the lower electrode 1 side becomes negative, for example, By forming a current path containing a large amount of Ag, Cu, Zn in the rare earth oxide thin film 2 or by forming many defects due to Ag, Cu, Zn in the rare earth oxide thin film 2, the rare earth The resistance value of the oxide thin film 2 becomes low, and the resistance value of the entire memory element 10 becomes low. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored by utilizing the change in resistance value of the memory element 10, particularly the change in resistance value of the rare earth oxide thin film 2, even when the memory element 10 is miniaturized, the information Recording and storing of recorded information becomes easy.

  Further, for example, when used in a storage device that can be erased in addition to recording such as RAM or EEPROM, the storage element 10 in the state after recording described above includes, for example, ions containing Ag, Cu, and Zn. A negative voltage (−potential) is applied to the source layer 3 so that the lower electrode 1 side becomes positive. As a result, the current path or defect due to Ag, Cu, Zn formed in the rare earth oxide thin film 2 disappears, the resistance value of the rare earth oxide thin film 2 increases, and the resistance value of the entire memory element 10 increases. Becomes higher. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

Furthermore, according to the memory element 10 of this embodiment, the lower electrode 1, the rare earth oxide thin film 2, the ion source layer 3, and the upper electrode 4 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

In the memory element 10 of the above-described form, the ion source layer 3 (3A, 3B) includes Ag, Cu, Zn and does not include the upper electrode 4. However, other configurations are possible.
In the ion source layer 3 (3A, 3B) of FIG. 1, the layer 3A containing a chalcogenide element contains a chalcogenide element of Te, Se, S, but does not contain an ion source element of Ag, Cu, Zn. For example, a configuration using a material such as GeSbTe, GeTe, GeSe, GeS, SiGeTe, and SiGeSbTe is also possible.
Further, the order of lamination of the rare earth oxide thin film 2 and the ion source layer 3 is reversed to form the ion source layer 3 containing Ag, Cu, Zn on the lower electrode 1, and the rare earth oxide thin film 2 is formed thereon. A configuration in which the upper electrode 4 is formed thereon is also possible.
Furthermore, a configuration in which only the lower electrode 1 includes Ag, Cu, Zn as the ion source, or a configuration in which the lower electrode 1 and the upper electrode 4 include Ag, Cu, Zn as the ion source may be employed. Further, the ion source layer 3 can be used as it is as the upper electrode.

A memory device (memory device) can be configured by arranging a large number of the memory elements 10 in the above-described form in a matrix.
For each memory element 10, a wiring connected to the lower electrode 1 side and a wiring connected to the upper electrode 4 side are provided. For example, each memory element 10 is disposed near the intersection of these wirings. What should I do? That is, a bit line (BL) and a word line (WL) are provided, and each storage element may be arranged near the intersection of these wirings.

Specifically, for example, the lower electrode 1 is formed in common in the memory cell in the row direction, and the wiring connected to the upper electrode 4 is formed in common in the memory cell in the column direction to constitute the memory device. Conceivable.
Then, by selecting the lower electrode 1 and the wiring through which a current is applied by applying a potential, a memory cell to be recorded is selected, and a current is passed through the storage element 10 of the memory cell to record information. The recorded information can be erased.

Further, for example, it is conceivable to form a memory device by forming wirings connected to the upper electrode 4 in common for the entire memory cell array.
FIG. 2 and FIG. 3 show schematic configuration diagrams of an embodiment of the memory cell array configured as described above. 2 is a cross-sectional view, and FIG. 3 is a plan view.

  As shown in FIG. 2 and FIG. 3, in this memory cell array, the memory elements 10 constituting each memory cell share the layers of the memory thin film 2, the ion source layer 3, and the upper electrode 4 throughout the memory cell. Yes. In other words, each storage element 10 includes the same layer of storage thin film 2, ion source layer 3, and upper electrode 4.

The upper electrode 4 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. A memory element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 2, each storage element 10 constituting each memory cell of the memory cell array is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the memory element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. This metal wiring layer 16 is connected to a bit line BL (see FIG. 3) which is the other address wiring of the memory element.

  In FIG. 3, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 3, reference numeral 21 denotes a contact portion that communicates with the lower electrode 1 of the memory element 10, and 22 denotes a contact portion that communicates with the bit line BL.

The memory cell array shown in FIGS. 2 and 3 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.

Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 4 (plate electrode PL), the resistance value of the memory element 10 transitions to a low resistance state. To do. Thereby, information can be recorded in the memory element 10 of the selected memory cell.
Further, by applying a field voltage, which is a positive potential compared to the potential of the upper electrode 4 (plate electrode PL), to the lower electrode 1, the resistance value of the memory element 10 transitions to the high resistance state again. Thereby, the recorded information can be erased from the storage element 10 of the selected memory cell.

In order to read out recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the memory element 10 is changed. Different currents or voltages are detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the memory element 10 changes.

The memory element 10 having the above-described form can easily record and read information, and has an excellent characteristic that variation in write and erase voltage thresholds is particularly small.
Further, even when the memory element 10 having the above-described form is miniaturized, it becomes easy to record information and hold recorded information.
Therefore, by configuring the memory device using the memory element 10 having the above-described form, the memory device can be integrated (densified) or downsized.

  Subsequently, a method for manufacturing the memory element 10 and the memory cell array shown in FIGS. 1 to 3 will be described as an embodiment of the method for manufacturing the memory element of the present invention and the method for manufacturing the memory device of the present invention.

  The lower electrode 1 made of, for example, a W film is formed above the semiconductor substrate 11 on which the CMOS circuit such as the selection transistor Tr is formed via the plug layer 15, the metal wiring layer 16, and the plug layer 17. Further, the bit line BL is formed by the metal wiring layer 16.

Next, if necessary, after removing oxides and the like on the surface of the lower electrode 1 by reverse sputtering or the like, a rare earth oxide thin film 2, for example, a Gd ₂ O ₃ film is formed.

Next, after a layer 3A containing a chalcogenide element, for example, a CuGeTeGd film, is formed by DC magnetron sputtering, a layer 3B, for example, a Cu film, is formed to supplement the ion source, and the ion source layer 3 is formed from these laminated films. .
Next, for example, a W film is formed as the upper electrode 4.

Next, the upper electrode 4, the ion source layer 3, and the rare earth oxide thin film 2 are patterned so as to remain in the memory cell array portion by, for example, plasma etching or the like. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
If necessary, a wiring for supplying a common potential is further connected to the upper electrode 4 (plate electrode PL).
In this manner, the memory cell array shown in FIGS. 1 to 3 can be manufactured.

In the present embodiment, in particular, a method of introducing oxygen or the like into the rare earth oxide thin film 2 constituting the memory thin film together with an inert gas such as argon during sputtering using a metal target, that is, so-called It forms using the reactive sputtering method (reactive sputtering).
As the inert gas used at this time, any one gas or a mixture of two or more of argon, krypton, and xenon can be used.
Further, as the gas used together with the inert gas, it is sufficient if oxygen is mainly contained, and in addition to this, halogen gas such as nitrogen, fluorine, chlorine, bromine, and organic gas containing them can be used.

When a Gd oxide thin film is formed as the rare earth oxide thin film, for example, a Gd target is used as a metal target, and argon and oxygen as inert gases are used as an introduction gas, and the Gd oxide thin film is used. Form.
As specific conditions of the reactive sputtering method in this case, for example, the flow rate ratio of argon and oxygen may be 3: 1, and the chamber pressure may be 3 mTorr.

Further, the mixing ratio (flow rate ratio) of the introduced gas is desirably half or more of the inert gas.
This is because the oxygen composition of the rare earth oxide thin film can be controlled by the mixing ratio of an inert gas and a gas such as oxygen, and a rare earth oxide film having a low oxygen composition is formed by lowering the mixing ratio of the oxygen gas. Because it can.
Moreover, the insulating characteristics can be changed by mixing nitrogen gas or the like.
That is, in order to form a rare earth oxide thin film having a certain thickness and a small resistance value, the flow rate ratio of oxygen gas may be reduced, or nitrogen gas or the like may be further mixed and adjusted.

According to the manufacturing method of the above-described embodiment, oxygen or the like is introduced into the rare earth oxide thin film 2 constituting the memory thin film together with an inert gas such as argon as an introduction gas during sputtering using a metal target. It is possible to form the rare earth oxide thin film 2 in a substantially uniform oxidation state by forming the memory element 10 and the memory cell array by using a method, that is, a so-called reactive sputtering method (reactive sputtering). it can.
Thereby, the nonuniformity of the rare earth oxide thin film 2 of the memory thin film can be reduced.

In the memory element 10 according to the present embodiment, the threshold voltage when the resistance value changes due to the ionization behavior excited by the applied voltage and the operation of the ions is large depending on the thickness and oxidation state of the rare earth oxide thin film 2. Therefore, by reducing the non-uniformity of the rare earth oxide thin film 2, it is possible to suppress variations in threshold voltage during writing and erasing of the memory element 10.
This makes it possible to manufacture the memory element 10 having excellent repetitive characteristics of writing and erasing, so that a memory device having excellent information retention durability and high reliability can be realized.

Further, the memory element 10 according to the present embodiment can be manufactured by a material or a manufacturing method used in a normal MOS logic circuit manufacturing process.
Therefore, with the manufacturing method of this embodiment, a storage element and a storage device with appropriate characteristics can be manufactured at low cost, and an inexpensive storage device can be provided.

  Accordingly, it becomes possible to suppress variation in threshold voltage in writing and erasing of the memory element 10, and thus the memory element 10 and the memory device having appropriate characteristics can be manufactured stably and with high yield.

(Example)
Next, the memory element 10 and the memory cell array having the above-described form were actually manufactured, and the characteristics were examined.

<Sample 1>
First, as shown in FIGS. 2 and 3, a MOS transistor Tr was formed on the semiconductor substrate 11.
Thereafter, an insulating layer was formed covering the surface.
Next, a via hole was formed in this insulating layer.
Subsequently, the inside of the via hole was filled with an electrode material made of W (tungsten) by CVD.
Next, the surface was planarized by CMP.
Then, by repeating these steps, the plug layer 15, the metal wiring layer 16, the plug layer 17, and the lower electrode 1 were formed, and the lower electrode 1 was further patterned for each memory cell.

Next, in order to remove the lower electrode 1 formed on the semiconductor substrate 11 on which the CMOS circuit including the MOS transistor Tr is formed, that is, the oxide on the upper surface of the tungsten plug (W plug), reverse sputtering using an RF power source is performed. By etching, 5 nm was etched.
At this time, it is desirable that the surface of the lower electrode 1 is ideally formed at the same height as the surrounding insulating layer and is flattened.

Then, a Gd oxide layer having a thickness of 1 nm was formed on the lower electrode 1 as a rare earth oxide thin film 2 constituting a memory thin film by a reactive sputtering method using a DC magnetron sputtering apparatus.
The specific conditions for the reactive sputtering method were a Gd target, a chamber internal pressure of 3 mTorr, and a mixing ratio of oxygen and argon of 1: 3.

Next, a CuGeTeGd film having a thickness of 20 nm was deposited as a layer 3A containing a chalcogenide element, and then a Cu film having a thickness of 12 nm was deposited as a layer 3B to supplement the ion source. The ion source layer 3 was formed by a laminated film of these layers 3A and 3B.
Further, a W film was formed as the upper electrode 4 on the ion source layer 3.
In this way, a laminated film constituting the memory element 10 shown in FIG. 1 was formed.

Subsequently, heat treatment was performed at 265 ° C. for 4 hours in a vacuum heat treatment furnace.
Thereafter, the rare earth oxide thin film 2, the ion source layer 3, and the upper electrode 4 formed on the entire surface were patterned so as to remain over the entire memory cell array portion (memory portion).

Further, etching was performed on the surface of the upper electrode 4 so that a contact portion connected to an external circuit for applying an intermediate potential (Vdd / 2) was exposed.
In this manner, a memory cell array including the memory element 10 shown in FIGS.

<Sample 2 and Sample 3>
When the rare earth oxide thin film 2 constituting the memory thin film is formed on the lower electrode 1 by reactive sputtering, the pressure in the chamber is 5 mTorr, the mixing ratio of oxygen and argon is 1: 5, In the same manner as Sample 1, a sample of the memory cell array was prepared and used as Sample 2.
Further, when the rare earth oxide thin film 2 constituting the memory thin film is formed on the lower electrode 1 by the reactive sputtering method, the pressure in the chamber is set to 5 mTorr, and the mixing ratio of oxygen and argon is set to 1:10. Otherwise, the sample of the memory cell array was prepared in the same manner as Sample 1, and Sample 3 was obtained.

(Comparative example)
<Sample 4>
After etching the surface of the lower electrode 1 by reverse sputtering about 5 nm, a Gd metal layer was formed with a film thickness of 0.8 nm.
Thereafter, the Gd oxide layer was formed by oxidizing the Gd metal layer by exposure to oxygen plasma. Others were made in the same manner as Sample 1, and a sample of the memory cell array was prepared as Sample 4.

(Characteristic evaluation)
For example, with respect to the memory element 10 of the sample 1, the upper wiring connected to the upper electrode 4 is grounded to an intermediate potential of Vdd / 2, and 2.5 V is applied to the gate electrode of the selected memory cell, that is, the word line WL. To the electrode connected to the one not connected to the memory element 10 among the source / drain 13 of the transistor Tr, that is, the bit line BL, 0V to + 1.25V, + 1.25V to -1. A voltage of 0 V, −1.0 V to 0 V was applied for insertion, and these cycles were repeated a total of 4 times.

FIG. 4 shows IV characteristics of the memory element of Sample 1 obtained as described above.
Further, the VR loop was calculated from the IV characteristics. The calculated VR loop is shown in FIG. 4 and 5, the broken line indicates the first loop, and the solid line indicates the second and subsequent loops.

4 and 5, the initial resistance immediately after device fabrication is high in resistance value, the memory device is in the OFF state, voltage is applied to the bit line, and the voltage at the lower electrode of the device increases negatively with respect to the upper electrode. By doing this (in the positive direction in the figure), the current abruptly increases above the threshold voltage (Vth) of 0.7 to 1.4V. That is, it can be seen that the resistance value of the memory element is lowered and the memory element shifts to the ON state. Thereby, information is recorded.
On the other hand, even if the voltage is decreased thereafter, the constant resistance value is maintained, that is, the storage element is kept in the ON state, and the recorded information is retained. Further, the same operation is performed even if the subsequent three record erasures are performed.

  Also, as shown in the figure, when a reverse polarity voltage V, that is, a positive potential (+ potential) is applied to the lower electrode, a positive potential of V = −0.6 V or more is applied, and then it is returned to 0 V again. Thus, it was confirmed that the resistance value of the memory element returned to the high resistance state in the initial OFF state. That is, it can be seen that the information recorded in the memory element can be erased by applying a negative voltage.

Next, for each of Samples 1 to 4, the same measurement was performed on 24 elements formed on the same substrate.
As an example, the results of VR measurement of 24 elements of Sample 1 are shown in FIG.

Next, from the fourth loop, the threshold value of the writing voltage and the threshold value of the erasing voltage were obtained, and the variation of the threshold value of each voltage was obtained.
In the calculation method, the standard deviation of the voltage threshold value of 24 elements was obtained, and the value (%) obtained by dividing the standard deviation value by the average value of the voltage threshold value was used as the variation value.
Table 1 shows the measurement results of the voltage threshold variation of Samples 1 to 4.

Next, the resistance value before writing and the resistance value after writing were obtained from the first and fourth VR loops, and the variation of the respective resistance values was obtained.
As a calculation method, a standard deviation of resistance values of 24 elements was obtained, and a value (%) obtained by dividing the standard deviation by the average of the resistance values was used as a variation value.
Table 2 shows measurement results of variations in resistance values of Samples 1 to 4.

From Table 1, in Samples 1 to 3, which are examples of the present invention, when attention is paid to variations in the threshold voltage of the erase operation, it is about 20% to 25%.
However, in the sample 4 of the comparative example in which the Gd oxide layer is formed by plasma oxidation, the variation is 37.6%, which is larger than each sample of the example.

Further, from Table 2, focusing on the resistance value variation at the time of the fourth writing and erasing operation, the resistance value variation at the time of the erasing operation is particularly large at 35.6% in the sample 4 of the comparative example. Yes.
On the other hand, all of Samples 1 to 3 which are examples of the present invention are as small as 3% or less.

  Therefore, it can be seen that in the sample in which the rare earth oxide thin film 2 is formed by reactive sputtering as in the example of the present invention, the variation in the operation threshold voltage and the variation in the resistance value after repeated recording and erasing can be reduced. That is, the variation characteristic when the write / erase operation is repeatedly performed is excellent.

Although the cause is not necessarily clear, the following is presumed.
When the rare earth metal film is plasma oxidized, the crystal grain boundaries of the rare earth metal film are preferentially oxidized during the oxidation process, so that an oxide layer with a non-uniform oxidation state is formed. In the process, ionic conduction occurs non-uniformly.
This is probably because when the rare earth oxide thin film is formed by reactive sputtering, the oxygen concentration gradient in the depth direction or in-plane direction of the oxide layer is difficult to occur, so that Cu ion conduction occurs uniformly. It is done.

A memory device (memory device) can be configured by arranging a large number of memory elements, for example, in a column shape or a matrix shape, using the memory element according to the present invention as shown in the above-described embodiments and the like. it can.
At this time, a memory cell is configured by connecting a MOS transistor or a diode for selecting the element to each memory element as necessary.
Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.

  The memory element according to the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. Any memory form such as (memory) can be applied.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of one form of the memory element which concerns on the manufacturing method of this invention. It is a schematic block diagram (sectional drawing) of the memory cell array using the memory element of FIG. FIG. 2 is a schematic configuration diagram (plan view) of a memory cell array using the memory element of FIG. 1. 4 is a measurement result of an IV characteristic curve of Sample 1. 3 is a measurement result of a VR characteristic curve of Sample 1. FIG. 5 is a diagram in which the VR characteristic curves of 24 elements of Sample 1 are superimposed.

Explanation of symbols

  1 Lower electrode, 2 memory thin film (rare earth oxide thin film), 3 ion source layer, 4 upper electrode, 10 memory element, Tr MOS transistor, BL bit line, WL word line, PL plate electrode

Claims (4)

A memory thin film is sandwiched between the first electrode and the second electrode,
The memory thin film has an oxide layer containing a rare earth element,
A method of manufacturing a memory element in which any element selected from Ag, Cu, Zn is contained in the memory thin film or in a layer in contact with the memory thin film,
The method for manufacturing a memory element, wherein the oxide layer containing the rare earth element is formed by a reactive sputtering method using the metal target of the rare earth element.   The gas flow rate of oxygen and argon is larger when using a mixed gas of oxygen and argon as a sputtering gas when forming the rare earth element-containing oxide layer. 2. A method for manufacturing a memory element according to 1.   2. The information storage device according to claim 1, wherein the memory element is configured to record information by applying a voltage pulse or a current pulse to the memory thin film to change an impedance of the memory thin film. A method for manufacturing the memory element according to the above. A memory thin film is sandwiched between the first electrode and the second electrode, and the memory thin film includes an oxide layer containing a rare earth element, or in the memory thin film, or A memory element containing any one element selected from Ag, Cu, and Zn in a layer in contact with the memory thin film;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A method of manufacturing a storage device in which a large number of the storage elements are arranged,
A method for manufacturing a memory device, comprising: forming an oxide layer containing the rare earth element of the memory element by a reactive sputtering method using a metal target of the rare earth element.

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