JP2008140907A - Electronic apparatus and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an electronic apparatus with MIM (metal-insulator-metal) devices having hysteresis disposed, at a high yield. <P>SOLUTION: The electronic apparatus comprises a substrate dummy patterns formed on the substrate, extending in a first direction parallel to each other; a pair of lower electrode patterns, made of first and second conductive sidewall films each formed on first and second sidewall surfaces opposite each other on the dummy patterns and each extending in the first direction; a hysteresis film made of metal oxide and formed on the substrate so as to cover the dummy patterns and the pair of lower electrode patterns; and an upper electrode pattern, made of a conductive film and formed on the hysteresis film so as to extend in a second direction different from the first direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to an electronic device, and more particularly to an electronic device including a MIM element having hysteresis and a manufacturing method thereof.

  With the progress of miniaturization technology, ultra-miniaturized semiconductor devices having a gate length of several nanometers are now in the field of practical use.

  On the other hand, the manufacturing cost of such an ultra-miniaturized semiconductor device is rapidly increasing, and further miniaturization is predicted not only in terms of manufacturing technology but also in terms of cost.

On the other hand, in a conventional MIM (metal-insulator-metal) capacitor, particularly an MOM (metal-oxide-metal) capacitor using an oxide film as a capacitor insulating film, when a voltage exceeding a certain forming voltage is applied, the capacitor insulating film becomes NiO. Hysteresis characteristics are known to be obtained even with non-ferroelectric films such as films, Fe ₂ O ₃ films, and CuO films, and ultrafine memories and switches can be constructed using these hysteresis characteristics Has been studied.
Japanese Patent Laid-Open No. 2003-218211

  1A to 1C show a configuration of an electronic device 10 including a PIM / NiO / Pt structure MIM element according to the related art of the present invention. 1A is a plan view of the electronic device 10, FIG. 1B is a cross-sectional view taken along the line AA 'in FIG. 1A, and FIG. 1A shows a cross-sectional view along the line BB ′.

  Referring to FIGS. 1A to 1C, a Pt film 14 constituting lower electrode patterns 14A to 14D is formed on a silicon substrate 11 with a silicon oxide film 12 having a thickness of 100 nm interposed therebetween. A NiO film 15 is formed on the silicon oxide film 12 as a capacitor insulating film so as to cover the lower electrode patterns 14A to 14D.

  Further, upper electrodes 16A to 16D each made of a Pt film 16 are formed on the NiO film 15 so as to intersect the lower electrodes 13A to 13D in a plan view.

  In such a configuration, in FIG. 1B, MIM elements surrounded by circles are formed corresponding to the intersections of the lower electrode patterns 14A to 14A and the upper electrodes 16A to 16D. The MIM element has hysteresis as shown schematically in FIG. 2 in its IV characteristics.

  Referring to FIG. 2, the value of the current I flowing through the MIM element increases with the applied voltage V when the applied voltage V is increased from 0V to positive polarity, but increases rapidly when the voltage reaches a certain voltage Vf ( When the resistance value suddenly decreases) and then the applied voltage is decreased, a loop is drawn to return to the original value. When the applied voltage is increased from 0V in a negative polarity, a similar loop appears symmetrically with respect to the origin where the applied voltage V is 0V, and when the voltage reaches a certain voltage −Vf, the value of the current I rapidly decreases. (The resistance value increases rapidly.) As a result, each of the MIM elements shown in FIGS. 1A to 1C can take two states, a high resistance state with high electrical resistance and a low resistance state with low electrical resistance.

  Although the mechanism by which the hysteresis loop as shown in FIG. 2 appears has not yet been elucidated, the hysteresis loop in FIG. 2 means that the MIM element in FIG. 1 can be programmed by applying a voltage higher than the voltage Vf. Thus, for example, in an electronic device such as a crossbar switch in which MIM elements are arranged in a matrix as shown in FIG. 3, the switching operation can be controlled, and various logical operations such as AND and OR are performed. It means that you can. In the example of FIG. 3, only the MIM element surrounded by a circle is in the low resistance state.

  By the way, in an electronic device such as a crossbar switch in which the MIM elements shown in FIGS. 1A to 1C are arranged in a matrix, as shown in the cross-sectional view of FIG. Since the upper electrode patterns 16A to 16D cover the patterning 14A to 14D and the upper electrode patterns 16A to 16D cover the patterning 14A to 14D, the hysteresis film 15c disappears at the corners surrounded by circles in FIG. There is a possibility that the electrode pattern may be short-circuited, or the film thickness of the upper electrode pattern may be reduced and disconnected.

  1A to 1C, the lower electrode patterns 14A to 14D and the upper electrode patterns 16A to 16D are made of white metal such as Pt, Rh, Ru, and Ir. Although it is made of a noble metal, such a material is expensive and has a problem that patterning by dry etching is difficult and the manufacturing cost increases.

  According to one aspect, the present invention provides a substrate, a dummy pattern formed on the substrate so as to extend in a first direction in parallel to each other, and first and second opposing surfaces of the dummy pattern. A pair of lower electrode patterns each formed of first and second conductive side wall films respectively formed on the side wall surfaces and extending in the first direction, and the dummy pattern and the pair of lower portions on the substrate A hysteresis film made of a metal oxide formed so as to cover the electrode pattern, and an upper part made of a conductive film formed on the hysteresis film so as to extend in a second direction different from the first direction An electronic device comprising an electrode pattern and an electrode pattern is provided.

According to another aspect, the present invention provides:
A step of forming a dummy pattern extending in the first direction on the main surface of the substrate, and a first conductive film matched with the cross-sectional shape of the dummy pattern so as to cover the dummy pattern on the main surface of the substrate Forming the shape, and etching back the first conductive film in a direction substantially perpendicular to the main surface of the substrate until the upper surface of the dummy pattern and the main surface of the substrate are exposed, and the dummy pattern Forming first and second conductive side wall films as a pair of lower electrode patterns on the opposing first and second side wall surfaces, respectively, and the pair of lower electrode patterns and Forming a hysteresis film made of a metal oxide so as to continuously cover the upper surface of the dummy pattern, forming a second conductive film on the hysteresis film, and the hysteresis It is patterned to provide a method of manufacturing an electronic device characterized by comprising a step of forming a top electrode patterns extending in a second direction different from the first direction.

  According to the present invention, when manufacturing an electronic device including an MIM element having a hysteresis film sandwiched between an upper electrode pattern and a lower electrode pattern, the lower electrode pattern is formed as a conductive sidewall film of a dummy pattern on a substrate. The step coverage of the hysteresis film or the upper electrode pattern thereon is improved, and when the hysteresis film and the upper electrode are formed on the lower electrode pattern, the hysteresis film is defective due to sharp corners of the lower electrode pattern. The problem that the upper and lower electrodes are short-circuited or the upper electrode pattern is disconnected is avoided. Further, by using a conductive nitride film for the upper electrode pattern and the lower electrode pattern, an etch back process when forming the lower electrode pattern and a dry etching process when forming the upper electrode pattern can be easily performed, The manufacturing yield and manufacturing efficiency of electronic devices are improved. Further, by forming the lower electrode pattern from a conductive metal film and forming the hysteresis film by low-temperature sputtering, formation of an oxide film on the surface of the lower electrode pattern is suppressed, and the electronic device has a large hysteresis loop. It becomes possible to comprise from an MIM element.

  4A to 4C show the configuration of the electronic device 20 according to an embodiment of the present invention. 4A is a plan view of the electronic device 20, FIG. 4B is a cross-sectional view along the line AA ′ in the plan view of FIG. 4A, and FIG. FIG. 4A shows a cross-sectional view along line BB ′ in FIG.

  4A to 4C, the electronic device 20 is formed on a silicon substrate 21 via a silicon oxide film 22 having a thickness of, for example, 100 nm. In FIG. 4A, dummy patterns 23A and 23B having a width of, for example, 100 nm and a height of 100 nm made of an insulating film such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are vertically arranged on the paper surface of FIG. They extend in parallel to each other, for example, with an interval of 100 nm or a repeated pitch.

In the dummy pattern 23A, conductive side wall films 24A ₁ and 24A ₂ made of, for example, MoN films are formed on a pair of opposite side wall surfaces. Similarly, the dummy pattern 23B has a pair of opposite side walls. Similar conductive side wall films 24B ₁ and 24B ₂ are formed on the side wall surface.

The conductive side wall films 24A ₁ , 24A ₂ , 24B ₁ , 24B ₂ are defined by curved surfaces that are convex outward (positive curvature) continuous from the upper surface of the dummy pattern 23A or 23B to the main surface of the substrate. And extend in parallel with each other in the vertical direction in the plan view of FIG. 4A along the dummy patterns 23A and 23B.

Further on the silicon oxide film 22, the conductive side wall film pattern 24A ₁ ~24B ₂ and the dummy pattern 23A, so as to continuously cover the upper surface of 23B, hysteresis thickness is from NiO film 15~60nm A film 25 is formed, and on the hysteresis film 25, upper electrode patterns 26A to 26D made of a MoN film having a thickness of, for example, 90 nm are respectively arranged in the horizontal direction in the drawing, for example, with a width of 100 nm and a pitch of 100 nm. It is repeatedly formed in parallel with each other. The film thickness, width, and repetition pitch of the dummy patterns 23A and 23B and the upper electrode patterns 26A to 26D are not limited to those described above.

In such a structure, FIG. 4 in plan view of (A) to correspond to the intersection of each of the conductive sidewall film pattern 24A ₁ ~24B ₂ and each of the upper electrode pattern 26A-26D, the conductive sidewall film pattern 24A ₁ the ～24B ₂ as a lower electrode, wherein the one upper electrode pattern 26A~26D an upper electrode, MIM element having a hysteresis characteristic as shown earlier in Figure 2 is formed.

In this embodiment, the MoN film used to form the conductive sidewall film patterns 24A _{1 to} 24B ₂ and the upper electrode patterns 26A to 26D generally has a non-stoichiometric composition MoNx. to suppress the oxidation of Mo of the conductive sidewall film pattern 24A ₁ ~24B ₂ during the formation of the hysteresis film 25, particularly as the said conductive sidewall film pattern 24A ₁ ~24B _2, close to the stoichiometric composition, That is, it is preferable to use a MoN film having a composition parameter x close to 1. As the conductive sidewall film patterns 24A _{1 to} 24B ₂ and the upper electrode patterns 26A to 26D, conductive nitrides such as WN, TaN, and TiN can be used in addition to MoN.

Furthermore, in the present embodiment, the hysteresis film is not limited to the NiO film, and may be a TiO ₂ film or an Nb ₂ O ₅ film.

  5A to 5C and FIG. 6D show the manufacturing process of the electronic device 20 shown in FIGS. 4A to 4C.

  Referring to FIG. 5A, dummy patterns 23A and 23B are formed on a silicon oxide film 22 covering the silicon substrate 21, and a conductive film 24 made of a conductive nitride film such as a MoN film is reacted. Typically, by sputtering, the dummy patterns 23A and 23B are formed in a shape matched with the cross-sectional shape so as to cover the dummy patterns 23A and 23B at room temperature.

Next, in the step of FIG. 5B, the conductive film 24 is formed on the upper surfaces of the dummy patterns 23A and 23B and the silicon oxide by RIE method in which Cl ₂ gas and O ₂ gas are added as etching gases in Ar gas plasma. Etching back is performed until the upper surface of the film 22 is exposed, whereby the conductive sidewall films 24A _{1 to} 24B ₂ are formed on the respective sidewall surfaces of the dummy patterns 23A and 23B. In this embodiment, by using a conductive nitride film such as a MoN film as the conductive film 24, the etch-back process of FIG. This can be carried out more efficiently than when a membrane is used. As the conductive film 24, an oxidation-resistant conductive film such as a WN film, a TaN film, or a TiN film can be used in addition to the MoN film as described above.

Next, in the step of FIG. 5C, the NiO hysteresis film 25 is formed on the silicon oxide film 22 on the conductive side wall by the reactive sputtering method in the oxygen atmosphere on the structure of FIG. so as to cover the film 24A ₁ ~24B _2, it is continuously formed at room temperature. Thereby, the conductive side wall films 24 </ b> A _{1 to} 24 </ b> B ₂ constitute a lower electrode under the hysteresis film 25. At this time, in this embodiment, the hysteresis film 25 is formed so as to cover the dummy patterns 23A and 23B and the respective conductive side wall films 24A _{1 to} 24B ₂ , and further, the respective conductive side wall films 24A _{1 to} 24B _2. However, the hysteresis film 25 is superior to the conductive sidewall films 24A _{1 to} 24B ₂ because it is covered with a sidewall surface having an outwardly convex shape from the upper surface of the dummy pattern to the surface of the silicon oxide film 22. However, there is no problem that the film thickness of the hysteresis film 25 is locally reduced or the hysteresis film 25 disappears due to poor step coverage.

In the present embodiment, since the conductive nitride film is used as the conductive film 24, the conductive sidewall films 24A _{1 to} 24B ₂ are formed even when the hysteresis film 25 is formed in an oxidizing atmosphere. Surface oxidation is efficiently suppressed, and an increase in resistance of the MIM element is suppressed.

Next, in the step of FIG. 6D, a conductive nitride film 26 such as a MoN film is formed on the hysteresis film 25 to a thickness of, for example, 90 nm by sputtering, and this is further used as a mask with the resist pattern R1 as a mask. The upper electrode patterns 26A to 26D are formed by patterning by dry etching. In the illustrated example, the dry etching process of FIG. 6D is performed by an RIE method using Cl ₂ gas and O ₂ gas as etching gases in Ar gas plasma.

  In the present embodiment, by using a conductive nitride film such as a MoN film as the conductive film 26, the patterning process in FIG. 5D is performed as a Pt film, Rh film, Ru film, or Ir film as the conductive film 26. As compared with the case of using the above, it can be carried out by a simple resist process, that is, without using a hard mask pattern. As described above, as the conductive nitride film 26, a conductive nitride such as a WN film, a TaN film, and a TiN film can be used in addition to the MoN film.

  The electronic device 20 obtained in this way has a configuration in which MIM elements having hysteresis characteristics are arranged in a matrix as shown in the plan view of FIG. 4A, and has been described with reference to FIG. As such, various logic operations can be performed.

Since the electronic device 20 uses the conductive sidewall films 24A _{1 to} 24B ₂ as the lower electrode, the element area is reduced. In particular, in the plan view of FIG. In addition, it is possible to easily and inexpensively form a high-integrated-density logic element composed of MIM arrays, which is realized without increasing the cost.

  As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

(Appendix 1) a substrate,
A dummy pattern formed on the substrate so as to extend in a first direction parallel to each other;
A pair of lower electrode patterns comprising first and second conductive sidewall films respectively formed on opposite first and second sidewall surfaces of the dummy pattern, each extending in the first direction;
On the substrate, a hysteresis film made of a metal oxide formed to cover the dummy pattern and the pair of lower electrode patterns;
An upper electrode pattern made of a conductive film formed on the hysteresis film so as to extend in a second direction different from the first direction;
An electronic device comprising:

  (Supplementary Note 2) Each of the first and second conductive sidewall films is defined by a curved surface having a positive curvature outward from the upper surface of the dummy pattern to the substrate surface on which the dummy pattern is formed. The electronic device according to claim 1, wherein the hysteresis film is defined by a curved surface having a positive curvature corresponding to the curved surface on the lower electrode pattern.

  (Supplementary note 3) The electron according to Supplementary note 1 or 2, wherein the hysteresis film has a substantially uniform thickness on the dummy pattern and on the first and second conductive sidewall films. apparatus.

  (Supplementary note 4) The electronic device according to any one of supplementary notes 1 to 3, wherein the lower electrode pattern and the upper electrode pattern are made of conductive metal nitride.

  (Supplementary note 5) The electronic device according to any one of supplementary notes 1 to 4, wherein the lower electrode pattern and the upper electrode pattern are selected from the group consisting of MoN, TaN, WN, HfN, and TiN.

  (Appendix 6) The electronic device according to any one of appendices 1 to 5, wherein the hysteresis film is made of a metal oxide film.

(Supplementary Note 7) The hysteresis film, NiO film, and a note 1 to 6, characterized in that consists of TiO ₂ film or Nb ₂ O ₅ film, electronic apparatus according to any one claim.

  (Supplementary Note 8) The first and second lower electrode patterns are repeatedly formed on the substrate in a direction perpendicular to the first direction, and the upper electrode pattern is formed on the hysteresis film and in the second direction. The electronic device according to claim 1, wherein the electronic device is repeatedly formed in an orthogonal direction.

(Additional remark 9) The process of forming the dummy pattern extended in a 1st direction on a board | substrate main surface,
Forming a first conductive film on the main surface of the substrate so as to cover the dummy pattern in a shape matching the cross-sectional shape of the dummy pattern;
The first conductive film is etched back in a direction substantially perpendicular to the main surface of the substrate until the upper surface of the dummy pattern and the main surface of the substrate are exposed. Forming first and second conductive sidewall films on the second sidewall surface as a pair of lower electrode patterns, respectively;
Forming a hysteresis film made of a metal oxide so as to continuously cover the upper surfaces of the pair of lower electrode patterns and the dummy pattern on the main surface of the substrate;
Forming a second conductive film on the hysteresis film;
Patterning the hysteresis film to form an upper electrode pattern extending in a second direction different from the first direction;
A method for manufacturing an electronic device, comprising:

  (Additional remark 10) The said 1st and 2nd electrically conductive film consists of metal nitride films, The manufacturing method of the electronic device of Additional remark 9 characterized by the above-mentioned.

  (Additional remark 11) The said 1st and 2nd electrically conductive film is a manufacturing method of the electronic device of Additional remark 9 or 10 selected from the group which consists of MoN, TaN, WN, HfN, and TiN.

  (Additional remark 12) The said hysteresis film consists of metal oxide films, The manufacturing method of the electronic device as described in any one of Additional remarks 9-11 characterized by the above-mentioned.

(Supplementary Note 13) The metal oxide film NiO film, a method of manufacturing an electronic device according to Note 12, wherein it is a TiO ₂ film or Nb ₂ O ₅ film.

  (Additional remark 14) The said metal oxide film is formed by sputtering, The manufacturing method of the electronic device as described in any one of Additional remarks 9-13 characterized by the above-mentioned.

(A)-(C) are figures which show the structure of the electronic device by the related technique of this invention. It is a figure which shows the hysteresis characteristic of the MIM element contained in the electronic device of FIG. It is a figure which shows the example of the logic operation | movement by the electronic device of FIG. (A)-(C) are figures which show the structure of the electronic device by one Embodiment of this invention. (A)-(C) is a figure (the 1) explaining the manufacturing process of the electronic device of FIG. (D) is a figure (the 2) explaining the manufacturing process of the electronic device of FIG.

Explanation of symbols

21 Silicon substrate 22 Silicon oxide film 23A, 23B Dummy pattern 24A ₁ , 24A ₂ , 24B ₁ , 24B ₂ Conductive sidewall film (lower electrode pattern)
25 Hysteresis film 26A-26D Upper electrode

Claims (6)

A substrate,
A dummy pattern formed on the substrate so as to extend in a first direction parallel to each other;
A pair of lower electrode patterns comprising first and second conductive side wall films respectively formed on opposite first and second side wall surfaces of the dummy pattern, each extending in the first direction;
On the substrate, a hysteresis film made of a metal oxide formed to cover the dummy pattern and the pair of lower electrode patterns;
An upper electrode pattern made of a conductive film formed on the hysteresis film so as to extend in a second direction different from the first direction;
An electronic device comprising:   2. The electronic device according to claim 1, wherein the hysteresis film has a substantially uniform film thickness on the dummy pattern and on the first and second conductive sidewall films.   3. The electronic device according to claim 1, wherein the lower electrode pattern and the upper electrode pattern are made of conductive metal nitride.   The electronic device according to claim 1, wherein the hysteresis film is made of a metal oxide film. Forming a dummy pattern extending in a first direction on the substrate main surface;
Forming a first conductive film on the main surface of the substrate so as to cover the dummy pattern in a shape matching the cross-sectional shape of the dummy pattern;
The first conductive film is etched back in a direction substantially perpendicular to the main surface of the substrate until the upper surface of the dummy pattern and the main surface of the substrate are exposed. Forming first and second conductive sidewall films on the second sidewall surface as a pair of lower electrode patterns, respectively;
Forming a hysteresis film made of a metal oxide so as to continuously cover the upper surfaces of the pair of lower electrode patterns and the dummy pattern on the main surface of the substrate;
Forming a second conductive film on the hysteresis film;
Patterning the hysteresis film to form an upper electrode pattern extending in a second direction different from the first direction;
A method for manufacturing an electronic device, comprising:   6. The method of manufacturing an electronic device according to claim 5, wherein the first and second conductive films are made of a metal nitride film.

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