JP2006319204A - 半導体装置の製造方法、及び半導体装置 - Google Patents
半導体装置の製造方法、及び半導体装置 Download PDFInfo
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Abstract
【解決手段】 本発明の半導体装置の製造方法は、支持基板上に第1の絶縁膜を介して形成された半導体層を有するSOI基板を準備する工程と、SOI基板に複数のSOIトランジスタを形成する工程と、SOIトランジスタを複数層にわたって適宜配線する工程と、複数層の配線のうち最上層配線で支持基板とSOIトランジスタとの電気的接続を取る工程とを有する。
【選択図】 図1
Description
また、SOIウェハの半導体層に形成されたトランジスタ(以下SOIトランジスタと称す)は、SOIトランジスタがオンの時に発生するホットキャリアがSOIトランジスタのチャネル領域に蓄積することによりSOIトランジスタの特性が変動してしまう。変動を抑制するためにチャネル領域の電位を固定して、SOIトランジスタの動作を安定させる必要がある。通常ICは、樹脂やセラミックによって封止されるため、基板との電気的接続を取ることが困難である。そこでICの裏面に金属板を貼り付けて、ICの表面のボンディングとは別に金属板へボンディングすることにより、金属板の電位を外部から固定する技術が用いられることがある。
なおICの表面から基板への電気的な接続を取っている技術に関しては例えば下記特許文献1に記載されている。
よって、本発明の目的は上記問題を解決し、トランジスタの特性変動やゲート酸化膜の劣化を最小限に抑える半導体装置及び半導体装置の製造方法を提供することである。
第3の絶縁層上に形成される第1の配線層と、第3の絶縁層、素子分離層及び第1の絶縁層を貫通し、支持基板と電気的導通を取る第1の導体と、第3の絶縁層を貫通し、ゲート電極と電気的導通を取る第2の導体と、第3の絶縁層を貫通し、半導体層の拡散領域と電気的導通を取る第3の導体と、第1の配線層上に第4の絶縁層を介して形成されると共に、第1の導体と、第2の導体又は第3の導体と電気的導通を取る最上層配線とを備えている。
第2の層間絶縁膜114、第4の導体141、及び第5の導体142上には第3の層間絶縁膜116が形成されている。第3の層間絶縁膜116を貫通して第5の導体142と電気的導通を取る第6の導体262が形成されている。第3の層間絶縁膜116を貫通して第4の導体141と電気的導通を取る第7の導体261が形成されている。第6の導体上には第1の電極パッドである第1の外部端子217が形成されている。第7の導体261上には第2の電極パッドである第2の外部端子227が形成されている。第3の層間絶縁膜116以下の構成を総称して半導体チップ810と称す。
図11(b)に示すように、スパッタリング等を使用してSOIウェハ1110を貫通する貫通孔を形成する。貫通孔内に、銅や錫の合金などの貫通電極1111をメッキ法、導電ペーストの埋め込み、あるいは、溶融金属の埋め込み法などを使用して形成する。
102 埋め込み酸化膜
103 半導体層
104 素子分離層
105 チャネル領域
106 拡散領域
107 ゲート酸化膜
108 ゲート電極
109 第1の層間絶縁膜
110 第1の導体
111 第2の導体
112 第3の導体
113 第1の配線層
114 第2の層間絶縁膜
115 最上層配線
116 第3の層間絶縁膜
117 外部端子
118 高濃度インプラ領域
141 第4の導体
142 第5の導体
161 第6の導体
Claims (15)
- 支持基板上に第1の絶縁膜を介して形成された半導体層を有するSOI基板を準備する工程と、
前記SOI基板に複数のSOIトランジスタを形成する工程と、
前記SOIトランジスタを複数層にわたって適宜配線する工程と、
前記複数層の配線のうち最上層配線で前記支持基板と前記SOIトランジスタとの電気的接続を取る工程と、
を有する半導体装置の製造方法。 - 前記支持基板と前記SOIトランジスタとの電気的接続を取る工程は、前記複数層の配線間に形成された絶縁層にコンタクトホールを形成し、導電体を埋め込むことにより電気的接続を取ることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記コンタクトホールの底部に位置する前記支持基板に高濃度のインプラを行う工程を有することを特徴とする請求項2に記載の半導体装置の製造方法。
- 支持基板上に第1の絶縁膜を介して形成された半導体層を有するSOI基板を準備する工程と、
前記SOI基板に複数のSOIトランジスタを形成する工程と、
前記SOIトランジスタを複数層にわたって適宜配線する工程と、
前記SOIトランジスタと電気的に接続された第1の電極パッドを形成する工程と、
前記支持基板と電気的に接続された第2の電極パッドを形成する工程と、
前記第1の電極パッドと前記第2の電極パッドとを電気的に接続する工程と、
を有する半導体装置の製造方法。 - 前記第1の電極パッドと前記第2の電極パッドとを電気的に接続する工程は、ワイヤボンディングによる接続であることを特徴とする請求項4に記載の半導体装置の製造方法。
- さらに、前記第1の電極パッド上に第1の最上層配線を形成する工程と、
前記第1の最上層配線上に導電体を形成する工程と、
前記第1の最上層配線及び前記導電体を樹脂封止し、前記導電体上に外部端子を形成する工程と、
を有することを特徴とする請求項4に記載の半導体装置の製造方法。 - チャネル領域と前記チャネル領域を挟む拡散領域とを有する半導体層と素子分離層とが第1の絶縁層を介して支持基板上に形成された半導体装置であって、
前記半導体層上の前記チャネル領域に第2の絶縁層を介して形成されるゲート電極と、
前記素子分離層、前記半導体層、及び前記ゲート電極上に形成される第3の絶縁層と、
前記第3の絶縁層上に形成される第1の配線層と、
前記第3の絶縁層、前記素子分離層及び前記第1の絶縁層を貫通し、前記支持基板と電気的導通を取る第1の導体と
前記第3の絶縁層を貫通し、前記ゲート電極と電気的導通を取る第2の導体と、
前記第3の絶縁層を貫通し、前記半導体層の前記拡散領域と電気的導通を取る第3の導体と、
前記第1の配線層上に第4の絶縁層を介して形成されると共に、前記第1の導体と、前記第2の導体又は前記第3の導体と電気的導通を取る最上層配線と、
を有する半導体装置。 - 前記最上層配線上には前記最上層配線と電気的に導通を取った電極パッドが形成されることを特徴とした請求項7に記載の半導体装置。
- 前記第1の導体と、前記第2の導体又は前記第3の導体の電気的な導通は前記最上層配線で始めて行われることを特徴とする請求項7に記載の半導体装置。
- 前記第1の導体と、前記第2の導体又は前記第3の導体の電気的な導通は前記電極パッドの直下の配線層で行われることを特徴とする請求項7に記載の半導体装置。
- 前記半導体層上でかつ前記最上層配線下の層では、前記第1の導体と、前記第2の導体又は前記第3の導体の電気的な導通は行われていないことを特徴とする請求項7に記載の半導体装置。
- チャネル領域と前記チャネル領域を挟む拡散領域とを有する半導体層と素子分離層とが第1の絶縁層を介して支持基板上に形成された半導体装置であって、
前記半導体層上の前記チャネル領域に第2の絶縁層を介して形成されるゲート電極と、
前記素子分離層、前記半導体層、及び前記ゲート電極上に形成される第3の絶縁層と、
前記第3の絶縁層、前記素子分離層及び前記第1の絶縁層を貫通し、前記支持基板と電気的導通を取る第1の導体と
前記第3の絶縁層を貫通し、前記ゲート電極と電気的導通を取る第2の導体と、
前記第3の絶縁層を貫通し、前記半導体層の前記拡散領域と電気的導通を取る第3の導体と、
複数の配線層及び複数の絶縁層を介して前記第1の導体上に前記第1の導体と電気的に導通を取って形成される第1の電極パッドと、
前記複数の配線層及び前記複数の絶縁層を介して前記第2の導体又は前記第3の導体上に前記第2の導体又は前記第3の導体いずれか又双方と電気的に導通を取って形成される第2の電極パッドと、
を有する半導体装置。 - 前記第1及び第2の電極パッドは、互いに電気的に接続されていることを特徴とする請求項12に記載の半導体装置。
- 前記第1の電極パッドと第2の電極パッドとの接続は、ワイヤボンディングによる電気的な接続であることを特徴とする請求項13に記載の半導体装置。
- 請求項12に記載の半導体装置は、前記第1の電極パッドと前記第2の電極パッドが一体形成されることにより電気的に接続されていることを特徴とする。
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