JP2006303128A - 中空半導体パッケージの製造方法 - Google Patents
中空半導体パッケージの製造方法 Download PDFInfo
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- JP2006303128A JP2006303128A JP2005121776A JP2005121776A JP2006303128A JP 2006303128 A JP2006303128 A JP 2006303128A JP 2005121776 A JP2005121776 A JP 2005121776A JP 2005121776 A JP2005121776 A JP 2005121776A JP 2006303128 A JP2006303128 A JP 2006303128A
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
【解決手段】 半導体素子2の回路面を配線基板側にして、半導体素子を基板1にフリップチップ実装し、光硬化性封止用部材15を、半導体素子が搭載された基板側から半導体素子及び基板に被せ、光硬化性封止用部材を、真空下で、半導体素子及び基板へ弾性体17を介した加圧押し当てにより貼り付けて半導体素子と基板との間の隙間に中空部4を形成し、真空状態を維持したまま、光硬化性封止用部材に樹脂硬化用光線を照射して光硬化性封止用部材を硬化させる。半導体素子を、基板上にマトリクス状又は直線状に複数配置し、光硬化性封止用部材に樹脂硬化用光線を照射して光硬化性封止用部材を硬化させた後、各々の半導体素子を基板とともに個別に切断してもよい。
【選択図】 図2
Description
2 半導体素子
3 光硬化性樹脂
4 中空部
5 バンプ
11 (分割前の)配線基板
15 光硬化性樹脂シート
16 真空チャンバ
17 加圧用ゴムシート
18 光硬化用光源
19 分割ライン
20 ダイシングソー
25 空隙
26 光硬化性樹脂シート貼付済み基板
27 樹脂破損
28 (チャンバ)上部
29 (チャンバ)下部
30 (チャンバ上部の真空、加圧)経路
31 (チャンバ下部の真空)経路
33 ミラー
34 ミラー
35 ガラス板
36 光源
37 光ファイバ
38 上部チャンバ
39 Oリング
40 下部チャンバ
Claims (3)
- 半導体素子の回路面を配線基板側にして、該半導体素子を該基板にフリップチップ実装し、
光硬化性封止用部材を、前記半導体素子が搭載された前記基板側から、該半導体素子及び該基板に被せ、
前記光硬化性封止用部材を、真空下で、前記半導体素子及び前記基板へ弾性体を介した加圧押し当てにより貼り付けて前記半導体素子と前記基板との間の隙間に中空部を形成し、
真空状態を維持したまま、前記光硬化性封止用部材に樹脂硬化用光線を照射して該光硬化性封止用部材を硬化させることを特徴とする中空半導体パッケージの製造方法。 - 前記半導体素子は、前記基板上にマトリクス状又は直線状に複数配置され、前記光硬化性封止用部材に樹脂硬化用光線を照射して該光硬化性封止用部材を硬化させた後、各々の半導体素子を前記基板とともに個別に切断することを特徴とする請求項1に記載の中空半導体パッケージの製造方法。
- 前記光硬化性封止用部材に樹脂硬化用光線を照射するにあたって、前記弾性体を回避して樹脂硬化用光線を照射することを特徴とする請求項1又は2に記載の中空半導体パッケージの製造方法。
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JP2005121776A JP4502870B2 (ja) | 2005-04-20 | 2005-04-20 | 中空半導体パッケージの製造方法 |
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JP2005121776A JP4502870B2 (ja) | 2005-04-20 | 2005-04-20 | 中空半導体パッケージの製造方法 |
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JP2006303128A true JP2006303128A (ja) | 2006-11-02 |
JP4502870B2 JP4502870B2 (ja) | 2010-07-14 |
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JP2005121776A Expired - Fee Related JP4502870B2 (ja) | 2005-04-20 | 2005-04-20 | 中空半導体パッケージの製造方法 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009021559A (ja) * | 2007-06-12 | 2009-01-29 | Nippon Dempa Kogyo Co Ltd | 電子部品及びその製造方法 |
WO2009122607A1 (ja) * | 2008-04-04 | 2009-10-08 | ソニーケミカル&インフォメーションデバイス株式会社 | 半導体装置及びその製造方法 |
JP7378096B2 (ja) | 2021-12-23 | 2023-11-13 | 三安ジャパンテクノロジー株式会社 | モジュールおよびモジュールの製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005302835A (ja) * | 2004-04-07 | 2005-10-27 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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2005
- 2005-04-20 JP JP2005121776A patent/JP4502870B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005302835A (ja) * | 2004-04-07 | 2005-10-27 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009021559A (ja) * | 2007-06-12 | 2009-01-29 | Nippon Dempa Kogyo Co Ltd | 電子部品及びその製造方法 |
WO2009122607A1 (ja) * | 2008-04-04 | 2009-10-08 | ソニーケミカル&インフォメーションデバイス株式会社 | 半導体装置及びその製造方法 |
US8409932B2 (en) | 2008-04-04 | 2013-04-02 | Sony Chemical & Information Device Corporation | Method for manufacturing semiconductor device |
JP7378096B2 (ja) | 2021-12-23 | 2023-11-13 | 三安ジャパンテクノロジー株式会社 | モジュールおよびモジュールの製造方法 |
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