JP2006251631A - Pixel circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit capable of compensating an influence of mobility in addition to threshold voltage of a drive transistor. <P>SOLUTION: The pixel circuit 2 has a transistor Tr5 for compensation, operates in a compensation period set prior to a sampling period, energizes capacity parts Cs1, Cs2, shields energization after resetting potential held by the capacity parts and detects potential difference which appears between a source S and a gate G of the drive transistor Tr2. The capacity parts Cs1, Cs2 hold potential according to the detected potential difference. The held potential offsets the influence of the threshold voltage Vth to output current Ids of the drive transistor Tr2. Furthermore, the drive transistor Tr2 shortens length of its channel area to provide the output current with dependency over voltage between the source S and a drain D and thus, performs self-compensation of the dependency over carrier mobility μ of the output current Ids. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit that current-drives a light emitting element arranged for each pixel. In addition, this pixel circuit is a display device arranged in a matrix (matrix), and the amount of current supplied to a light emitting element such as an organic EL is controlled by an insulated gate field effect transistor provided in each pixel circuit. The present invention relates to a so-called active matrix display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional pixel circuit is arranged at a portion where a row scanning line supplying a control pulse and a column signal line supplying a video signal intersect, and includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control pulse supplied from the scanning line and samples the video signal supplied from the signal line. The capacitor holds an input potential corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period according to the input potential held in the capacitor portion. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives the input potential held in the capacitor portion at the gate, causes an output current to flow between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input potential written in the capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic equation, Ids represents a drain current flowing between the source and drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate applied voltage applied to the gate with reference to the source, and is the above-described input potential in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as the above transistor characteristic equation shows, the same amount of drain current Ids is always supplied to the light emitting element if the gate voltage Vgs is constant. Accordingly, if input signals having the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As is apparent from the above transistor characteristic equation, if the threshold voltage Vth of each drive transistor varies, even if the gate applied voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

A pixel circuit incorporating a function for canceling variations in threshold voltage can improve screen uniformity to some extent. However, the characteristics of the polysilicon thin film transistor vary not only in the threshold voltage but also in the mobility μ from element to element. As is apparent from the transistor characteristic equation described above, the drain current Ids is proportional to the mobility μ. Therefore, when the mobility μ varies, the drain current Ids varies even when the gate voltage Vgs is constant. As a result, the emission luminance varies from pixel to pixel, and there is a problem that the uniformity of the screen is impaired. Although there is no direct relevance to the present invention, the following Patent Documents 6 to 11 are cited as techniques for improving the uniformity of the screen.
JP2002-132218A JP2003-186438 JP 2000-276075 A JP 2004-126559 A JP2004004911 JP 2004-054234 A

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device and a pixel circuit capable of correcting a variation in mobility in addition to a variation in threshold voltage of a drive transistor. In order to achieve this purpose, the following measures were taken. That is, the present invention is arranged at a portion where a row scanning line for supplying a control pulse and a column signal line for supplying a video signal intersect, and includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element, The sampling transistor conducts in response to a control pulse supplied from a scanning line during a predetermined sampling period to sample a video signal supplied from a signal line, and the capacitor unit receives an input potential corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period according to the input potential held in the capacitor, and the output current is set to the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element has the image by the output current supplied from the drive transistor. In the pixel circuit that emits light with a luminance according to the signal, the pixel circuit includes correction means for correcting the dependency of the output current on the threshold voltage, and the correction means is connected to the drive transistor and the capacitor unit, Operates in the correction period set prior to the sampling period, energizes the capacitor unit to reset the potential held by the capacitor unit, and then shuts off the energization and appears between the source and gate of the drive transistor. A potential difference is detected, the capacitor holds a potential corresponding to the detected potential difference, the held potential cancels the influence of the threshold voltage on the output current of the drive transistor, and the drive transistor further detects the channel region. Shortening the length to give the output current a dependency on the source-drain voltage, which in turn depends on the carrier mobility of the output current Is self-correcting. Preferably, the drive transistor has a channel region length reduced to 5 μm or less.

  In addition, the present invention includes a pixel array unit, a scanner unit, and a signal unit, and the pixel array unit is arranged at a portion where scanning lines arranged in rows and signal lines arranged in columns intersect. The signal unit supplies a video signal to the signal line, and the scanner unit supplies a control pulse to the scanning line to sequentially scan the pixels row by row, The pixel includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element, and the sampling transistor is supplied from the signal line in a conductive state according to a sampling control pulse supplied from the scanning line during a predetermined sampling period. The video signal is sampled, the capacitor unit holds an input potential corresponding to the sampled video signal, and the drive transistor has an input potential held in the capacitor unit Accordingly, an output current is supplied during a predetermined light emission period, and the output current is dependent on the carrier mobility and threshold voltage of the channel region of the drive transistor, and the light emitting element is supplied from the drive transistor. In the display device that emits light with the luminance corresponding to the video signal by the output current, each pixel includes a correction unit for correcting the dependency of the output current on the threshold voltage, and the correction unit includes the drive transistor. Connected to the capacitor unit, operates in a correction period set prior to the sampling period, and energizes the capacitor unit to reset the potential held by the capacitor unit and then shuts off the energization. A potential difference appearing between a source and a gate of the drive transistor is detected, and the capacitor holds a potential corresponding to the detected potential difference, and the held potential is The influence of the threshold voltage on the output current of the transistor is offset, and the drive transistor shortens the length of its channel region to give the output current a dependency on the source-drain voltage, and thereby the carrier movement of the output current. It is characterized by self-correcting the dependence on the degree. Preferably, the drive transistor has a channel region length reduced to 5 μm or less.

  According to the present invention, the pixel circuit corrects the dependency on the carrier mobility in addition to the dependency on the threshold voltage of the output current. First of all, the dependency on the threshold voltage is corrected. In the predetermined correction period, a transient current for detection is applied to the drive transistor, and when this is cut off, the potential difference appearing between the source and gate of the drive transistor is detected. It is held in the capacity section. The potential difference that appears when the drive transistor is cut off is just equal to the threshold voltage Vth, which is held in the capacitor and added to the input potential. As a result, the influence of the threshold voltage of the drive transistor can be canceled.

  Next, carrier mobility variation correction is performed. The channel region of the drive transistor is shortened to give a so-called Early effect, and this is used to self-correct the mobility variation. Specifically, by shortening the length of the channel region to 5 μm or less, an Early effect that is effective in suppressing mobility variation can be imparted. In general, when a drive transistor operates in a saturation region, the output current (drain current) depends only on the gate voltage appearing between the source and the gate, and does not depend on the drain voltage appearing between the source and the drain. However, when the channel region is shortened and the Early effect is applied, the drain current becomes dependent on the drain voltage. In the pixel circuit, the drive transistor drives the light emitting element, and the drain voltage is determined by the operating point with the light emitting element. In other words, the drain voltage varies depending on the anode potential of the light emitting element. When an early effect is applied to the drive transistor, when the mobility is high and the current supply capability is large, the operating point changes in the direction in which the anode potential increases, and the drain voltage decreases accordingly. When the drain voltage decreases due to the Early effect, the drain current decreases. In this way, when the mobility is high, self-correction is applied in the direction in which the drain current decreases. Conversely, when the mobility is small and the output current supply capability is small, the anode potential tends to change downward, and the drain voltage increases accordingly. Due to the Early effect, the drain current increases as the drain voltage increases. That is, since the Early effect acts in a direction to compensate for a small output current supply capability, self-correction is still applied. In this way, it is possible to automatically correct variations in mobility due to the Early effect of the drive transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention. As shown in the figure, an active matrix display device is composed of a pixel array 1 as a main part and a peripheral circuit group. The pixel array 1 includes a pixel circuit 2. The peripheral circuit group includes a horizontal selector 3, a write scanner 4, a first drive scanner 5, a second drive scanner 6, a correction scanner 7, and the like.

  The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines SL, and pixel circuits 2 arranged in a matrix at portions where they intersect. In the case of this example, in order to perform color display, the pixel circuit 2 is provided separately for the three primary colors of RGB. The signal line SL is driven by the horizontal selector 3. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS1, DS2, and AZ are also wired in parallel with the scanning line WS. The scanning line DS1 is scanned by the first drive scanner 5. The scanning line DS2 is scanned by the second drive scanner 6. Note that three scanning lines DS2 are divided into RGB. On the other hand, one scanning line DS1 is provided in common for RGB. The remaining scanning lines AZ are scanned by the correction scanner 7.

  FIG. 2 is a circuit diagram showing a basic configuration of the pixel circuit 2 shown in FIG. The pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Tr2, a switching transistor Tr3, a switching transistor Tr4, a detection transistor Tr5, a switching transistor Tr6, a pair of capacitive elements Cs1 and Cs2, and a light emitting element EL. In this embodiment, each of the transistors Tr1 to Tr6 is composed of an N channel type amorphous silicon thin film transistor (TFT). As the light emitting element EL, for example, an organic EL element can be used. As a feature of the present invention, the channel length of the drive transistor Tr2 is shortened to 5 μm or less, and an early effect is given. Due to this Early effect, the output current (drain current Ids) of the drive transistor Tr2 depends on the voltage between the source S and drain D (drain voltage Vds). Specifically, the drain current tends to decrease as the drain voltage decreases.

  Next, the configuration of the pixel circuit 2 will be specifically described with reference to FIG. The drive transistor Tr2 includes a gate G serving as an input node, a source S serving as an output node, and a drain D serving as a power supply node. The anode of the light emitting element EL is connected to the output node (S). The cathode of the light emitting element EL is grounded (GND). In this example, the light emitting element EL is a two-terminal type including an anode and a cathode. The power supply side node (D) of the drive transistor Tr2 is connected to the power supply Vcc via the switching transistor Tr4. The gate of the switching transistor Tr4 is connected to the scanning line DS2.

  One end of the storage capacitor Cs2 is connected to the input node (G) of the drive transistor Tr2. The other end of the storage capacitor Cs2 is connected to the output node (S) and grounded via the switching transistor Tr3. The gate of the switching transistor Tr3 is connected to the scanning line DS1. Further, the sampling transistor Tr1 is connected to the input node (G) via the coupling capacitor Cs1. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The source of the sampling transistor Tr1 is connected to the signal line SL. In addition, the connection node between the coupling capacitor Cs1 and the sampling transistor Tr1 is grounded via the switching transistor Tr6. The gate of the switching transistor Tr6 is connected to the scanning line AZ. Finally, the detection transistor Tr5 is connected between the gate G and the drain D of the drive transistor Tr2. The gate of the detection transistor Tr5 is connected to the scanning line AZ.

  With reference to the timing chart of FIG. 3, the operation of the pixel circuit according to the first embodiment shown in FIG. 2 will be described in detail. In the illustrated timing chart, one field (1f) starts at the timing T1 and one field ends at the timing T8. Along the time axis, waveforms of control pulses WS, AZ, DS1, and DS2 applied to the scanning lines WS, AZ, DS1, and DS2, respectively, are shown. Further, along the same time axis, the potential change of the input node (G) and the output node (S) of the drive transistor Tr2 is shown.

  At the timing T0 before the timing T1 at which the field starts, the scanning lines WS, AZ, DS1 are at the low level, while the scanning line DS2 is at the high level. Therefore, only the switching transistor Tr4 is on, and the remaining transistors Tr1, Tr3, Tr5, and Tr6 are off. In this state, the drain D of the drive transistor Tr2 is connected to the power supply Vcc via the switching transistor Tr4 in the on state. The drive transistor Tr2 supplies an output current (drain current) Ids to the light emitting element EL according to a gate voltage Vgs applied between the gate G and the source S. Thus, the light emitting element EL emits light with a predetermined luminance.

    When the field starts at timing T1, the control pulse AZ rises. As a result, the detection transistor Tr5 and the switching transistor Tr6 are turned on. When Tr6 is turned on, one end of the coupling capacitor Cs1 is fixed at the ground potential GND, and a detection voltage threshold (Vth) detection state of the drive transistor Tr2 is entered. Since the detection transistor Tr5 is also turned on, the gate G and the drain D of the drive transistor Tr2 are directly connected. At this time, since the switching transistor Tr4 is still kept on, the gate potential of the drive transistor Tr2 rises rapidly. In conjunction with this, the source potential of the drive transistor Tr2 also rises rapidly. In this way, the potential held in the capacitive elements Cs1 and Cs2 is once reset.

  Subsequently, at timing T2, the control pulse DS2 becomes low level and the switching transistor Tr4 is turned off. As a result, the drive transistor Tr2 is disconnected from the power supply Vcc and enters a non-light emitting state. At the same time, since the control pulse DS1 rises, the switching transistor Tr3 is turned on, and the source S of the drive transistor Tr2 and one end of the storage capacitor Cs2 are grounded. When the switching transistor Tr4 is turned off, the gate potential G of the drive transistor Tr2 decreases. The drain current Ids stops flowing when the difference Vgs between the gate potential G and the source potential S reaches the threshold voltage Vth. As a result, the threshold voltage Vth of the drive transistor Tr2 is held in the holding capacitor Cs2 connected between the gate G and the source S.

  Thereafter, at timing T3, the control pulse AZ falls, the detection transistor Tr5 is turned off, and the Vth detection operation ends.

  Subsequently, at timing T4, the control pulse WS rises and the sampling transistor Tr1 is turned on. As a result, the video signal supplied from the signal line SL is coupled to the holding capacitor Cs2 via the coupling capacitor Cs1. As a result, the signal voltage Vin corresponding to the video signal is written to the storage capacitor Cs2 in a manner that adds to the previously written Vth. As a result, the storage capacitor Cs2 supplies the input potential Vin + Vth to the input node (G) of the drive transistor Tr2. Since the threshold voltage Vth is always added to the input potential, even if the threshold voltage of the drive transistor varies from pixel to pixel, it can always be canceled.

  Thereafter, the control pulse WS falls at the timing T5 when one horizontal period (1H) assigned to the sampling of the video signal elapses, and the sampling transistor Tr1 is turned off.

  Subsequently, at timing T6, the control pulse DS1 falls and the switching transistor Tr3 is turned off. As a result, the source S of the drive transistor Tr2 and one end of the storage capacitor Cs2 are disconnected from the ground level, and the light emitting operation is ready.

  Thereafter, at timing T7, the control pulse DS2 rises and the switching transistor Tr4 is turned on. As a result, the drain D of the drive transistor Tr2 is connected to the power supply potential Vcc, the drain current Ids corresponding to the input potential Vin + Vth flows, and the light emitting element EL emits light with the luminance corresponding to the signal potential Vin. Since the source S of the drive transistor Tr2 is already disconnected from the ground potential GND at the timing T7, the anode potential (and hence the source potential of the drive transistor Tr2) rises due to the voltage drop when the output current Ids flows through the light emitting element EL. At this time, since the gate potential also rises as it is by the bootstrap operation, the input potential (gate potential Vgs) held in the holding capacitor Cs2 is kept constant. As a result, the drive transistor Tr2 operates as a constant power source.

  Finally, when the timing T8 is reached, the field is completed and the next field is entered.

  Here, the self-correction operation of the drive transistor Tr2 performed in the light emission period T7-T8 will be described in detail. 4A and 4B are graphs showing the drain current Ids / drain voltage Vds characteristics of the drive transistor. FIG. 4A shows characteristics of a normal drive transistor having no Early effect, and FIG. 4B is a drive transistor having an Early effect. Represents the characteristics. In the graph, curve H represents the characteristics of a drive transistor having a relatively high mobility, and curve L represents the characteristics of a drive transistor having a relatively low mobility. The black dots on the characteristic curves represent operating points when the drive transistor drives the light emitting element. The anode potential is seen from the light emitting element side, and the source potential is seen from the drive transistor side.

  First, in the case where there is no Early effect (A), the drive transistor operates in the saturation region, and the drain current Ids has no dependency on the drain voltage Vds. That is, the drain current Ids is constant regardless of Vds. As is apparent from the above transistor characteristic equation, the drain current Ids is determined by the gate voltage Vgs. However, even if Vgs is constant, mobility μ and threshold voltage Vth vary, and Ids also varies between pixels. In the present invention, the variation in the threshold voltage Vth is canceled in advance. Therefore, only the influence of mobility μ remains. As is apparent from the graph, when the mobility μ is high, the drive transistor has a high current supply capability, and therefore the drain current Idsh of the drive transistor having high mobility is high. As a result, the voltage drop generated in the light emitting element is increased, so that the anode potential is increased, and as a result, the drain voltage Vdsh is relatively low. However, in the case of a normal drive transistor, the drain current Ids does not depend on the drain voltage Vds. Therefore, the drain current Idsh determined by the gate voltage Vgs always flows regardless of the operating point.

  On the other hand, as shown by the characteristic curve L, in the case of a drive transistor having a low mobility μ, the drain current Idsl is at a relatively low level because the current supply capability is low. Accordingly, the operating point (Vdsl) is shifted upward as compared with the case where the mobility is high (Vdsh). As is apparent from the above results, in the normal drive transistor, the difference in mobility μ appears directly as the difference in output current Ids, and the uniformity of the screen cannot be maintained unless correction is made. When the drive transistor operates in the saturation region, it becomes an ideal constant current source as shown in (A). Therefore, even if the operating point changes, the output current value does not change, and the output current due to variation in mobility. Variations in these cannot be corrected.

  On the other hand, when the Early effect is given to the drive transistor (B), the drain current Ids becomes dependent on the drain voltage Vds. As shown in (B), the drain current Ids tends to increase as the drain voltage Vds increases. The ratio is represented by the slope of the characteristic curve, and the slope is larger when the mobility is larger than when the mobility is small. Due to this Early effect, the operating point for the light emitting element varies. First, when the mobility is high, the relatively high anode voltage decreases, so that the operating point Vdsh moves downward as compared with the case where there is no Early effect. As a result, the drain current Idsh is also smaller than when there is no Early effect. On the other hand, in the case where the mobility is small, the relatively low anode voltage rises conversely due to the Early effect, and the operating point Vdsl shifts upward compared to the case where there is no Early effect. As a result, the drain current Idsl of the drive transistor having a low mobility becomes larger than that without the Early effect. As described above, due to the Early effect, the difference between Idsh and Idsl changes in the direction of reduction, and the self-correction function acts in the direction of absorbing the variation in mobility of the drive transistor. Therefore, it is possible to correct the variation in mobility according to the present invention.

  FIG. 5 is a graph showing the relationship between the variation in output current and the channel length (L length) of the drive transistor. The horizontal axis represents the variation in the output current of the drive transistor between pixels in%, and the horizontal axis represents the L length (unit: μm) of the drive transistor. As apparent from the graph, the variation in output current is rapidly improved by shortening the L length to 5 μm or less. By shortening the channel length of the drive transistor to 5 μm or less in this way, it is possible to self-correct the mobility variation, and even in a panel using a transistor with large variations such as a low-temperature polysilicon TFT, the uniformity is high. You can get image quality.

  FIG. 6 is a circuit diagram showing a display device and a pixel circuit according to a second embodiment of the present invention. Basically, it is similar to the first embodiment shown in FIG. 2, and corresponding parts are denoted by corresponding reference numerals. The difference is that the gate of the switching transistor Tr3 is connected to the scanning line WS, and the switching transistor Tr3 is operated by the write scanner 4. By sharing the write scanner 4 for the operation of the sampling transistor Tr1 and the switching transistor Tr3, one drive scanner is not required.

  FIG. 7 is a timing chart for explaining the operation of the pixel circuit according to the second embodiment shown in FIG. In the correction preparation period T1-T2, the control pulses DS and AZ are at a high level, while the control pulse WS is at a low level. As a result, the transistors Tr1, Tr3 are turned off, while the transistors Tr4, Tr5, Tr6 are turned on. As a result, the potential held in the capacitors (Cs1, Cs2) is once reset. Next, in the Vth correction period T2-T3, the control pulse DS is switched to the low level, and the switching transistor Tr4 is turned off. As a result, the threshold voltage Vth of the drive transistor Tr2 is detected and held in the capacitors (Cs1, Cs2). Subsequently, in the sampling period T4-T5, the control pulse WS is switched to the high level, and the sampling transistor Tr1 and the switching transistor Tr3 that have been turned off are turned on. As a result, the video signal supplied from the signal line SL is sampled and held in the capacitors (Cs1, Cs2). Finally, when the light emission period T6 starts, the control pulse DS becomes high level and the switching transistor Tr4 is turned on. At this time, the other transistors Tr1, Tr3, Tr5, Tr6 are all turned off. The drain current Ids flows through the light emitting element EL and emits light with a luminance corresponding to the video signal. At this time, since the transistor Tr3 is off, a bootstrap operation is performed. As a feature of the present invention, by reducing the channel length of the drive transistor Tr2 to 5 μm or less, variation in mobility can be corrected by itself, and even in a panel using a transistor with large variation such as a low-temperature polysilicon TFT. , You can get high uniformity image quality.

  FIG. 8 is a circuit diagram showing a display device and a pixel circuit according to a third embodiment of the present invention. Basically, it is similar to the second embodiment shown in FIG. 6, and corresponding reference numerals are assigned to corresponding parts. The difference is that the gate of the switching transistor Tr3 is connected not to the scanning line WS but to the scanning line AZ. The operation timing in this case is the same as the timing chart shown in FIG. Also in this embodiment, by reducing the channel length of the drive transistor Tr2 to preferably 5 μm or less, it is possible to self-correct the mobility variation, and even in a panel using a transistor with a large variation such as a low-temperature polysilicon TFT. , You can get high uniformity image quality.

  FIG. 9 is a circuit diagram showing a display device and a pixel circuit according to a fourth embodiment of the present invention. Basically, it is the same as the previous embodiment shown in FIG. 8, and all the transistors are N-channel type. The difference is that the number of transistors constituting the pixel circuit is reduced by one to five. In addition, the number of capacitive elements is reduced from two to one, and the capacitive portion is composed of one capacitive element Cs. In this relationship, the connection relationship of the pixel circuit 2 is slightly different from the previous embodiment. In addition, although one correction scanner 7 is used in the previous embodiment, the first correction scanner 71 and the second correction scanner 72 are used in this embodiment instead.

  Next, a specific configuration of the pixel circuit 2 will be described. The drain D of the drive transistor Tr2 is connected to the power supply potential Vcc via the switching transistor Tr4. The gate of the switching transistor Tr4 is connected to the drive scanner 5 via the scanning line DS. The source S of the drive transistor Tr2 is connected to the anode of the light emitting element EL. The cathode of the light emitting element EL is grounded. The gate G of the drive transistor Tr2 is connected to a predetermined reference potential Vss2 via the storage capacitor Cs and the switching transistor Tr3. The gate of the transistor Tr3 is connected to the second correction scanner 72 via the scanning line AZ2. A switching transistor Tr6 is connected between the gate G of the drive transistor Tr2 and another reference potential Vss1. The gate of the switching transistor Tr6 is connected to the first correction scanner 71 via the scanning line AZ1. Finally, the sampling transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Tr2. The gate of the sampling transistor Tr1 is connected to the write scanner 4 through the scanning line WS.

  FIG. 10 is a timing chart for explaining the operation of the fourth embodiment shown in FIG. At timing T1, the control pulse DS is switched from the high level to the low level, and the switching transistor Tr4 is turned off. Since the current path for the light emitting element EL is cut off, the pixel circuit 2 enters a non-light emitting period. At this time, the other control pulses AZ1, AZ2, WS are all at a low level. Therefore, at the timing T1, all the transistors Tr1, Tr3, Tr4, Tr6 are turned off.

  Subsequently, when entering the correction preparation period T2-T3, the control pulses AZ1, AZ2 are switched from the low level to the high level. As a result, the switching transistors Tr3 and Tr6 are turned on, and the potential held in the holding capacitor Cs is reset by Vss1 and Vss2. Thereafter, in the Vth correction period T4-T5, the control pulse DS becomes high level and the switching transistor Tr4 is turned on. At this point, Tr6 continues to be in the on state, while transistor Tr3 has returned to the off state. As a result, the drain current Ids flows into the storage capacitor Cs, and the potential between the gate G and the source S at the time when the drain current Ids is cut off is held in the storage capacitor Cs. The held potential corresponds to the cut-off voltage of the drive transistor Tr2, that is, the threshold voltage Vth. Thereafter, when proceeding to the sampling period T7-T8, the control pulse WS becomes high level, and the sampling transistor Tr1 is turned on. At this point, the transistor Tr6 is off. When the sampling transistor Tr1 is turned on, the video signal is sampled from the signal line SL and held in the holding capacitor Cs. Finally, when proceeding to the light emission period T9-, the control pulse DS becomes high level again, and the switching transistor Tr4 is turned on. As a result, a current path is formed between the power supply potential Vcc and the ground potential, an output current flows from the drive transistor Tr2 to the light emitting element EL, and light emission starts. Also in this embodiment, by reducing the channel length of the drive transistor Tr2 to, for example, 5 μm or less, variation in mobility can be self-corrected. Even in a panel using a transistor with large variation such as a low-temperature polysilicon TFT, High image quality can be obtained.

  FIG. 11 is a schematic circuit diagram showing a pixel circuit and a display device according to a fifth embodiment of the invention. In order to facilitate understanding, parts corresponding to those of the previous embodiment are given corresponding reference numbers. The difference is that a P-channel TFT is used instead of the N-channel TFT as the drive transistor Tr2. Even in a P-channel type drive transistor, carrier channel variation can be self-corrected by shortening the length of the channel region and providing an Early effect.

  As shown in the figure, the pixel circuit 2 includes five thin film transistors Tr1, Tr2, Tr4, Tr5, Tr6, two capacitive elements Cs1, Cs2, and one light emitting element EL. The drive transistor Tr2 is a P-channel type polysilicon TFT. The remaining sampling transistor Tr1, switching transistor Tr4, detection transistor Tr5 and switching transistor Tr6 are all N-channel polysilicon TFTs. The two main elements Cs1 and Cs2 together constitute a capacitance part of the pixel circuit 2. The light emitting element EL is composed of, for example, a two-terminal organic EL element having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  A specific configuration of the pixel circuit 2 is that the source S of the drive transistor Tr2 as the center is connected to the power supply Vcc, and the drain D is connected to the anode A of the light emitting element EL via the switching transistor Tr4. The gate of the transistor Tr4 is connected to the scanning line DS. The cathode K of the light emitting element EL is connected to the ground potential GND. A threshold voltage detection transistor Tr5 is connected between the gate G and the drain D of the drive transistor Tr2. The gate of the detection transistor Tr5 is connected to the scanning line AZ. The gate G of the drive transistor Tr2 is connected to the sampling transistor Tr1 via the storage capacitor Cs2. The sampling transistor Tr1 is interposed between the storage capacitor Cs2 and the signal line SL. The gate of the sampling transistor Tr1 is connected to the scanning line WS. A potential fixing switching transistor Tr6 is connected to a connection node between the holding capacitor Cs2 and the sampling transistor Tr1. The gate of the switching transistor Tr6 is connected to the scanning line AZ. Further, another holding capacitor Cs1 is connected between this connection node and the power supply potential Vcc. In the figure, the gate voltage appearing between the gate G and the source S of the drive transistor Tr2 is Vgs. A drain current flowing between the source S and the drain D of the drive transistor Tr2 is represented by Ids.

  FIG. 12 is a timing chart for explaining the operation of the embodiment shown in FIG. In the illustrated timing chart, one field (1f) starts at the timing T1 and one field ends at the timing T8. Waveforms of control pulses WS, AZ, DS applied to the scanning lines WS, AZ, DS, respectively, are shown along the time axis. Further, along the same time axis, the potential change of the gate G of the drive transistor Tr2 and the anode A of the light emitting element EL is shown. First, at timing T1, the control pulse AZ rises, and the detection transistor Tr5 and the potential fixing switching transistor Tr6 are turned on. As a result, the gate potential of the drive transistor Tr2 rapidly decreases and the anode potential A of the light emitting element EL increases rapidly. That is, the detection transistor Tr5 is turned on, the drain current Ids is supplied to the holding capacitor Cs2, and the potential held by this is once reset.

  At timing T2, the control pulse DS falls, the switching transistor Tr4 is turned off, and a non-light emitting period is entered. At this time, the gate potential rises, and the drain current Ids is cut off when the difference from Vcc becomes Vth. Therefore, the anode potential is lowered to the ground potential GND. The threshold voltage Vth of the drive transistor Tr2 detected in this way is held in the holding capacitor Cs2.

  Thereafter, after the control pulse AZ falls at timing T3, the control pulse WS rises at timing T4. As a result, the sampling transistor Tr1 is turned on, and the signal potential Vin corresponding to the video signal supplied from the signal line SL is sampled in the storage capacitor Cs1. As a result, the input potential held in the holding capacitor Cs2 becomes Vth + Vin, which is given as the gate potential Vg of the drive transistor Tr2. At timing T5 after one horizontal period (1H) has elapsed from timing T4, the control pulse WS returns to the low level.

  Thereafter, at timing T7, the control pulse DS rises and the switching transistor Tr4 is turned on. As a result, the drain current Ids corresponding to the input potential Vth + Vin flows through the light emitting element EL, and the light emission period is reached until timing T8. Note that a period T2-T3 from timing T2 to timing T3 is called a Vth correction period. A period T4-T5 from timing T4 to timing T5 is called a sampling period. This sampling period T4-T5 corresponds to one horizontal period 1H. In addition, a period T7-T8 from timing T7 to timing T8 is called a light emission period.

  FIG. 13 is a circuit diagram showing a sixth embodiment of a display device and a pixel circuit according to the present invention. In order to facilitate understanding, parts corresponding to those of the previous embodiment are given corresponding reference numbers. The present embodiment is characterized in that all transistors are configured as a P-channel type. As shown in the figure, the pixel circuit 2 includes five transistors Tr1 to Tr5, two capacitors Cs1 and Cs2, and one light emitting element EL.

  The source S of the drive transistor Tr2 is connected to the power supply potential Vcc via the switching transistor Tr4. The gate of the switching transistor Tr4 is connected to the drive scanner 5 via the scanning line DS. The drain D of the drive transistor Tr2 is connected to the anode of the light emitting element EL. The cathode of the light emitting element EL is grounded. The gate G of the drive transistor Tr2 is connected to a predetermined offset potential Vofs through the switching transistor Tr3. The gate of the switching transistor Tr3 is connected to the correction scanner 7 via the scanning line AZ. A holding capacitor Cs2 is arranged between the gate G of the drive transistor Tr2 and the node X on the input side. A Vth detection transistor Tr5 is connected between the source S of the drive transistor Tr2 and the input node X. The gate of the detection transistor Tr5 is connected to the scanning line AZ. Another capacitive element Cs1 is connected between the input node X and the power supply potential Vcc. Finally, the sampling transistor Tr1 is connected between the signal line SL and the input node X. The gate of the sampling transistor Tr1 is connected to the write scanner 4 through the scanning line WS. The signal line SL is connected to the horizontal selector 3.

  FIG. 14 is a timing chart for explaining the operation of the sixth embodiment shown in FIG. 13, and shows changes in the control pulses DS, AZ, WS over time. In the correction preparation period T1-T2, the control pulses DS and AZ are at a low level, and the control pulse WS is at a high level. As a result, the transistors Tr3, Tr4, Tr5 are turned on, while Tr1 is turned off. As a result, the drain current of the drive transistor Tr2 flows to the capacitor portions (Cs1, Cs2), and the potential held by these is reset. Subsequently, in the Vth correction period T2-T3, the control pulse DS becomes high level, and the switching transistor Tr4 is switched off. As a result, the drain current is cut off, and the potential difference Vth appearing between the source and the gate when the drive transistor Tr2 is cut off is detected. The detected potential difference Vth is held in the capacitor portions (Cs1, Cs2). The held potential Vth is used to cancel the influence of the threshold voltage Vth on the output current Ids of the drive transistor Tr2. Further, in the sampling period T4-T5, the control pulse WS becomes low level, the sampling transistor Tr1 is turned on, the video signal supplied from the signal line SL is sampled, and held in the capacitors (Cs1, Cs2). Thereafter, in the light emission period T6˜, the control pulse DS becomes low level, the switching transistor Tr4 is turned on, the output current Ids flows into the light emitting element EL, and light emission starts. As a feature of the present invention, by shortening the channel length of the drive transistor Tr2, it is possible to self-correct the variation in mobility, and even in a panel using a transistor having a large variation such as a low-temperature polysilicon TFT. High image quality can be obtained.

  As is apparent from the above description, the pixel circuit of the present invention basically has the row-like scanning lines WS, DS1, DS2 for supplying the control pulses WS, DS1, DS2, AZ, for example, referring to FIGS. AZ and the columnar signal lines SL for supplying video signals are arranged at the intersections. The pixel circuit 2 includes at least a sampling transistor Tr1, capacitors Cs1 and Cs2, a drive transistor Tr2, and a light emitting element EL. The sampling transistor Tr1 conducts in response to a control pulse WS supplied from the scanning line WS during a predetermined sampling period T4-T5 and samples the video signal supplied from the signal line SL. The capacitors (Cs1, Cs2) hold an input potential Vin corresponding to the sampled video signal. The drive transistor Tr2 supplies the output current Ids during a predetermined light emission period T7-T8 in accordance with the input potential Vin held in the capacitor portions (Cs1, Cs2). This output current Ids is dependent on the carrier mobility μ and the threshold voltage Vth in the channel region of the drive transistor Tr2. The light emitting element EL emits light with luminance according to the video signal by the output current Ids supplied from the drive transistor Tr2. As a feature, the pixel circuit 2 includes a correction unit for correcting the dependency of the output current Ids on the threshold voltage Vth. This correction means includes a detection transistor Tr5 in the embodiment of FIG. This correction means is connected to the drive transistor Tr2 and the capacitors (Cs1, Cs2), operates in a correction period T1-T3 set prior to the sampling period T7-T8, and operates in the capacitors (Cs1, Cs2). After energization and resetting the potential held by the capacitor portions (Cs1, Cs2), the energization is interrupted and the potential difference Vgs appearing between the source S and the gate G of the drive transistor Tr2 is detected. The capacitive element Cs2 in the capacitive unit holds a potential corresponding to the detected potential difference Vgs. This held potential Vgs corresponds to the threshold voltage Vth of the drive transistor Tr2. By adding this detection voltage to the input potential, the influence of the threshold voltage Vth on the output current Ids of the drive transistor Tr2 is canceled. Further, the drive transistor Tr2 shortens the length of the channel region to give the output current Ids a dependency on the voltage between the source S and the drain D, thereby self-correcting the dependency of the output current Ids on the carrier mobility μ. Yes.

1 is a block diagram showing a first embodiment of a display device according to the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a pixel circuit included in the display device illustrated in FIG. 1. It is a timing chart with which it uses for operation | movement description of 1st Embodiment. It is a graph similarly provided for operation | movement description of 1st Embodiment. It is a graph similarly provided for operation | movement description. It is a circuit diagram which shows 2nd Embodiment of the display apparatus and pixel circuit concerning this invention. It is a timing chart with which it uses for operation | movement description of 2nd Embodiment. It is a circuit diagram which shows 3rd Embodiment of the display apparatus and pixel circuit concerning this invention. It is a circuit diagram which shows 4th Embodiment of the display apparatus and pixel circuit concerning this invention. It is a timing chart used for operation | movement description of 4th Embodiment. It is a circuit diagram which shows 5th Embodiment of the display apparatus and pixel circuit concerning this invention. It is a timing chart with which it uses for operation | movement description of 5th Embodiment. It is a circuit diagram which shows 6th Embodiment of the display apparatus and pixel circuit concerning this invention. It is a timing chart used for operation | movement description of 6th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel circuit, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 6 ... Drive scanner, 7 ... Correction scanner, Tr1 ... Sampling transistor, Tr2 ... Drive transistor, Cs1 ... Capacitance element, Cs2 ... Capacitance element, EL ... Light emitting element

Claims (4)

A row-shaped scanning line for supplying a control pulse and a column-shaped signal line for supplying a video signal are arranged at a crossing portion, and includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element,
The sampling transistor conducts in response to a control pulse supplied from the scanning line during a predetermined sampling period and samples the video signal supplied from the signal line,
The capacitor unit holds an input potential corresponding to the sampled video signal,
The drive transistor supplies an output current during a predetermined light emission period according to an input potential held in the capacitor, and the output current is dependent on the carrier mobility and threshold voltage of the channel region of the drive transistor. Have
In the pixel circuit that emits light with luminance according to the video signal by the output current supplied from the drive transistor,
The correction means for correcting the dependency of the output current on the threshold voltage is provided, and the correction means is connected to the drive transistor and the capacitor unit, and is in a correction period set prior to the sampling period. Operates, detects the potential difference appearing between the source and gate of the drive transistor by cutting off the energization after resetting the potential held by the capacitor by energizing the capacitor,
The capacitor unit holds a potential corresponding to the detected potential difference, and the held potential cancels the influence of the threshold voltage on the output current of the drive transistor,
Further, the drive transistor shortens the length of its channel region to give the output current a dependency on the source-drain voltage, thereby self-correcting the dependency of the output current on the carrier mobility. Pixel circuit.   2. The pixel circuit according to claim 1, wherein the channel length of the drive transistor is shortened to 5 μm or less. Including a pixel array unit, a scanner unit, and a signal unit,
The pixel array section is composed of scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in a portion where both intersect.
The signal unit supplies a video signal to the signal line,
The scanner unit supplies a control pulse to the scanning line to sequentially scan pixels for each row,
Each pixel includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element,
The sampling transistor is configured to sample a video signal supplied from a signal line by conducting in response to a sampling control pulse supplied from a scanning line during a predetermined sampling period,
The capacitor unit holds an input potential corresponding to the sampled video signal,
The drive transistor supplies an output current during a predetermined light emission period according to an input potential held in the capacitor, and the output current is dependent on the carrier mobility and threshold voltage of the channel region of the drive transistor. Have
In the display device that emits light with luminance according to the video signal by the output current supplied from the drive transistor,
Each pixel includes correction means for correcting the dependency of the output current on the threshold voltage,
The correction means is connected to the drive transistor and the capacitor unit, operates in a correction period set prior to the sampling period, energizes the capacitor unit, and resets the potential held by the capacitor unit Then, the current supply is cut off and a potential difference appearing between the source and gate of the drive transistor is detected,
The capacitor unit holds a potential corresponding to the detected potential difference, and the held potential cancels the influence of the threshold voltage on the output current of the drive transistor,
Further, the drive transistor shortens the length of its channel region to give the output current a dependency on the source-drain voltage, thereby self-correcting the dependency of the output current on the carrier mobility. Display device. 4. The display device according to claim 3, wherein a length of a channel region of the drive transistor is shortened to 5 μm or less.

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