JP2006208745A - Pixel circuit and display device, and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit capable of sufficiently writing even a fine signal current of black level, and a display device and a driving method thereof. <P>SOLUTION: A signal current Isig flowing through a signal line SL is supplied to a driving transistor Trd, a signal voltage Vcs1 developed at its gate G at this time is sampled. A designated reference current Iref flowing to the signal line SL before or after the signal current Isig is supplied to the driving transistor Trd to sample a reference voltage Vcs1' developed at the gate G at this time in an external pixel capacitor Cs'. Further, an internal pixel capacitor Cs1 and the external pixel capacitor Cs1' where the signal voltage Vcs1 and reference voltage Vcs1' are sampled are connected to each other and the difference is obtained and held as a control voltage Vcs1'' in the internal pixel capacitor Cs1. The driving transistor Trd receives the control voltage Vcs1'' at its gate and supplies a driving current Ids to a light emitting element EL, which is made to emit light. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit that drives a light emitting element arranged for each pixel in a current and a driving method thereof. In addition, the pixel circuit is a display device in which the pixel circuits are arranged in a matrix (matrix), and the amount of current supplied to a light emitting element such as an organic EL is controlled by an insulated gate field effect transistor provided in each pixel circuit. The present invention relates to a so-called active matrix display device and a driving method thereof.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, the current flowing through the light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  FIG. 15 is a schematic block diagram showing a conventional active matrix organic EL display. As shown in the figure, this display device is composed of a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit section includes a current driver 3, a write scanner 4, a drive scanner 5, a correction scanner 7, and the like. The pixel array 1 includes row-like scanning lines WS and column-like signal lines SL, and pixels R, G, and B arranged in a matrix at the intersection of the two. In order to enable color display, RGB three primary color pixels are prepared, but monochrome display monochrome pixels may be used instead. Each pixel R, G, B is composed of a pixel circuit 2. The signal line SL is driven by a current driver 3 so that a signal current flows. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS and AZ are also wired in parallel with the scanning line WS. The scanning line DS is scanned by the drive scanner 5. The drive scanner 5 controls the light emission period of the light emitting elements included in each pixel. The scanning line AZ is scanned by the correction scanner 7. The light scanner 4, the drive scanner 5, and the correction scanner 7 constitute a scanner unit as a whole, and sequentially scan the pixel rows every horizontal period.

  FIG. 16 is a circuit diagram showing a configuration example of the pixel circuit shown in FIG. As shown in the drawing, the pixel circuit 2 is composed of four transistors Tr1, Tr4, Tr5, Trd, one pixel capacitor Cs, and one light emitting element EL. All of the four transistors are thin film transistors. Among these, the transistors Tr1, Tr4 and Tr5 are control switching transistors, and all of them are N-channel type. On the other hand, the transistor Trd is a driving transistor for driving the light emitting element EL, and uses a P-channel type. The light-emitting element EL is a two-terminal self-light-emitting element having an anode and a cathode. For example, an organic EL element can be used.

  The source S of the drive transistor Trd is connected to the power supply Vcc. The drain D is located on the anode side of the light emitting element EL. The cathode side of the light emitting element EL is grounded. The gate G of the drive transistor Trd is connected to one end of the pixel capacitor Cs. The other end of the pixel capacitor Cs is connected to the power supply Vcc.

  The source / drain of the switching transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Trd. The gate of the switching transistor Tr1 is connected to the scanning line WS. The source / drain of the switching transistor Tr4 is connected between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr4 is connected to the scanning line AZ. The source / drain of the switching transistor Tr5 is connected between the drain D of the driving transistor Trd and the anode of the light emitting element EL. The gate of this transistor Tr5 is connected to the scanning line DS.

The drive transistor Trd operates in the saturation region, and its characteristics are expressed by the following Equation 1.

  In Equation 1, Vgs is a gate voltage and represents a voltage between the source S and the gate G of the drive transistor Trd. Ids is a drain current, which flows between the source S and the drain D of the driving transistor Trd and is supplied to the light emitting element EL. Vth represents the threshold voltage of the drive transistor Trd. μ similarly represents the carrier mobility of the drive transistor Trd. K is a constant and is given by Cox · W / L. Here, Cox is the gate capacitance of the drive transistor Trd, W is the channel width, and L is the channel length. The constant k may be called a size factor. When the drive transistor Trd operates in the saturation region, the drain current Ids begins to flow from the time when the gate voltage Vgs exceeds the threshold voltage Vth, as is apparent from the above formula 1. The magnitude of the drain current Ids increases in proportion to the square of the gate voltage Vgs. In this specification, the threshold voltage Vth of the driving transistor is assumed to be an absolute value of the threshold voltage of the driving transistor. Incidentally, since the threshold voltage has a negative value in a P-channel transistor, it is not correct if the value is directly put into the above equation 1. Therefore, in this specification, an absolute value is taken and Vth is handled as a positive value.

  The drive transistor Trd is, for example, a TFT having a polycrystalline silicon thin film as an active layer. As the polycrystalline silicon thin film, low-temperature polysilicon crystallized by laser annealing is often used. In general, low-temperature polysilicon TFTs tend to vary in threshold voltage Vth and carrier mobility μ for each device. In other words, Vth and μ of the drive transistor Trd are different for each pixel circuit 2.

上記数式２は数式１のドレイン電流Ｉｄｓを信号電流Ｉｓｉｇで置き換えたものとなっている。 The pixel circuit 2 performs a sampling operation and a light emission operation roughly. In the first sampling operation, the transistor Tr5 is turned off while the transistors Tr1 and Tr4 are turned on. When the signal line SL is driven by the current driver 3 in this state, the signal current Isig flows from the power source Vcc to the signal line SL through the driving transistor Trd and the switching transistors Tr4 and Tr1. The operating characteristic of the drive transistor Trd at this time is expressed by the following Equation 2.

Equation 2 above is obtained by replacing the drain current Ids of Equation 1 with the signal current Isig.

The gate voltage Vgs appearing between the gate G and the source S of the drive transistor Trd when the signal current Isig flows is expressed as the following Expression 3 by solving Expression 2 with Vgs.

  The gate voltage Vgs expressed by Equation 3 is held in the pixel capacitor Cs. In this manner, in the sampling operation, the gate voltage Vgs corresponding to the level of the signal current Isig supplied by the current driver 3 is written into the pixel capacitor Cs. In short, the signal current Isig is written to the gate of the drive transistor Trd.

Subsequently, in the light emitting operation, the transistors Tr1 and Tr4 are turned off while the Tr5 is turned on. As a result, the drive current Ids flows from the drive transistor Trd to the light emitting element EL, and emits light with a predetermined luminance. At this time, the drive current Ids flowing through the drive transistor Trd is expressed by the following Equation 4.

  Substituting Vgs obtained by Equation 3 into Vgs of Equation 4 results in cancellation of the terms of mobility μ and threshold voltage Vth, and Ids = Isig. Therefore, even if the mobility μ and the threshold voltage Vth of the drive transistor Trd vary from pixel to pixel, the signal current writing operation described above cancels all of them, and the screen uniformity can be maintained.

  The conventional pixel circuit shown in FIG. 16 has an advantage that the same drive current Ids as the signal current Isig can be supplied to the light emitting element EL regardless of variations in the mobility μ and the threshold voltage Vth of the drive transistor. The current driver 3 can change the luminance of the light emitting element EL from the black level to the white level through the intermediate gray level by controlling the level of the signal current Isig. At the black level, the signal current Isig is weak and approaches 0, while at the white level, the signal current Isig is large. However, the parasitic capacitance of the signal line SL is relatively large, such as several tens of pF, and in the conventional configuration shown in FIG. 16, the black level signal current Isig having a weak current value is assigned to one horizontal video period ( 1H), there was a problem that writing could not be performed sufficiently.

  FIG. 17 schematically shows this problem. The pixel array 1 constitutes a screen, and is a case where a white window is displayed on a black background. A gray area appears below the white window. Originally, this gray part belongs to the background and must be black. However, in the conventional pixel circuit configuration shown in FIG. 16, black level signal current cannot be written to the pixel located below the white window, and black floating and vertical crosstalk as shown in the figure occur. It has become a problem to be solved.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a pixel circuit and a display device capable of sufficiently writing a black level signal current, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, the present invention includes a light emitting element, a driving transistor for supplying a driving current to the light emitting element, and a pixel capacitor, which are arranged at a portion where a signal line through which a signal current flows and a scanning line for supplying a control signal intersect. A pixel circuit that operates in response to the control signal and controls a drive current of the drive transistor based on the signal current, the control unit sending a signal current flowing through the signal line to the drive transistor; A first sampling means for sampling a signal voltage generated at the gate at that time into one of an internal pixel capacitor disposed in the pixel circuit or an external pixel capacitor disposed in a pixel circuit different from the pixel circuit; A predetermined reference current flowing in the signal line before and after the signal current is passed through the driving transistor, and a reference voltage generated at the gate at that time is set to the internal pixel capacitance or the external pixel capacitance. A second sampling means for sampling the signal voltage, and the internal pixel capacity and the external pixel capacity obtained by sampling the signal voltage and the reference voltage are mutually connected to obtain a difference, and the obtained difference is held in the internal pixel capacity as a control voltage. The driving transistor receives the control voltage held in the internal pixel capacitor at the gate and supplies a driving current flowing between the source and drain to the light emitting element to emit light. And

  Specifically, the signal voltage and the reference voltage sampled respectively by the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element is small and when the difference is large, the light emission amount is large. On the other hand, even when the relative difference between the two is small, the absolute levels of the signal current and the reference current are set so as to enable sampling. Preferably, the control unit detects a threshold voltage of the driving transistor, holds the threshold voltage in an additional pixel capacitor, and adds the held threshold voltage to the control voltage held in the internal pixel capacitor. Means for canceling the influence of the threshold voltage from the drive current. The control unit uses an internal pixel capacity and an external pixel capacity having the same capacitance value.

  The present invention also includes a pixel array section, a driver section, and a scanner section, and the pixel array section includes column-shaped signal lines, row-shaped scanning lines, and matrix-shaped pixels arranged at portions where the two intersect. The driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, and each pixel circuit supplies a light emitting element and a driving current to the light emitting element. A display device comprising: a drive transistor to be supplied; and an in-pixel control unit that includes a pixel capacitor and operates according to the control signal and controls the drive current of the drive transistor based on the signal current. The control unit distributes a signal current flowing through the signal line to the driving transistor, and a signal voltage generated at the gate at that time is disposed in an internal pixel capacitor disposed in the pixel circuit or in a pixel circuit different from the pixel circuit. A first sampling means for sampling to one of the external pixel capacitors; and a predetermined reference current flowing through the signal line before and after the signal current is passed through the driving transistor, and a reference voltage generated at the gate at that time is used as an internal pixel capacitor or an external pixel. A second sampling means for sampling to the other of the capacitors; and the internal pixel capacitor and the external pixel capacitor that sample the signal voltage and the reference voltage are connected to each other to obtain a difference; And the driving transistor receives the control voltage held in the internal pixel capacitor at the gate and supplies a driving current flowing between the source and the drain to the light emitting element to emit light. It is characterized by.

  Specifically, the signal voltage and the reference voltage sampled respectively by the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element is small and when the difference is large, the light emission amount is large. On the other hand, even when the relative difference between the two is small, the absolute levels of the signal current and the reference current are set so as to enable sampling. Preferably, the intra-pixel control unit detects a threshold voltage of the driving transistor, holds the threshold voltage in another pixel capacitor, and sets the held threshold voltage to the control voltage held in the internal pixel capacitor. Compensation means is provided for canceling the influence of the threshold voltage from the drive current. Preferably, the intra-pixel control unit uses an internal pixel capacitance and an external pixel capacitance having the same capacitance value.

  The present invention further includes a light emitting element, a driving transistor for supplying a driving current to the light emitting element, and a pixel capacitor, which are arranged at a portion where a signal line through which a signal current flows and a scanning line for supplying a control signal intersect. A pixel circuit driving method comprising: a controller that operates in accordance with the control signal and controls the driving current of the driving transistor based on the signal current, wherein the signal current flowing through the signal line is passed through the driving transistor. A first sampling procedure for sampling a signal voltage generated at the gate into one of an internal pixel capacitor disposed in the pixel circuit or an external pixel capacitor disposed in a pixel circuit different from the pixel circuit; A predetermined reference current flowing in the signal line before and after the current is passed through the drive transistor, and a reference voltage generated at the gate at that time is set in addition to the internal pixel capacitance or the external pixel capacitance. A second sampling procedure for sampling the signal voltage, and the internal pixel capacitance and the external pixel capacitance obtained by sampling the signal voltage and the reference voltage are mutually connected to obtain a difference, and the obtained difference is held in the internal pixel capacitance as a control voltage. A difference procedure and a light emission procedure in which the control voltage is applied to the gate of the drive transistor and a drive current flowing between the source and the drain is supplied to the light emitting element are performed.

  In addition, the present invention includes a pixel array unit, a driver unit, and a scanner unit, and the pixel array unit has a matrix signal line, a row-shaped scanning line, and a matrix-like arrangement arranged at the intersection of the two. The pixel circuit includes a pixel circuit, the driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, and each pixel circuit supplies a light emitting element and a driving current to the light emitting element. A display device driving method comprising: a driving transistor for driving and a pixel capacitor, wherein the driving current of the driving transistor is controlled based on the signal current according to the control signal, wherein the driving current is supplied to the signal line. A first sub-sample that samples the signal voltage generated at the gate through the transistor at one of the internal pixel capacitor disposed in the pixel circuit or the external pixel capacitor disposed in a pixel circuit different from the pixel circuit. A pulling procedure, and a second sampling for sampling a reference voltage generated at the gate of the predetermined reference current flowing in the signal line before and after the signal current to the other of the internal pixel capacitance or the external pixel capacitance. A difference procedure for obtaining a difference by connecting the internal pixel capacitance and the external pixel capacitance obtained by sampling the signal voltage and the reference voltage, and holding the obtained difference in the internal pixel capacitance as a control voltage; and the control A light emission procedure is performed in which a voltage is applied to the gate of the driving transistor and a driving current flowing between the source and the drain is supplied to the light emitting element.

  The display device according to the present invention supplies not only a signal current but also a reference current from the current driver side. The pixel circuit samples the signal current and the reference current into a pair of capacitors before and after, and further obtains the difference between the two by a capacitance canceling operation, which is used as the gate control voltage of the driving transistor. Thereby, the drive transistor can drive the light emitting element according to the difference of the signal current with respect to the reference current. At this time, the difference in the light emission luminance at the black level is close to 0, and the signal current is substantially the same as the reference current. Even in such a state, the absolute values of the signal current and the reference current can be set sufficiently higher than the parasitic capacitance of the signal line. Therefore, even a black level current can be written into each pixel at a sufficiently high speed, and black floating and vertical crosstalk, which have been problems in the past, can be prevented. Since the level of the signal current and the reference current can be set high without depending on the luminance gradation to be displayed, even the black display current can be sufficiently written to the pixels within one horizontal period, and the luminance is sufficiently reduced. It is possible to express black and obtain high contrast characteristics. In addition, since the drive current for the light emitting element is controlled by obtaining the difference between the signal current and the reference current without depending on the threshold voltage or mobility of the drive transistor, a high uniformity is achieved without being affected by variations in the characteristics of the drive transistor. Mitty's image can be displayed. In particular, the effect of the present invention is significant in a pixel circuit using a low-temperature polysilicon TFT whose mobility and threshold voltage vary greatly.

  In particular, in the present invention, when sampling the signal current and the reference current into a pair of capacitors, an internal pixel capacitor disposed in the pixel circuit and an external pixel capacitor disposed in a pixel circuit different from the pixel circuit are used. ing. As a result, the number of capacitive elements per pixel circuit can be reduced. In other words, the pixel capacity included in one pixel circuit is used by another pixel circuit, thereby reducing the number of capacitive elements. Naturally, when the other pixel circuit described above samples the signal current and the reference current, the capacitive element used as the external pixel capacitance is now the internal pixel capacitance.

  Hereinafter, the present invention will be described in detail with reference to the drawings. Before proceeding to the description of the embodiments of the invention, in order to clarify the background of the present invention, a pixel circuit according to a reference example on which the present invention is based will be described. FIG. 1 is a circuit diagram showing this reference example. As shown in the drawing, the pixel circuit 2 is arranged at a portion where the column-shaped signal lines SL and the row-shaped scanning lines WS1, WS2, WS3, AZ, DS intersect. A signal current Isig and a reference current Iref are passed through the signal line SL from a current driver (not shown). Control signals WS1, WS2, WS3, AZ, and DS are supplied from the corresponding scanners to the scanning lines WS1, WS2, WS3, AZ, and DS, respectively. In this specification, in order to simplify the notation, the same reference numerals are used for the scanning lines and the corresponding control signals. The pixel circuit shown in FIG. 1 can be incorporated into a pixel array of a display device as shown in FIG. 15, for example. In this case, the corresponding control signals WS1, WS2 and WS3 are supplied from the write scanner 4 to the scanning lines WS1, WS2 and WS3, respectively. A control signal AZ is supplied to the scanning line AZ from the correction scanner 7. Further, a control signal DS is supplied from the drive scanner 5 to the scanning line DS.

  The pixel circuit 2 includes eight switching transistors Tr1 to Tr8, one drive transistor Trd, three pixel capacitors Cs1 to Cs3, and a light emitting element EL. The switching transistors Tr1 to Tr8 are all N-channel thin film transistors. The drive transistor Trd is a P-channel thin film transistor. The light emitting element EL is a two-terminal (diode type) light emitting element having an anode and a cathode, and for example, an organic EL element can be used. In the above embodiment, the transistors Tr1 to Tr8 are all N-channel type, but they may all be P-channel type or a mixture of N-channel type and P-channel type.

  The drive transistor Trd has its source S connected to the power supply Vcc, its drain D connected to the anode side of the light emitting element EL via the switching transistor Tr1, and its gate G connected to one end of the pixel capacitor Cs3. A control signal DS is applied from the scanning line DS to the gate of the switching transistor Tr1 interposed between the drive transistor Trd and the light emitting element EL. A switching transistor Tr2 is connected between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr2 is connected to the scanning line AZ.

  The source / drain of the switching transistor Tr3 is connected between the signal line SL and the other end of the pixel capacitor Cs3. The gate of the transistor Tr3 is connected to the scanning line WS1. The switching transistor Tr5 is connected between the other end of the pixel capacitor Cs3 and one end of the pixel capacitor Cs1. The gate of the switching transistor Tr5 is connected to the scanning line WS1 like the transistor Tr3. The other end of the pixel capacitor Cs1 is connected to the power supply Vcc. The switching transistor Tr4 is connected between the power supply Vcc and one end of the pixel capacitor Cs2. The gate of the switching transistor Tr4 is connected to the scanning line WS2. The other end of the pixel capacitor Cs2 is connected to the other end of the pixel capacitor Cs3. The switching transistor Tr6 is connected between one end of the pixel capacitor Cs1 and one end of the pixel capacitor Cs2. The gate of the transistor Tr6 is connected to the scanning line WS3. The transistor Tr7 is connected between the other end of the pixel capacitor Cs1 and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr7 is connected to the scanning line WS3 like Tr6. Finally, the switching transistor Tr8 is connected between the drain D of the driving transistor Trd and the other end of the pixel capacitor Cs3. The gate of the transistor Tr8 is connected to the scanning line WS1 like the switching transistors Tr3 and Tr5.

  FIG. 2 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. A change in the waveform of the control signals DS, AZ, WS1, WS2, and WS3 is represented along the time axis T. At the same time, the waveform change of the signal current Isig is also shown. The signal level of the signal current Isig changes every horizontal period (1H). Further, after the signal current Isig flows in the first half within each horizontal period, the second half switches to a predetermined reference current Iref. While the reference current Iref is fixed, the signal current Isig changes according to the video signal. This display device writes one screen in the pixel array in one field. In the timing chart of FIG. 2, it is described that one field starts from the timing T1.

  In a period T0 before the timing T1 when the field starts, the control signal DS is at a high level, while the remaining control signals AZ, WS1, WS2, and WS3 are at a low level. Since the control signal DS is at a high level, the switching transistor Tr1 is turned on, and the light emitting element EL is driven by the drive transistor Trd and is in a light emitting state.

  When the field starts at timing T1, the control signals AZ and WS3 are switched from the low level to the high level. Thus, a preparation state for detecting the threshold voltage Vth of the drive transistor Trd is entered. Subsequently, at timing T2, the control signal DS is switched from the high level to the low level, the light emitting element EL changes from the light emitting state to the non-light emitting state, and the threshold voltage Vth of the driving transistor Trd is detected. Subsequently, at timing T3, the control signals AZ and WS3 become low level, and the detected threshold voltage is held and fixed. This held and fixed Vth is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd at a later light emission stage. Therefore, a period T2-T3 from timing T2 to timing T3 may be referred to as a Vth correction period.

  When the timing T4 is reached, the control signals WS1 and WS2 are switched to a high level. At this time, the signal current Isig flows through the signal line SL. This signal current Isig is sampled and written into the pixel circuit 2. Subsequently, when the control signal WS2 is switched to the low level at the timing T5, the Isig writing is completed. A period in which Isig is sampled from timing T4 to timing T5 may be referred to as an Isig writing period.

  Subsequently, when the current flowing through the signal line SL is switched from the signal current Isig to Iref after the timing T5, the reference current Iref is sampled. When the control signal WS1 returns to the low level at the timing T6, the writing of Iref is completed. A period T5-T6 from timing T5 to timing T6 is called an Iref writing period.

  As is clear from the above description, Isig writing and Iref writing are sequentially performed while the control signal WS1 is at the high level from timing T4 to T6. The period T4-T6 during which the control signal WS1 is at the high level is exactly one horizontal period (1H). It is possible to sample Isig and Iref sequentially in one horizontal period 1H assigned to the pixel circuit 2.

  Thereafter, the control signal WS3 rises at timing T7, and the control signal WS3 falls similarly at timing T8. The difference between Isig and Iref is obtained in the period T7-T8 when the control signal WS3 is at the high level. This difference is performed by the cancel operation of the pixel capacitors Cs1 and Cs2. Therefore, this period T7-T8 may be referred to as a capacity cancellation period.

  At timing T9, the control signal DS changes to high level and the control signal WS2 also becomes high level. As a result, the pixel capacitors Cs2 and Cs3 are coupled, and the drive current Ids is supplied from the drive transistor Trd to the light emitting element EL, and the light emission operation is performed.

  FIG. 3 is a schematic diagram showing a Vth cancel operation performed in the Vth correction period T2-T3 shown in FIG. In this period T2-T3, the switching transistors Tr1, Tr3, Tr4, Tr5, Tr8 are turned off, while Tr2, Tr6, and Tr7 are turned on. As a result, one end of the pixel capacitor Cs3 is connected to the gate of the drive transistor Trd, while the other end is connected to the power supply Vcc via the transistor Tr7. When the switch Tr1 is turned off while a current is flowing from the power source Vcc toward the light emitting element EL, the current path is cut off, so that the pixel capacitor Cs3 is charged through the transistor Tr2. With this charging, the gate potential of the drive transistor Trd rises. The drive transistor Trd is cut off just when the gate potential becomes Vth of the drive transistor Trd. Vth of the drive transistor Trd detected at this time is held at both ends of the pixel capacitor Cs3. Thereafter, the transistor Tr2 is turned off, and Vth held in the pixel capacitor Cs3 is fixed. The Vth held and fixed in this way is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd in a later light emission operation.

上記数式５において、Ｖｇｓは駆動トランジスタＴｒｄのゲートソース間に現れるゲート電圧を表し、Ｖｔｈは同じく駆動トランジスタＴｒｄの閾電圧を表し、ｋは同じく駆動トランジスタＴｒｄのサイズファクタを表し、μは同じく移動度を表している。 FIG. 4 is a schematic diagram showing the Isig write operation performed in the period T4-T5 shown in the timing chart of FIG. In this period, the signal current Isig flows through the signal line. Further, the transistors Tr1, Tr2, Tr6, Tr7 are turned off, while the transistors Tr3, Tr4, Tr5, Tr8 are turned on. As a result, the signal current Isig flows from the power source Vcc to the signal line side through the drive transistor Trd, the switching transistor Tr8, and the switching transistor Tr3. In other words, Isig flows through the drive transistor Trd as a drain current. Therefore, in accordance with the basic characteristics of the transistor expressed by Equation 1, the drain current Isig is expressed by Equation 5 below.

In Equation 5, Vgs represents the gate voltage appearing between the gate and source of the drive transistor Trd, Vth represents the threshold voltage of the drive transistor Trd, k represents the size factor of the drive transistor Trd, and μ represents the mobility. Represents.

Here, when formula 5 is arranged for Vgs, the following formula 6 is obtained.

Referring to FIG. 4, pixel capacitors Cs2 and Cs3 are connected in series between the source and gate of the drive transistor Trd. Here, when the voltage held at both ends of the pixel capacitor Cs2 is Vcs2, and the voltage held in the pixel capacitor Cs3 is Vcs3, the gate voltage Vgs = Vcs2 + Vcs3. Here, Vcs3 is set to Vth by the previous Vth cancel operation. Therefore, Vgs = Vcs2 + Vth. By substituting Vgs given by Equation 6 into Vgs in this equation, the voltage Vcs2 held in the pixel capacitor Cs2 is given by Equation 7 below.

  As is clear from Equation 7, the voltage Vcs2 held in the pixel capacitor Cs2 is proportional to the square root of the signal current Isig. In other words, the voltage Vcs2 corresponding to the signal current Isig is sampled and held in the pixel capacitor Cs2 by the Isig writing operation in the period T4-T5.

FIG. 5 is a schematic diagram showing an Iref write operation performed in the period T5-T6 shown in FIG. When the Isig write operation shown in FIG. 4 proceeds to the Iref write operation of this figure, the control line WS2 goes low, and as a result, the transistor Tr4 is turned off. The states of the other switching transistors are maintained as they are. Therefore, as apparent from a comparison between FIGS. 4 and 5, the pixel capacitance Cs2 is switched to the pixel capacitance Cs1. More specifically, in the Isig write operation of FIG. 4, the pixel capacitors Cs2 and Cs3 are connected in series between the source / gate of the drive transistor Trd, whereas in the Iref write operation of FIG. 4, the drive transistor Trd. A pixel capacitor Cs1 and a pixel capacitor Cs3 are connected in series between the source and the gate. That is, as a circuit operation, Cs2 is simply replaced by Cs1. At this time, Iref flows in the signal line instead of the previous Isig. More specifically, the reference current Iref flows from the power source Vcc through the drive transistor Trd and further flows to the signal line side via the switching transistors Tr8 and Tr3. At this time, a part of the gate voltage Vgs generated between the source and the gate of the drive transistor Trd is held in the pixel capacitor Cs1. Assuming that this voltage is Vcs1, it is expressed as in the following Expression 8 in exactly the same manner as in Expression 7.

  Here, as apparent from a comparison between Expression 7 and Expression 8, the left side of the expression is replaced from Vcs2 to Vcs1, while the right side of the expression is replaced from Isig to Iref. As is apparent from Equation 8, the voltage Vcs1 held in the pixel capacitor Cs1 corresponds to the square root of the reference current Iref. In other words, in this Iref writing operation, a voltage corresponding to the reference current Iref is sampled in the pixel capacitor Cs1.

FIG. 6 is a schematic diagram illustrating the capacity canceling operation performed in the period T7 to T8 in the timing chart illustrated in FIG. In this operation, the switching transistors Tr3, Tr5 and Tr8 are turned off, while Tr6 and Tr7 are turned on. As a result, the negative terminal of the pixel capacitor Cs1 and the positive terminal of the pixel capacitor Cs2 are connected, and the positive terminal of the pixel capacitor Cs1 and the negative terminal of the pixel capacitor Cs2 are connected. Thereby, the capacity cancellation of the pixel capacities Cs1 and Cs2 is performed between Vcs1 and Vcs2. That is, a difference between the voltage Vcs1 held in the pixel capacitor Cs1 and the voltage Vcs2 held in the pixel capacitor Cs2 is obtained, and this difference is held at both ends of the pixel capacitor Cs2. Here, when the pixel capacitors Cs1 and Cs2 have the same capacitance, the potential Vcs2 ′ held in the pixel capacitor Cs2 after the capacitance cancellation is given by the following Equation 9.

  As is apparent from Equation 9, Vcs2 ′ is a value corresponding to the difference between the signal current Isig and the reference current Iref. Precisely, a voltage corresponding to the difference between the square root of Isig and the square root of Iref is held as Vcs2 ′ in the pixel capacitor Cs2.

  FIG. 7 is a schematic diagram showing capacitive coupling and light emission operation in a light emission period performed after timing T9 shown in FIG. When the timing T9 is reached, the control signals DS and WS2 become high level, while the other control signals are all at low level. Accordingly, the switching transistors Tr4 and Tr1 are turned on, while the remaining switching transistors Tr3, Tr5, Tr6, Tr7, Tr2, and Tr8 are turned off. Since Tr4 is turned on, the pixel capacitors Cs2 and Cs3 are coupled between the source and gate of the drive transistor Trd. At this time, since the gate capacitance Cg of the drive transistor Trd is sufficiently small, the pixel capacitances Cs2 and Cs3 are coupled in a state in which the mutual charges are held. That is, the gate voltage Vgs of the drive transistor Trd during light emission is Vgs = Vcs3 + Vcs2 ′ = Vth + Vcs2 ′.

When Vgs obtained in this way is included in the basic characteristic equation of the transistor shown in Equation 1, a drive current Ids as shown in Equation 10 below can be obtained.

  In the first stage of Equation 10, Vth + Vcs2 ′ is substituted for Vgs. As a result, Vth is canceled and the drive current Ids takes a form proportional to the square of Vcs2 ′. Further, as shown in the second stage of Expression 10, Expression 9 is substituted into Vcs2 ′. Thereafter, the mobility μ appearing in the denominator and the mobility μ of the coefficient part are canceled, and finally the form represented by the third stage of Equation 10 is obtained. As is apparent from this equation, the drive current (light emission current) Ids is determined by the current difference value between Isig and Iref, and high uniformity image quality can be obtained regardless of variations in Vth and mobility μ of the drive transistor. . Furthermore, in the pixel circuit of the present invention, Isig = Iref is set during black display. As is apparent from Equation 10, when Isig = Iref, Ids = 0 and the light emission current disappears. This results in a complete black display. On the other hand, even in black display, the absolute value of Iref can be set to a sufficiently high level, and a black signal can be sufficiently written within one horizontal period (1H). As a result, it is possible to suppress the occurrence of black floating and vertical crosstalk, and it is possible to express completely sunken black and obtain high contrast characteristics.

  As described above, the pixel circuit according to the first embodiment of the present invention shown in FIG. 1 includes the signal line SL through which the signal current Isig flows and the scanning lines WS1, WS2, WS3, AZ, DS that supply control signals. It is arranged at the intersection of and. The pixel circuit 2 includes a light-emitting element EL, a drive transistor Trd that supplies a drive current Ids to the light-emitting element EL, and operates according to control signals WS1, WS2, WS3, AZ, DS, and a drive transistor based on the signal current Isig. It is comprised with the control part which controls the drive current Ids of Trd. The control unit includes first sampling means, second sampling means, and difference means. The first sampling means is composed of transistors Tr3, Tr4, Tr8 and a pixel capacitor Cs2. A signal current Isig flowing through the signal line SL is passed through the drive transistor Trd, and the signal voltage Vcs2 generated at the gate G at that time is a first voltage. Sampling is performed on the capacitor Cs2. The second sampling means is composed of transistors Tr3, Tr5, Tr8 and a pixel capacitor Cs1, and passes a predetermined reference current Iref flowing in the signal line SL before and after the signal current Isig through the driving transistor Trd, and a reference generated at the gate G at that time. The voltage Vcs1 is sampled to the second capacitor Cs1. The difference means includes transistors Tr6 and Tr7 and a pair of pixel capacitors Cs1 and Cs2, and connects the first capacitor Cs2 sampled from the signal voltage Vcs2 and the second capacitor Cs1 sampled from the reference voltage Vcs1 to each other. Then, the difference Vcs2 ′ is obtained, and the obtained difference Vcs2 ′ is held in Cs2, which is one of the first and second capacitors, as the control voltage. The drive transistor Trd receives the control voltage Vcs2 ′ held in Cs2, which is one of the first and second capacitors, at the gate G, and generates a drive current Ids flowing between the source (S) and the drain (D) as the light emitting element EL. To emit light.

  The signal voltage Vcs2 and the reference voltage Vcs1 sampled respectively by the first and second sampling means are such that the light emission amount of the light emitting element EL is small when the relative difference Vcs2 ′ between them is small and the light emission amount is large when the difference Vcs2 ′ is large. On the other hand, the absolute levels of the signal current Isig and the reference current Iref are set so as to enable sampling even when the relative difference Vcs2 ′ between them is small.

  The control unit in the pixel circuit 2 described above has correction means in addition to the first and second sampling means and the difference means. This correcting means is composed of transistors Tr1, Tr2, Tr7 and a pixel capacitor Cs3, and detects the threshold voltage Vth of the driving transistor Trd and holds it in the third capacitor Cs3 before obtaining the above-described difference Vcs2 ′. Thereafter, the held threshold voltage Vth is added to the control voltage Vcs2 ′ held in Cs2 which is one of the first and second capacitors. Thereby, the influence of the threshold voltage Vth can be canceled from the drive current Ids.

  The pixel circuit according to the reference example described above uses a pair of pixel capacitors Cs1 and Cs2 in order to sample the signal current and the reference current. Further, an additional pixel capacitor Cs3 is provided to detect and hold the threshold voltage of the driving transistor. Therefore, the pixel circuit according to the reference example uses three pixel capacitors Cs1, Cs2, and Cs3 for convenience. However, since the pixel capacity has a high area occupancy rate within the pixel, various restrictions are imposed on the layout. Therefore, the present invention aims to improve the above-described reference example and reduce the number of pixel capacitors required per pixel. In order to achieve this object, the configuration detailed below was obtained.

  FIG. 8 is a schematic circuit diagram showing an embodiment of a pixel circuit according to the present invention. In order to facilitate understanding, the pixel circuit 2 at the stage and the pixel circuit 2 ′ at the next stage are shown side by side. In order to facilitate understanding, corresponding reference numerals are used for portions corresponding to the reference example shown in FIG. The pixel circuit 2 in this stage is arranged at a portion where the columnar signal lines SL and the row scanning lines WS1, WS2, WS3, AZ, DS intersect. A signal current Isig and a reference current Iref are passed through the signal line SL from a current driver (not shown). Control signals WS1, WS2, WS3, AZ, and DS are supplied from the corresponding scanners to the scanning lines WS1, WS2, WS3, AZ, and DS, respectively. When such a pixel circuit is applied to the pixel array of the display device shown in FIG. 15, for example, the control signals WS1, WS2, and WS3 are supplied from the write scanner 4, the control signal AZ is supplied from the correction scanner 7, and the control signal DS Is supplied from the drive scanner 5.

  The pixel circuit 2 ′ at the next stage has the same configuration as the pixel circuit 2 at the corresponding stage. Adjacent pixel circuits 2, 2 'are connected to each other by a pair of connection lines CL1, CL2 arranged in parallel with the signal line SL. Note that elements constituting the pixel circuit 2 ′ are distinguished from corresponding elements constituting the pixel circuit 2 by adding a symbol “′” to a reference number to avoid duplicating detailed description.

  The pixel circuit 2 is largely divided into an output unit 2T and an input unit 2N. The output unit 2T is located on the light emitting element side, while the input unit 2N is located on the signal line SL side.

  The output unit 2T includes a drive transistor Trd, switching transistors Tr1, Tr2, Tr3, Tr6, a pixel capacitor Cs2, and a light emitting element EL. The drive transistor Trd is a P-channel type, and the switching transistors Tr1, Tr2, Tr3, Tr6 are all N-channel type. However, the present invention is not limited to this, and P-channel and N-channel transistors can be mixed as appropriate. The gate of the driving transistor Trd is connected to one end of the pixel capacitor Cs2. The source S is connected to the power supply Vcc. The drain D is connected to the light emitting element EL via the switching transistor Tr1. The light emitting element EL is a diode type organic EL element having an anode and a cathode. The anode is connected to the drain D side of the drive transistor Trd, while the cathode side is grounded to the cathode potential Vcatode. The gate of the switching transistor Tr1 is connected to the scanning line DS. The switching transistor Tr2 is interposed between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr2 is connected to the scanning line AZ. The switching transistor Tr3 is interposed between the source S of the driving transistor Trd and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr3 is connected to the scanning line AZ. The remaining switching transistor Tr6 is interposed between the drain D of the driving transistor Trd and the other end of the pixel capacitor Cs2. The gate of the transistor Tr6 is connected to the scanning line WS1. The other end of the pixel capacitor Cs2 is connected to the input unit 2N side. The output unit 2T ′ of the pixel circuit 2 at the next stage has the same configuration as the output unit 2T of the pixel circuit 2 at the next stage.

  On the other hand, the input section 2N is composed of six switching transistors Tr4, Tr5, Tr7, Tr8, Tr9, Tr10 and one pixel capacitor Cs1. The switching transistor Tr10 is connected between the signal line SL and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr10 is connected to the scanning line WS1. The switching transistor Tr5, the pixel capacitor Cs1, and the switching transistor Tr4 are connected in series between the power supply Vcc and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr5 is connected to the scanning line WS2. Similarly, the gate of the switching transistor Tr4 is also connected to the scanning line WS2. One end of the pixel capacitor Cs1 is connected to the connection line CL1, and the other end is connected to the connection line CL2. The switching transistor Tr8 is inserted in a connection line CL1 that connects the stage to the next stage. Similarly, the switching transistor Tr7 is inserted in a connection line CL2 connecting the corresponding stage and the next stage. The gates of these switching transistors Tr8 and Tr7 are connected to the scanning line WS3. The remaining switching transistor Tr9 is connected between the switching transistors Tr10 and Tr8. The gate of the transistor Tr9 is connected to the scanning line WS1. The input unit of the pixel circuit 2 ′ at the next stage has the same configuration.

  FIG. 9 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. A change in the waveform of the control signals DS, AZ, WS1, WS2, and WS3 is represented along the time axis T. At the same time, the waveform change of the signal current Isig is also shown. The signal level of the signal current Isig changes every horizontal period (1H). Further, after the signal current Isig flows first within each horizontal period, the remainder is switched to a predetermined reference current Iref. While the reference current Iref is fixed, the signal current Isig changes according to the video signal. This display device writes one screen in the pixel array in one field. In the timing chart of FIG. 9, one field is described so as to start from timing T1. The control signals DS, AZ, WS1, WS2, and WS3 shown in the timing chart are assigned to the pixel circuit 2 shown in FIG. For convenience of explanation, a control signal WS2 ′ supplied to the pixel circuit 2 ′ of the next stage is also shown in parallel with the control signal assigned to the stage.

  In the period T0 before the timing T1 when the field starts, the control signals DS and WS2 and WS2 ′ are at the high level, while the remaining control signals AZ, WS1 and WS3 are at the low level. Since the control signal DS is at a high level, the switching transistor Tr1 is turned on, and the light emitting element EL is driven by the drive transistor Trd and is in a light emitting state. Since the control signal WS2 is also at a high level, the pixel capacitors Cs1 and Cs2 are connected in series between the power supply Vcc and the gate G of the drive transistor Trd.

  When the field starts at timing T1, the control signal AZ is switched from the low level to the high level. Thus, a preparation state for detecting the threshold voltage Vth of the drive transistor Trd is entered. Subsequently, at timing T2, the control signals DS and WS2 are switched from the high level to the low level, the light emitting element EL changes from the light emitting state to the non-light emitting state, the pixel capacitor Cs1 is disconnected from Cs2, and the threshold voltage Vth of the driving transistor Trd Detection is performed. The detected threshold voltage Vth is held in the pixel capacitor Cs2. Subsequently, at timing T3, the control signal AZ becomes a low level, and the detected threshold voltage Vth is held and fixed in the pixel capacitor Cs2. This held and fixed Vth is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd at a later light emission stage. Therefore, the period T2-T3 from timing T2 to timing T3 may be referred to as a Vth correction period.

  When the timing T4 is reached, the control signals WS1 and WS2 are switched to a high level. At this time, the signal current Isig flows through the signal line SL. This signal current Isig is sampled and written to the pixel capacitor Cs1. Subsequently, when the control signal WS2 is switched to the low level at the timing T5, the Isig writing is completed. A period in which Isig is sampled by the pixel capacitor Cs1 from timing T4 to timing T5 may be referred to as Isig writing period T4-T5.

  Subsequently, when the current flowing through the signal line SL after the timing T5 is switched from the signal current Isig to Iref, the control signal WS2 ′ becomes high level in accordance with this, and the reference current Iref is sampled. When the control signal WS2 ′ becomes a high level, the pixel capacitor Cs1 ′ at the next stage is connected to the pair of connection lines CL1 and CL2, and thus the reference current Iref is written into the pixel capacitor Cs1 ′ at the next stage. Here, in order to distinguish between the pixel capacitor Cs1 of the current stage and the pixel capacitor Cs1 ′ of the next stage, the former may be referred to as an internal pixel capacitor Cs1 and the latter may be referred to as an external pixel capacitor Cs1 ′. When the control signal WS2 ′ returns to the low level at the timing T6, the writing of Iref is completed. A period from timing T5 to timing T6 may be referred to as an Iref writing period.

  Subsequently, the control signal WS3 rises at timing T7, and the control signal WS3 falls similarly at timing T8. The internal pixel capacitor Cs1 and the external pixel capacitor Cs1 ′ are connected in reverse polarity during a period T7-T8 when the control signal WS3 is at a high level, and the difference between the sampled Isig and Iref is obtained. This difference is performed by the cancel operation of the internal pixel capacitor Cs1 and the external pixel capacitor Cs1 ′. Therefore, this period T7-T8 may be referred to as a capacity cancellation period. As is clear from the above description, the writing of Isig and Iref and the capacity cancellation are performed while the control signals WS1, WS2, and WS3 sequentially become high level from timing T4 to T8. This period T4-T8 is exactly one horizontal period (1H). In one horizontal period 1H assigned to the pixel circuit 2, Isig sampling, Iref sampling, and an operation for obtaining a difference between the two are performed. Note that the difference obtained by the capacitance cancellation between the internal pixel capacitance Cs1 and the external pixel capacitance Cs1 ′ is held in the internal pixel capacitance Cs1.

  At timing T9, the control signal DS changes to high level and the control signal WS2 also changes to high level. As a result, the pixel capacitor Cs1 on the input unit 2N side and the pixel capacitor Cs2 on the output unit 2T side are coupled, and the drive current Ids is supplied from the drive transistor Trd to the light emitting element EL, and the light emission operation is performed.

  FIG. 10 is a schematic diagram showing a Vth cancel operation performed in the Vth correction period T2-T3 shown in FIG. During this period T2-T3, the switching transistors Tr2 and Tr3 are on, while the remaining switching transistors are all off. As a result, one end of the pixel capacitor Cs2 is connected to the gate of the drive transistor Trd, while the other end is connected to the power supply Vcc via the transistor Tr3. The drain and gate of the drive transistor Trd are directly connected by the switching transistor Tr2. Here, since the switch transistor Tr1 is turned off in a state where current flows from the power source Vcc toward the light emitting element EL, the current path is cut off, so that the pixel capacitor Cs2 is charged via the transistor Tr2. With this charging, the gate potential of the drive transistor Trd rises. The drive transistor Trd is cut off just when the gate potential becomes Vth of the drive transistor Trd. The Vth of the drive transistor Trd detected at this time is held at both ends of the pixel capacitor Cs2. Thereafter, the transistors Tr2 and Tr3 are turned off, and Vth held in the pixel capacitor Cs2 is fixed. The Vth held and fixed in this way is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd in a later light emission operation.

上記数式１１から明らかなように、画素容量Ｃｓ１に保持された信号電圧Ｖｃｓ１は信号電流Ｉｓｉｇの平方根に比例している。また、駆動トランジスタＴｒｄの閾電圧Ｖｔｈの効果は画素容量Ｃｓ２に予め保持されたＶｔｈでキャンセルされている。したがって、期間Ｔ４‐Ｔ５のＩｓｉｇ書き込み動作により、画素容量Ｃｓ１に信号電流Ｉｓｉｇに対応した正味の信号電圧Ｖｃｓ１がサンプリング保持された事になる。 FIG. 11 is a schematic diagram showing the Isig write operation performed in the period T4-T5 shown in the timing chart of FIG. In this period, the signal current Isig flows through the signal line. Further, the switching transistors Tr4, Tr5, Tr6, Tr9, and Tr10 are on, while the transistors Tr1, Tr2, Tr3, Tr7, and Tr8 are off. As a result, the signal current Isig flows from the power source Vcc to the signal line side through the drive transistor Trd, the switching transistors Tr6 and Tr10. In other words, Isig flows through the drive transistor Trd as a drain current. At this time, since the switching transistors Tr4 and Tr5 are turned on, the pixel capacitor Cs1 is connected between the power supply Vcc and the other end of the pixel capacitor Cs2. Therefore, when the signal current Isig flowing through the signal line is passed through the drive transistor Trd, the signal voltage generated at the gate is held in the pixel capacitor Cs1. This signal voltage Vcs1 is given by the following expression 11 in exactly the same way as the above expression 7.

As is clear from Equation 11, the signal voltage Vcs1 held in the pixel capacitor Cs1 is proportional to the square root of the signal current Isig. Further, the effect of the threshold voltage Vth of the drive transistor Trd is canceled by Vth held in advance in the pixel capacitor Cs2. Therefore, the net signal voltage Vcs1 corresponding to the signal current Isig is sampled and held in the pixel capacitor Cs1 by the Isig writing operation in the period T4-T5.

FIG. 12 is a schematic diagram showing the Iref write operation performed in the period T5-T6 shown in FIG. When the process proceeds from the Isig write operation shown in FIG. 11 to the Iref write operation shown in FIG. 11, the control line WS2 goes low. As a result, the transistors Tr4 and Tr5 are turned off, so that the pixel capacitor Cs1 is disconnected from the circuit. On the other hand, as a result of the control signal WS2 ′ becoming high level, the pixel capacitor Cs1 ′ at the next stage is connected to the pixel circuit 2 at the corresponding stage via the pair of connection lines CL1 and CL2. Therefore, as apparent from a comparison between FIG. 11 and FIG. 12, the internal pixel capacitance Cs1 is switched to the external pixel capacitance Cs1 ′. More specifically, in the Isig write operation of FIG. 11, the pixel capacitors Cs1 and Cs2 are connected in series between the source / gate of the drive transistor Trd, whereas in the Iref write operation of FIG. 11, the drive transistor Trd. A pixel capacitor Cs1 ′ and a pixel capacitor Cs2 are connected in series between the source (power supply line Vcc) and the gate. That is, the internal pixel capacitance Cs1 is merely replaced with the external pixel capacitance Cs1 ′ as a circuit operation. At this time, Iref flows in the signal line instead of the previous Isig. More specifically, the reference current Iref flows from the power supply Vcc through the drive transistor Trd and further flows to the signal line side through the switching transistors Tr6 and Tr10. At this time, a part of the gate voltage Vgs generated between the source and the gate of the driving transistor Trd is held in the pixel capacitor Cs1 ′. Assuming that this voltage is the reference voltage Vcs1 ′, it is expressed as in the following Expression 12, in exactly the same way as in Expression 11.

  Here, as apparent from a comparison between Expression 11 and Expression 12, the left side of the expression is changed from Vcs1 to Vcs1 ′, while the right side of the expression is changed from Isig to Iref. As is apparent from Equation 12, the voltage Vcs1 ′ held in the pixel capacitor Cs1 ′ corresponds to the square root of the reference current Iref. In other words, in this Iref write operation, the reference voltage Vcs1 ′ corresponding to the reference current Iref is sampled in the external pixel capacitor Cs1 ′.

FIG. 13 is a schematic diagram illustrating the capacity canceling operation performed in the period T7 to T8 in the timing chart illustrated in FIG. In this operation, the switching transistors Tr7 and Tr8 are turned on, while the remaining switching transistors are all turned off. As a result, the negative terminal side of the internal pixel capacitor Cs1 and the positive terminal of the external pixel capacitor Cs1 ′ are connected via one connection line and the transistor Tr7, and the positive terminal of the internal pixel capacitor Cs1 and the external pixel capacitor Cs1 ′. The-side terminal is connected to the other connection line and the switching transistor Tr8. As a result, the capacitance cancellation of the pixel capacitors Cs1 and Cs′1 is performed between Vcs1 and Vcs1 ′. That is, a difference between the signal voltage Vcs1 held in the internal pixel capacitor Cs1 and the reference voltage Vcs1 ′ held in the external pixel capacitor Cs1 ′ is obtained, and this difference is held as both the control voltage Vcs1 ″ at both ends of the internal pixel capacitor Cs1. The Here, since the internal pixel capacitance Cs1 and the external pixel capacitance Cs1 ′ have the same capacitance, the control voltage Vcs1 ″ held in the pixel capacitance Cs1 after the capacitance cancellation is given by Equation 13 below.

  As is clear from the above equation 13, the control voltage Vcs1 ″ is a value corresponding to the difference between the signal current Isig and the reference current Iref. Precisely, a control voltage corresponding to the difference between the square root of Isig and the square root of Iref is held as Vcs1 ″ in the pixel capacitor Cs1.

  FIG. 14 is a schematic diagram showing capacitive coupling and light emission operation in a light emission period performed after timing T9 shown in FIG. When the timing T9 is reached, the control signals DS and WS2 become high level, while the other control signals are all at low level. Accordingly, the switching transistors Tr1, Tr4, Tr5 are turned on, while the remaining switching transistors are all turned off. Since the transistors Tr4 and Tr5 are turned on, the pixel capacitors Cs1 and Cs2 are coupled between the source (power supply line Vcc) and the gate of the drive transistor Trd. At this time, since the gate capacitance Cg of the drive transistor Trd is sufficiently small, the pixel capacitances Cs1 and Cs2 are coupled in a state in which the mutual charges are held. That is, the gate voltage Vgs of the drive transistor Trd during light emission is the sum of the control voltage Vcs1 ″ held in the pixel capacitor Cs1 and the threshold voltage Vth held in the pixel capacitor Cs2, and is given by Vgs = Vcs1 ″ + Vth.

上記数式１４の１段目で、ＶｇｓにＶｃｓ１´´＋Ｖｔｈを代入している。これによりＶｔｈがキャンセルされ、駆動電流ＩｄｓはＶｃｓ１´´の２乗に比例した形となる。さらに数式１４の２段目に示すようにＶｃｓ１´´に数式１３を代入する。このあと分母に現れる移動度μと係数部の移動度μがキャンセルされ、最終的に数式１４の３段目で表す形となる。この式から明らかなように、ＩｓｉｇとＩｒｅｆの電流差分値により駆動電流（発光電流）Ｉｄｓが決定され、駆動トランジスタのＶｔｈや移動度μのばらつきによらないユニフォーミティの高い画質を得る事ができる。さらに本発明の画素回路では黒表示時Ｉｓｉｇ＝Ｉｒｅｆに設定する。数式１４から明らかなように、Ｉｓｉｇ＝ＩｒｅｆにするとＩｄｓ＝０となり、発光電流はなくなる。この結果完全な黒表示となる。一方黒表示でもＩｒｅｆの絶対値は充分に高いレベルに設定する事ができ、１水平期間（１Ｈ）内で充分に黒信号を書き込むことができる。これにより、黒浮きや縦クロストークなどの発生を抑制でき、完全に沈んだ黒の色調を表現でき高いコントラストを得ることが可能である。なお、上記実施形態では、内部画素容量に信号電圧を書き込む一方外部画素容量に基準電圧を書き込んでいるが、本発明はこれに限られるものではなく逆にしても良い。また、上記実施形態では外部画素容量として次段の画素容量を利用しているが、本発明はこれに限られるものではなく別の段に属する画素回路の画素容量であれば良い。この様に、別の段の画素回路の画素容量を利用する事で、画素１個あたりに必要な容量素子の個数を削減する事ができる。 When the Vgs obtained in this way is put into the basic characteristic equation of the transistor shown in Equation 1, a drive current Ids as shown in Equation 14 below can be obtained.

In the first stage of Equation 14, Vcs1 ″ + Vth is substituted for Vgs. As a result, Vth is canceled and the drive current Ids takes a form proportional to the square of Vcs1 ″. Further, as shown in the second stage of Expression 14, Expression 13 is substituted into Vcs1 ″. Thereafter, the mobility μ appearing in the denominator and the mobility μ of the coefficient part are canceled, and finally the form expressed by the third stage of Equation 14 is obtained. As is apparent from this equation, the drive current (light emission current) Ids is determined by the current difference value between Isig and Iref, and high uniformity image quality can be obtained regardless of variations in Vth and mobility μ of the drive transistor. . Furthermore, in the pixel circuit of the present invention, Isig = Iref is set during black display. As is apparent from Equation 14, when Isig = Iref, Ids = 0 and the light emission current disappears. This results in a complete black display. On the other hand, even in black display, the absolute value of Iref can be set to a sufficiently high level, and a black signal can be sufficiently written within one horizontal period (1H). As a result, it is possible to suppress the occurrence of black floating and vertical crosstalk, and it is possible to express the color tone of the completely sinked black and to obtain a high contrast. In the above embodiment, the signal voltage is written to the internal pixel capacitor while the reference voltage is written to the external pixel capacitor. However, the present invention is not limited to this and may be reversed. In the above embodiment, the pixel capacitance of the next stage is used as the external pixel capacitance. However, the present invention is not limited to this, and any pixel capacitance of a pixel circuit belonging to another stage may be used. In this manner, by using the pixel capacitance of the pixel circuit in another stage, the number of capacitor elements required per pixel can be reduced.

  As described above, the pixel circuit according to the present invention is arranged at the intersection of the signal line SL through which the signal current Isig flows and the scanning lines WS1, WS2, WS3, AZ, DS that supply the control signal. . The pixel circuit 2 includes a light-emitting element EL, a drive transistor Trd that supplies a drive current Ids to the light-emitting element EL, and a pixel capacitor Cs1, and operates in response to control signals WS1, WS2, WS3, AZ, and DS. And a control unit that controls the drive current Ids of the drive transistor Trd based on Isig. The control unit includes first sampling means, second sampling means, and difference means. The first sampling means is composed of switching transistors Tr6, Tr5, Tr4, Tr9, Tr10. The signal current Isig flowing through the signal line SL is passed through the drive transistor Trd and the signal voltage Vcs1 generated at the gate at that time is supplied to the pixel circuit 2. Sampling is performed on one of the internal pixel capacitor Cs1 disposed inside or the external pixel capacitor Cs1 ′ disposed on a pixel circuit 2 ′ different from the pixel circuit 2. In the above-described embodiment, the sampled signal voltage Vcs1 is held in the internal pixel capacitor Cs1. The second sampling means is composed of switching transistors Tr6, Tr9, Tr10. A predetermined reference current Iref flowing in the signal line SL before and after the signal current Isig is passed through the drive transistor Trd, and a reference voltage Vcs1 ′ generated at the gate at that time. Is sampled to the other of the internal pixel capacitor Cs1 and the external pixel capacitor Cs ′. In the above-described embodiment, the reference voltage Vcs1 ′ is sampled by the external pixel capacitor Cs1 ′. In the above-described embodiment, sampling is performed in the order of Isig and Iref. However, the present invention is not limited to this, and sampling can be performed in the order of Iref and Isig. The difference means comprises transistors Tr7 and Tr8, and the internal pixel capacitors Cs1 and Cs1 ′ obtained by sampling the signal voltage Vcs1 and the reference voltage Vcs1 ′ are connected to each other to obtain a difference, and the obtained difference is set as a control voltage Vcs1 ″ as an internal pixel. The drive transistor Tr held in the capacitor Cs1 receives the control voltage Vcs1 ″ held in the internal pixel capacitor Cs1 at the gate, and supplies the drive current Ids flowing between the source and drain to the light emitting element EL to emit light. The control unit of the pixel circuit 2 further includes correction means including switching transistors Tr2 and Tr3, detects the threshold voltage Vth of the driving transistor Trd, holds this in the additional pixel capacitor Cs2, and holds the threshold voltage Vth is added to the control voltage Vcs1 ″ held in the internal pixel capacitor Cs1. Thereby, the influence of the threshold voltage Vth can be canceled from the drive current Ids.

It is a circuit diagram which shows the pixel circuit concerning a reference example. 2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 1. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. 1 is a circuit diagram showing an embodiment of a pixel circuit according to the present invention. 9 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 8. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a whole block diagram which shows an example of the conventional display apparatus. FIG. 16 is a circuit diagram illustrating a configuration of a pixel circuit included in the conventional display device illustrated in FIG. 15. It is a schematic diagram which shows an example of the screen of the conventional display apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel circuit, 3 ... Current driver, 4 ... Write scanner, 5 ... Drive scanner, 7 ... Correction scanner, Trd ... Drive transistor, Tr1 ... switching transistor, Tr2 ... switching transistor, Tr3 ... switching transistor, Tr4 ... switching transistor, Tr5 ... switching transistor, Tr6 ... switching transistor, Tr7 ... switching transistor, Tr8 ... Switching transistor, Tr9 ... Switching transistor, Tr10 ... Switching transistor, EL ... Light emitting element, Cs1 ... Pixel capacitance, Cs2 ... Pixel capacitance, Cs3 ... Pixel capacitance

Claims (10)

The signal line through which the signal current flows and the scanning line that supplies the control signal are arranged at the intersection,
A light-emitting element; a drive transistor that supplies a drive current to the light-emitting element; and a control unit that includes a pixel capacitor and operates in accordance with the control signal and controls the drive current of the drive transistor based on the signal current A pixel circuit,
The control unit passes a signal current flowing through the signal line through the drive transistor, and a signal voltage generated at the gate at that time is disposed in an internal pixel capacitor disposed in the pixel circuit or in a pixel circuit different from the pixel circuit. First sampling means for sampling to one of the external pixel capacitors;
A second sampling means for passing a predetermined reference current flowing in the signal line before and after the signal current through the driving transistor and sampling a reference voltage generated at the gate at that time to the other of the internal pixel capacitance or the external pixel capacitance;
A difference means for connecting the internal pixel capacity and the external pixel capacity obtained by sampling the signal voltage and the reference voltage to obtain a difference and holding the obtained difference in the internal pixel capacity as a control voltage;
The pixel circuit characterized in that the driving transistor receives the control voltage held in the internal pixel capacitor at a gate and supplies a driving current flowing between a source and a drain to the light emitting element to emit light.   The signal voltage and the reference voltage sampled by each of the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element decreases and when the difference is large, the light emission amount increases. 2. The pixel circuit according to claim 1, wherein the absolute levels of the signal current and the reference current are set so as to enable sampling even when the relative difference between them is small.   The control unit includes a correcting unit that detects a threshold voltage of the driving transistor, holds the threshold voltage in an additional pixel capacitor, and adds the held threshold voltage to the control voltage held in the internal pixel capacitor. The pixel circuit according to claim 1, wherein the influence of the threshold voltage is canceled from the drive current.   The pixel circuit according to claim 1, wherein the control unit uses an internal pixel capacitance and an external pixel capacitance having the same capacitance value. It consists of a pixel array part, a driver part, and a scanner part.
The pixel array section is composed of a column-shaped signal line, a row-shaped scanning line, and a matrix-shaped pixel circuit arranged at a portion where both intersect.
The driver section sends a signal current to each signal line,
The scanner unit supplies a control signal to each scanning line,
Each pixel circuit includes a light emitting element, a driving transistor that supplies a driving current to the light emitting element, and a pixel capacitor, and operates according to the control signal to control the driving current of the driving transistor based on the signal current. A display device comprising an in-pixel control unit,
The in-pixel control unit passes a signal current flowing through the signal line through the driving transistor, and a signal voltage generated at the gate at that time is an internal pixel capacitor disposed inside the pixel circuit or a pixel circuit different from the pixel circuit First sampling means for sampling to one of the external pixel capacitances arranged in
A second sampling means for passing a predetermined reference current flowing in the signal line before and after the signal current through the drive transistor and sampling a reference voltage generated at the gate to the other of the internal pixel capacitance or the external pixel capacitance;
A difference means for connecting the internal pixel capacity and the external pixel capacity obtained by sampling the signal voltage and the reference voltage to obtain a difference and holding the obtained difference in the internal pixel capacity as a control voltage;
The display device according to claim 1, wherein the driving transistor receives the control voltage held in the internal pixel capacitor at a gate and supplies a driving current flowing between the source and the drain to the light emitting element to emit light.   The signal voltage and the reference voltage sampled by each of the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element decreases and when the difference is large, the light emission amount increases. 6. The display device according to claim 5, wherein the absolute levels of the signal current and the reference current are set large so as to enable sampling even when the relative difference between them is small.   The in-pixel control unit detects a threshold voltage of the driving transistor, holds the threshold voltage in another pixel capacitor, and corrects the threshold voltage held in the internal pixel capacitor to the control voltage The display device according to claim 5, wherein the influence of the threshold voltage is canceled from the drive current.   The display device according to claim 5, wherein the intra-pixel control unit uses an internal pixel capacitance and an external pixel capacitance having the same capacitance value. A signal line through which a signal current flows and a scanning line that supplies a control signal are arranged at a crossing portion, and includes a light emitting element, a driving transistor that supplies a driving current to the light emitting element, a pixel capacitor, and according to the control signal A pixel circuit driving method comprising: a control unit that operates and controls a driving current of the driving transistor based on the signal current,
A signal current flowing through the signal line is passed through the driving transistor, and a signal voltage generated at the gate at that time is an internal pixel capacitor disposed in the pixel circuit or an external pixel capacitor disposed in a pixel circuit different from the pixel circuit. A first sampling procedure for sampling into one of
A second sampling procedure in which a predetermined reference current flowing through the signal line before and after the signal current is passed through the drive transistor and a reference voltage generated at the gate is then sampled on the other of the internal pixel capacitance or the external pixel capacitance;
A difference procedure for connecting the internal pixel capacity and the external pixel capacity obtained by sampling the signal voltage and the reference voltage to obtain a difference and holding the obtained difference in the internal pixel capacity as a control voltage;
A method for driving a pixel circuit, comprising: applying a control voltage to the gate of the driving transistor and supplying a driving current flowing between the source and drain to the light emitting element. The pixel array unit is composed of a pixel array unit, a driver unit, and a scanner unit, and the pixel array unit is composed of a column-shaped signal line, a row-shaped scanning line, and a matrix-shaped pixel circuit arranged at a portion where the two intersect. The driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, each pixel circuit includes a light emitting element, a driving transistor for supplying a driving current to the light emitting element, and a pixel A display device driving method for controlling a driving current of the driving transistor based on the signal current in response to the control signal,
A signal current flowing through the signal line is passed through the driving transistor, and a signal voltage generated at the gate at that time is an internal pixel capacitor disposed in the pixel circuit or an external pixel capacitor disposed in a pixel circuit different from the pixel circuit. A first sampling procedure for sampling into one of
A second sampling procedure in which a predetermined reference current flowing through the signal line before and after the signal current is passed through the drive transistor and a reference voltage generated at the gate is then sampled on the other of the internal pixel capacitance or the external pixel capacitance;
A difference procedure for connecting the internal pixel capacity and the external pixel capacity obtained by sampling the signal voltage and the reference voltage to obtain a difference and holding the obtained difference in the internal pixel capacity as a control voltage;
A driving method of a display device, comprising: applying a light emitting procedure for applying the control voltage to the gate of the driving transistor and supplying a driving current flowing between the source and the drain to the light emitting element.

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