JP2005157347A - Active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device which performs satisfactory display operation when supplying signals by current signals. <P>SOLUTION: The active matrix display device is provided with a plurality of pixels 100 arranged like a matrix on a substrate, each of which includes a display element 110 and a pixel circuit 120 for supplying a driving current to the display element, image signal lines Xm arranged along the pixels, and an image signal driver 300 for supplying a gradation current to the pixels through the image signal lines after supplying a base current to the image signal lines. Each pixel circuit includes a pixel switch SST for controlling selection/non-selection of a pixel and stores a difference current between the gradation current and the base current when selecting the pixel and outputs the stored difference current to the display element as the driving current when not selecting the pixel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix display device, and more particularly to an active matrix display device that performs signal writing using a current signal.

  The demand for flat display devices typified by liquid crystal display devices has rapidly increased for CRT displays by utilizing the features of thinness, light weight, and low power consumption. In particular, an active matrix display device in which a pixel switch having a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel is provided in each pixel has crosstalk between adjacent pixels. Since a good display quality without any problem can be obtained, it has come to be used for various displays including portable information devices.

  In recent years, organic electroluminescence (EL) display devices have been actively developed as self-luminous displays capable of high-speed response and wide viewing angle compared to liquid crystal display devices.

The organic EL display device includes an organic EL element as a display element for each pixel and a pixel circuit that supplies a drive current to the display element, and performs a display operation by controlling light emission luminance. For supplying image information to the pixel circuit, a method using a current signal (for example, Patent Document 1) and a method using a voltage signal (for example, Patent Document 2) are known.
US Pat. No. 6,373,454 B1 US Pat. No. 6,229,506 B1

  However, in the case of a display device that supplies a signal using the current signal as described above, there is a possibility that sufficient signal supply cannot be performed due to the wiring capacity of the wiring that supplies the signal. In particular, there is a problem that a display defect due to insufficient writing occurs when the current value to be written is small. In addition, when performing multi-gradation display, writing becomes difficult on the low gradation side where the set current amount is small, resulting in display problems.

  The present invention has been made to solve the above problems, and provides an active matrix display device capable of performing a good display operation even when a signal is supplied by a current signal.

An active matrix display device according to an aspect of the present invention includes a display element, a plurality of pixels arranged in a matrix on a substrate, and a pixel circuit that supplies a driving current to the display element. And a video signal driver that supplies a gradation current to the pixel through the video signal wiring after supplying a base current to the video signal wiring,
Each pixel circuit includes a pixel switch that controls selection and non-selection of the pixel, stores the difference current between the gradation current and the base current when the pixel is selected, and stores the difference current when the pixel is not selected The differential current is output to the display element as a drive current.

  According to the present invention, an active matrix display device capable of performing a good display operation can be realized.

  As a first embodiment of the present invention, an organic EL display device will be described as an example with reference to the drawings.

  FIG. 1 is a schematic plan view of the organic EL display device 1, and FIG. 2 is a schematic diagram for explaining the operation thereof.

As shown in FIG. 1, the organic EL display device 1 is configured, for example, as a large active matrix display device having a size of 10 or more, and is arranged in a matrix (M × N) on an insulating support substrate 10 such as glass. A plurality of pixels 100, a plurality of scanning wirings Y1n to Y2n (n = 1, 2, 3,..., N) and a plurality of output control wirings Y0n arranged along the row direction of the pixels 100; A plurality of video signal wirings Xm (m = 1, 2, 3,..., M), power supply voltage supply wirings Vdd1, Vdd2, and scanning wirings Y1n to Y2n arranged along the column direction of the pixels 100 are scanned. outputs a signal Ysig1n～Ysig2n, a scan driver 122 for outputting a control signal Ysig0n the output control lines Y0N, and outputs a base current _{I B} to the video signal lines Xm, and video to the video signal line Xm Includes a video signal driver 300 which outputs a gradation current I _C as No., and a plurality of base current storage unit 200 to be output to the video signal lines Xm corresponding storing the base current I _B supplied from the video signal driver 300 ing.

  As shown in FIG. 5, the base current storage unit 200 includes a first transistor DRT1 connected between the first voltage power supply Vdd1 and the video signal wiring Xm, and one electrode connected to the gate of the first transistor DRT1, A first capacitor Cs1 that maintains a constant potential difference between the gate and source of one transistor DRT1 and a first switch TCT1 connected between the gate and drain of the first transistor DRT1 are provided. The first capacitor Cs1 is connected between the gate and the source of the first transistor DRT1, but is not limited thereto. For example, the first transistor DRT1 and the first switch TCT1 are configured by p-type thin film transistors. The base current storage unit 200 is integrally and simultaneously formed on the support substrate 10 on which the pixels 100 are formed.

  As shown in FIGS. 1 and 5, each pixel 100 includes a display element 110 having a photoactive layer between opposing electrodes, and a pixel circuit 120 that supplies a drive current to drive the display element 110. Yes. The display element 110 is, for example, a self-light emitting element, and here is an organic EL element including at least an organic light emitting layer as a photoactive layer.

The pixel circuit 120 stores the difference current _I C -I _B of gradation current _{I C} and base current _{I B} when selecting the pixel 100, differential current _I C -I _B a driving current stored at the time of non-selection of the pixel 100 It is output to the display element 110 as _ID . The pixel circuit 120 includes a pixel switch SST that controls selection / non-selection of the pixel 100, a drive current storage unit 121 that stores a drive current, and output / non-output of drive current from the drive current storage unit 121 to the display element 110. Is provided with an output switch BCT.

First, as shown in FIG. 2 (a), in the base current supply period, and set to flow a predetermined base current I _B to the video signal line Xm through the first transistor DRT1 in the base current storage unit 200, the base the gate of the first transistor DRT1 corresponding to the current _{I B} - writing source potential to the first capacitor Cs1. At this time, the drive current storage unit 121 is electrically isolated from the video signal wiring.

The Here the base current I _B, the constant current source 131 is a current signal set to a predetermined value, one horizontal scanning period (t), from highest to lowest gradation display in the wiring capacitance of the video signal lines (Cp) A value larger than the amount of charge corresponding to the potential change (maximum voltage change ΔV) for gradation display is set (I _B > Cp × ΔV / t). For example, it is set to the same magnitude as the drive current for performing the highest gradation display. As an example, in the case of performing full color display, in the pixel 100 that emits red light, the drive current for performing the maximum gradation display is about 2 μA.

Next, as shown in FIG. 2 (b), the video signal write period, the gate of the first transistor DRT1 - at the time when the drain was disconnected, the gate of the first transistor DRT1 corresponding to the base current I _B - The potential between the sources is held in the first capacitor Cs1. Then, outputs the base current I _B stored in the base current storage unit 200 to the video signal lines Xm, by supplying a gradation current I _C corresponding to a video signal, a desired drive current to the drive current storage unit 121 I _D is supplied and the drive current _ID is stored.

Here, the gradation current I _C, the driving transistor DRT source pixel circuits 120 to be described later - a current signal set so that the amount of current flowing between the drain becomes the current amount of the desired magnitude, base current I _B and the drive current _ID to be supplied to the display element 110 are added to each other. That is, the source of the drive transistor DRT - the amount of current flowing between the drain is set by the difference current _I C -I _B between the gradation current _{I C} and base current _{I B.} In the following embodiments, secure the base current I _B, but illustrating the gradation current I _C as a variable current, it is also possible to vary both.

As shown in FIG. 2C, the drive current _ID stored in the drive current storage unit 121 is supplied to the display element 110 while the pixel 100 and the video signal wiring Xm are electrically disconnected in the display period. Thus, the display element 110 is operated.

For example, when performing a black display in the voltage change of 3V, the base current _{I B} 2.0μA, a gradation current _{I C} may be set as 2.0Myuei. Since a current of several μA or more flows through the wiring to the input terminal (input of the pixel switch SST) of each pixel 100, even if a capacitance of 10 pF is applied, charging is performed within 15 μs, and the video signal to the pixel circuit 120 Thus, a stable display operation can be performed without causing a shortage of the writing time.

  As described above, since the current writing corresponding to the input signal representing the video information input from the outside is performed using the differential current, the current value supplied to the video signal wiring can be freely set. For this reason, it can be set to a value sufficiently larger than the wiring capacity of the video signal wiring. By setting the base current and the gradation current sufficiently larger than the wiring capacity, it is sufficient in writing the video signal to the pixel. It is possible to supply a simple signal.

  In addition, when writing a video signal to a pixel, it is possible to write a small current, which is a difference current, with a large write current that is not affected by the wiring capacity, so that even a pixel with a small set current amount can be written without causing insufficient writing. Good writing can be performed. In particular, it is possible to eliminate the appearance of unevenness and a rough feeling on the low gradation side.

  In addition, it is possible to solve the shortage of writing of the low current video signal when the low current writing is performed after the high current writing to the video signal wiring. For example, conventionally, when writing a video signal with the highest gradation display (white display) and then writing with the lowest gradation display (black display), the latter lack of video signal writing causes the higher gradation display (white display) to be written. There is a possibility that the image is in a writing state and the white display has a tail on display. The present invention can also eliminate such display defects due to insufficient writing.

  In the present embodiment, the base current storage unit 200 is provided on the same substrate as the support substrate 10 on which the display element 110 is formed, and can be formed in the same process as the wiring and the thin film transistor that configure the pixel circuit 120. . Thus, by incorporating the base current storage unit 200 in the display device, the length of the wiring for supplying the current signal can be reduced, the capacitive load can be reduced, and a stable current signal can be supplied. Become. In addition, the number of connection points with an external circuit can be reduced, and mechanical reliability can be improved. Since the pixel circuit 120 and the base current storage unit 200 are formed on the same substrate in the same process, the pixel circuit 120 and the base current storage unit 200 can be configured using elements with similar characteristics, and the variation in drive current to the display element is reduced. can do.

  Each pixel 100 is configured as shown in FIG. 3, for example. In this case, the drive current storage unit 121 includes the drive transistor DRT connected in series with the display element 110 and the output switch BCT between the second voltage power supply Vdd2 and the third voltage power supply Vss, the drain of the drive transistor DRT, and the output switch BCT. Between the gate of the drive transistor DRT, the correction switch TCT connected between the gate of the drive transistor DRT and the drain of the drive transistor DRT via the write switch WRT, and the gate and source of the drive transistor DRT. And a storage capacitor Cs that keeps the potential difference constant. The gate of the drive transistor DRT is connected to the video signal line Xm via the correction switch TCT and the pixel switch SST, and the drain of the drive transistor DRT is connected to the video signal line Xm via the write switch WRT and the pixel switch SST. Such a configuration is called a current copy type.

  For example, each pixel 100 may be configured as shown in FIG. In this modification, the drive current storage unit 121 includes a transistor Tr arranged so as to have a relationship of a drive transistor DRT and a current mirror. When the video signal is written when the pixel 100 is selected, the drive transistor DRT is stored. In use, when the pixel 100 is not selected, a current substantially equal to the current written via the drive transistor DRT can be output to the display element 110 as a drive current via the transistor Tr. Such a configuration is called a current mirror type. In this case, the output switch BCT can be omitted.

  In the pixel 100 shown in FIGS. 3 and 4, the write switch WRT supplies the output of the base current from the base current storage unit 200 to the video signal driver 300 through the video signal wiring Xm without passing through the pixel 100. It can be omitted. In this case, the drain of the first transistor DRT1, the drain of the correction switch TCT, and the drain of the pixel switch SST are always connected.

  Thus, the present embodiment can be applied to various types of display devices 1 that write video signals to the pixels 100 using current signals.

  In this embodiment, all the thin film transistors constituting the pixel circuit 120 are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer. By constituting all the thin film transistors with the same conductivity type, an increase in the number of manufacturing steps can be suppressed.

  Hereinafter, the first embodiment will be described in more detail.

  As shown in FIGS. 1 and 5, the base current storage unit 200 is provided for each video signal wiring Xm. FIG. 5 shows a relationship between the plurality of pixels 100 connected to the m-th column video signal wiring Xm and the base current storage unit 200 as an example, and FIG. 6 shows a timing chart thereof.

  The first switch TCT1 of the base current storage unit 200 is connected to a common control line YBn, and on / off control of the switch is performed based on the control signal YsigBn.

  The pixel switch SST and the correction switch TCT in each pixel 100 are connected to the common first scanning wiring Y1n and second scanning wiring Y2n for each row of the pixels 100, and are integrally formed on the support substrate 10 with the scanning driver 122. ON / OFF control is performed based on the scanning signals Ysig1n and Ysig2n supplied from. The output switch BCT is connected to the same output control wiring Y0n for each row of the pixels 100, and is turned on / off based on the control signal Ysig0n supplied from the scan driver 122.

  The scan driver 122 includes a shift register and an output buffer, sequentially transfers a horizontal scan start pulse supplied from the outside to the next stage, and outputs the output of each stage to the first scan line Y1n via the output buffer. Supplied as Ysig1n. This timing is synchronized with one horizontal scanning period. Further, the output of each stage is signal-processed to generate an output control signal Ysig0n or a scanning signal Ysig2n, which is supplied to the corresponding output control wiring Y0n and scanning wiring Y2n. The control signal YsigBn is generated based on the output (or input) signal of the shift register of the scan driver 122.

The drain of the driving transistor DRT is connected to the video signal wiring Xm commonly wired for each column of the pixels 100 via the pixel switch SST, and is connected to the video signal driver 300 which is a driving circuit via these video signal wirings. Is done. Base current I _B and the gradation current I _c is set by the video signal driver 300 by time division, it is supplied with the same video signal line Xm. The base current storage unit 200, for each timing of rewriting the video signal for one screen, that is, the writing of the base current I _B from the video signal driver 300 is performed every vertical period, stored data is refreshed. In the case where the pixel switch SST and the correction switch TCT are composed of thin film transistors of the same conductivity type, the scanning wiring can be shared.

  Next, an organic EL display device 1 according to a second embodiment of the invention will be described. As shown in FIGS. 7 and 8, the base current storage unit 200 is provided corresponding to each video signal wiring Xm, and is connected between the drain of the first transistor DRT1 and the video signal wiring. Thus, the input / output of the base current is controlled.

  8 schematically shows a relationship between a certain pixel 100 in the organic EL display device and a base current storage unit 200 provided corresponding to the video signal wiring Xm, FIG. 9 shows an equivalent circuit thereof, and FIG. (A) to 10 (c) show the operation of the pixel and base current storage unit 200. FIG. 11 shows a timing chart. In order from the top, the current / voltage switch switching state in the driver (constant current output at SI, constant voltage output at SV), signal state of the video signal wiring in the m-th column , The control signal of the base current switch SW, the control signal YsigB of the first switch TCT1, the scanning signal of each part of the pixel 100 in the (n−1) th row and the mth column, and each part of the pixel 100 in the nth row and the mth column. The scanning signals are respectively shown. Here, the same wiring is used as the scanning wiring for controlling the pixel switch SST and the correction switch TCT.

  The video signal driver 300 includes a constant voltage source 132 that outputs a predetermined potential of about halftone writing, for example, a potential of 3 V as the precharge voltage Vp, in addition to the constant current source 131 that outputs a gradation signal. As shown in FIG. 10 (a), after writing the base current from the constant low current source 131 to the base current storage unit 200, as shown in FIG. 10 (b1), the SW of the base current storage unit 200 is turned off. A precharge voltage Vp is precharged from the constant voltage source 132 to the drive current storage unit 121. Subsequently, as shown in FIG. 10B2, after the written base current is supplied to the drive current storage unit 121 and the drive current is written in the drive current storage unit, as shown in FIG. The display element 110 is driven to emit light by the driving current. In this way, the video signal writing period is time-divided, and the driving transistor DRT of the driving current storage unit 121 can be set in a good operating state in advance for each row writing.

  As shown in FIG. 12, according to the organic EL display device 1 according to the third embodiment of the present invention, the base current storage unit 200 is provided one more than the number of video signal lines, and is a predetermined period, for example, 1 vertical. It is also possible to operate the pixel 100 using the output from the base current storage unit 200 that is different for each period. In this case, as shown in FIG. 13, a pair of thin film transistors having different conductivity types, that is, a set of an n-type thin film transistor n-Tr and a p-type thin film transistor p-Tr is arranged for each video signal wiring Xm, and is different for each thin film transistor. A base current storage unit 200 is connected.

  In this way, by switching and connecting the plurality of base current storage units 200 to the video signal wiring Xm, it is possible to average the output variation of the base current and to improve the display operation. Can do.

  As shown in FIG. 14, the organic EL display device 1 according to the fourth embodiment of the present invention further includes a second base current switch SW2 provided corresponding to each pixel 100, and corresponding base current storage. The output of the unit 200 is configured to be supplied to the video signal wiring Xm via the pixel switch SST. The second base current switch SW2 is connected between the base current storage unit 200 and the drive current storage unit 121. For example, the second base current switch SW <b> 2 is configured by a p-type thin film transistor similarly to the pixel circuit 120, the source is the drain of the first transistor DRT <b> 1 of the base current storage unit 200, and the drain is the drive transistor DRT of the drive current storage unit 121. Connected to the drain.

  As described above, by outputting the base current via the pixel switch SST and the second base current switch SW2 via the wiring different from the video signal wiring Xm, a stable base current can be output, which is favorable. Display operation can be realized. In this case, it is desirable that the switching timing of the output control signals Ysig0n and Ysig0 (n + 1) for scanning between adjacent output control wirings is very short (almost simultaneously). When there is a period from turning off the previous row to turning on the next row, the base current storage unit and the wiring are not electrically connected to the output terminal of the base current storage unit 200 during the period. It is desirable to provide a switch that

  The second base current switch SW2 is controlled by the same signal as the control of the pixel switch SST, that is, the gate of the second base current switch SW2 is connected to the same scanning wiring as the gate of the pixel switch SST. An increase in the number of wirings can be suppressed.

  As shown in FIG. 15, according to the organic EL display device 1 according to the fifth embodiment of the present invention, the base current storage unit 200 is provided for each pixel 100. In the base current storage unit 200, the drain of the first transistor DRT1 is connected to the video signal line Xm via the pixel switch SST of the pixel circuit 120. The base current and the gradation current are set by the video signal driver 300, and are supplied to the plurality of base current storage units 200 using the same video signal wiring Xm by time division.

  FIG. 16 shows one pixel 100 in the fifth embodiment, FIG. 17 shows an equivalent circuit thereof, and FIG. 18 shows a timing chart of each part. The base current storage unit 200 writes the base current at each timing of rewriting each pixel 100, that is, every horizontal period, and performs a storage operation for each base current storage unit 200. In each base current storage unit 200, the stored contents are refreshed every vertical period. In FIG. 17, Y3n (n = 1, 2, 3,..., N) represents a third scanning wiring, and supplies the scanning signal Ysig3 to the writing switch WRT.

  In this way, by disposing the base current storage unit 200 in each pixel 100, display unevenness in the display surface, particularly in units of video signal wiring, can be reduced. At the same time, the responsiveness can be improved and the writing period can be shortened.

  As shown in FIG. 19, according to the organic EL display device 1 according to the sixth embodiment of the present invention, the base current storage unit 200, the drive current storage unit 121, and the video signal writing circuit 310 are provided for each pixel 100. ing. FIG. 19 shows a relationship among a plurality of pixels 100 connected to the m-th column video signal wiring Xm, the base current storage unit 200, the drive current storage unit 121, and the video signal writing circuit 310 as an example. The video signal driver 300 is connected to each video signal line Xm and functions as a first current supply unit, and a variable source that is connected to the video signal line via a switch S9 and functions as a second current supply unit. An IC 322 is provided. The constant current circuit 320 is built on the support substrate 10, and the source IC 322 is disposed outside the support substrate 10.

  Each pixel 100 includes a display element 110 having a photoactive layer between opposing electrodes, and a pixel circuit 120 that supplies a drive current to drive the display element 110. The display element 110 is, for example, a self-light emitting element, and here is an organic EL element including at least an organic light emitting layer as a photoactive layer.

  The pixel circuit 120 including the drive current storage circuit 121 is connected in series with the display element 110 and the output switch S8 (BCT) between the second voltage power supply Vdd2 (for example, 5V) and the third voltage power supply Vss (for example, −5V). The drive transistor DRT, the write switch S4 (WRT) connected between the drain of the drive transistor DRT and the output switch S8 (BCT), and the gate of the drive transistor DRT and the write switch S4 (WRT) are driven. A correction switch S3 (TCT) connected between the drain of the transistor DRT and a storage capacitor Cs that holds the potential difference between the gate and the source of the driving transistor DRT constant are provided. The gate of the drive transistor DRT is passed through the correction switch S3 (TCT) and the pixel switch S7 (SST), and the drain of the drive transistor DRT is passed through the write switch S4 (WRT) and the pixel switch S7 (SST). Xm is connected. For example, the drive transistor DRT, the correction switch S3 (TCT), and the write switch S4 (WRT) are configured by p-type thin film transistors.

The base current storage unit 200 includes a first transistor DRT1 connected between a first voltage power supply Vdd1 (for example, 0V) and a video signal wiring Xm via a second switch S2 and a pixel switch S7 (SST), and one electrode Is connected to the gate of the first transistor DRT1, and the second switch S2 is connected between the first capacitor Cs1 that keeps the potential difference between the gate and source of the first transistor DRT1 constant and the gate and drain of the first transistor DRT1. And a first switch S1 (TCT1) connected to each other. For example, the first transistor DRT1 is an n-type thin film transistor, and the first switch and the second switches S1 and S2 are p-type thin film transistors. The base current storage unit 200 is integrally and simultaneously formed on the support substrate 10 on which the pixels 100 are formed. Base current I _B to be described later is set at a constant current circuit 320 of the video signal driver 300 are supplied to the plurality of pixels 100 using the same video signal line Xm by time division.

The video signal writing circuit 310 includes a second transistor DRT2 connected between the fourth voltage power supply Vdd4 (for example, 10V) and the video signal wiring Xm via a fourth switch S6 and a pixel switch S7 (SST), and one electrode. Is connected to the gate of the second transistor DRT2, the second capacitor Cs2 that keeps the potential difference between the gate and source of the second transistor DRT2 constant, and the gate and the drain via the fourth switch S6 of the second transistor DRT2. And a third switch S5 connected therebetween. For example, the second transistor DRT2 and the third to fourth switches S5 and S6 are p-type thin film transistors. The video signal writing circuit 310 is integrally and simultaneously formed on the support substrate 10 on which the pixels 100 are formed. Gradation current I _C to be described later, is set in the source IC322 video signal driver 300 are supplied to the plurality of pixels 100 using the same video signal line Xm by time division.
The switches S1 to S8 are each connected to the scanning signal driver 122 via the gate wiring, and are controlled to open and close based on a control signal from the scanning signal driver.

  Next, a writing operation and a display operation in the pixel 100 of the organic EL display device 1 configured as described above will be described. FIG. 20 shows the switching timing of each switch in the pixel 100. 21 to 23 show the base current write operation, video signal current write operation, drive current write operation, and display operation of each pixel, respectively.

First, as shown in FIGS. 20 and 21, in the base current write period, the switches S1 and S2, the pixel switch S7, and the switch 10 of the base current storage circuit 200 are turned on and the other switches are turned off. Thus, through the first transistor DRT1 of video signal lines Xm and the base current storage unit 200, the constant current circuit 320 to a first voltage power supply Vdd1 flowing a predetermined base current _{I B,} corresponding to the base current _{I B} The gate-source potential of the first transistor DRT1 is written to the first capacitor Cs1. At this time, the pixel circuit 120 and the video signal writing circuit 310 are electrically separated from the video signal wiring Xm.

Next, as shown in FIGS. 20 and 22, in the video signal current writing period, the switches S5 and S6, the pixel switch S7, and the switch 9 of the video signal writing circuit 310 are turned on and the other switches are turned off. The gate of the first transistor DRT1 - when the drain was disconnected, the gate of the first transistor DRT1 corresponding to the base current I _B - holds the source potential to the first capacitor Cs1. Then, the source IC322, from the fourth voltage source VDD4 (10V) through a second transistor DRT2 and the video signal line Xm of the image signal writing circuit 310 passes a gradation current _{I C} corresponding to a video signal, the gradation the gate of the second transistor DRT2 corresponding to the current _{I C} - writing source potential to the second capacitor Cs2. At this time, the pixel circuit 120 and the driving current storage unit 121 are electrically separated from the video signal wiring Xm.

Subsequently, as shown in FIGS. 20 and 23, in the drive signal writing period, the switch S2 of the base current storage circuit 200, the switches S3 and S4 of the pixel circuit 120, and the switch S6 of the video signal writing circuit 310 are turned on. Set the switch to OFF. Once the drain was disconnected, the gate of the second transistor DRT2 corresponding to the gradation current I _C - - the gate of the second transistor DRT2 holds the source potential to the second capacitor Cs2.

Then, in a state of electrically disconnecting the pixel 100 and the video signal line Xm, the base current I _B and the image signal writing circuit first voltage gradation current I _C stored in the power supply Vdd1 stored in the base current storage unit 200 by outputting the (0V), the gradation current _{I C} and base current _{I B} and the differential current _(I B -I _C) a is the drive current _{I D} drive transistor DRT of the gate in response to - the capacitor-source potential Write to Cs.

As shown in FIGS. 20 and 24, in the display period, the switch S4 and the output switch S8 of the pixel circuit 120 are turned on and the other switches are turned off. Accordingly, the drive current _ID stored in the drive current storage unit 121 is supplied to the display element 110 in a state where the pixel 100 and the video signal wiring Xm are electrically disconnected, and the display element 110 is operated.

  In the present embodiment, the base current storage unit 200 and the video signal write circuit 310 perform the base current write and the video signal write at every timing of rewriting each pixel 100, that is, in one horizontal cycle. 200 and the video signal writing circuit 310 are stored. Each base current storage unit 200 may refresh the stored contents every vertical period. Alternatively, the base current writing and the video signal current writing may be performed in one horizontal cycle, and the driving signal current writing may be performed in the next one horizontal cycle.

In the embodiment described above, secure the base current I _B, described gradation current I _C as a variable current, but it is also possible to vary both.

  According to the sixth embodiment configured as described above, the current value to be supplied to the video signal wiring is changed because the differential current is used in the current writing corresponding to the input signal representing the video information input from the outside. It can be set freely. For this reason, it can be set to a value sufficiently larger than the wiring capacity of the video signal wiring. By setting the base current and the gradation current sufficiently larger than the wiring capacity, it is sufficient in writing the video signal to the pixel. It is possible to supply a simple signal.

  Then, by providing the base current storage unit 200, the video signal writing circuit 310, and the drive current storage unit 121 in each pixel 100, the video signal wiring having a large capacitive load (Csig) with the pixel 100 in writing the video signal to the pixel. The video signal can be written to the video signal writing circuit 310 in a state where Xm is electrically disconnected. Accordingly, when the video signal is written, the driving load is greatly reduced, and good writing can be performed even for a pixel having a small set current amount without causing insufficient writing even in low gradation display. As a result, it is possible to eliminate the visibility of the unevenness and the rough feeling on the low gradation side. Such an effect is particularly effective in a large display device.

  Further, by disposing the base current storage unit 200, the video signal writing circuit 310, and the drive current storage unit 121 in each pixel 100, display unevenness within the display surface, particularly in units of video signal wirings, can be reduced. At the same time, it is possible to improve responsiveness and shorten the writing period.

  In the sixth embodiment described above, the n-type thin film transistor is used as the first transistor DRT1 of the base current storage unit 200, but a p-type thin film transistor may be used. According to the seventh embodiment shown in FIG. 25, the base current storage unit 200 is connected to the first voltage power supply Vdd1 (for example, 0V) and the video signal wiring Xm via the switch S2 and the pixel switch S7. The first transistor DRT1 is composed of a p-type thin film transistor. The drain of the first transistor DRT1 is connected to the first voltage power supply Vdd1.

The base current storage unit 200 has one electrode connected to the source of the first transistor DRT1, the first capacitor Cs1 holding a potential difference between the gate and the source of the first transistor DRT1, and the first transistor DRT1. A switch S1 connected between the gate and the drain; The switches S1 and S2 are composed of p-type thin film transistors. The base current storage unit 200 is integrally and simultaneously formed on the support substrate 10 on which the pixels 100 are formed. Base current I _B and the gradation current Ic will be described later is set in the variable of the source IC322, is supplied to a plurality of pixels 100 using the same video signal line Xm by time division. As described in the sixth embodiment, it is possible to incorporate a constant current circuit on the support substrate and switch to the source IC by the switches S9 and S10.

  In the seventh embodiment, the configurations of the pixel circuit 120 and the video signal writing circuit 310 are the same as those of the sixth embodiment, and the same parts are denoted by the same reference numerals and detailed description thereof is omitted.

As shown in FIG. 26, in the base current writing period, the switches S1 and S2 and the pixel switch S7 of the base current storage circuit 200 are turned on and the other switches are turned off. Thus, through the first transistor DRT1 of video signal lines Xm and the base current storage unit 200, to the first voltage power supply Vdd1 from a source IC flowing a predetermined base current _{I B,} the first corresponding to the base current _{I B} A potential between the gate and the source of the transistor DRT1, for example, −5V is written to the first capacitor Cs1. At this time, the pixel circuit 120 and the video signal writing circuit 310 are electrically separated from the video signal wiring Xm.

Next, as shown in FIG. 27, in the video signal current writing period, the switches S5 and S6 and the pixel switch S7 of the video signal writing circuit 310 are turned on and the other switches are turned off. The gate of the first transistor DRT1 - drain and source - at the time when the non-connection between the video signal lines Xm, a gate of the first transistor DRT1 corresponding to the base current I _B - source potential (e.g., -5V) to the 1 capacitor Cs1 holds. Then, from the fourth voltage source VDD4 (10V) through a second transistor DRT2 and the video signal line Xm of the image signal writing circuit 310 passes a gradation current _{I C} corresponding to a video signal to the source IC322, the gradation current The potential between the gate and the source of the second transistor DRT2 corresponding to I _C is written to the second capacitor Cs2. At this time, the pixel circuit 120 and the driving current storage unit 121 are electrically separated from the video signal wiring Xm.

Hereinafter, as in the sixth embodiment, in the drive signal writing period, the switch S2 of the base current storage circuit 200, the switches S3 and S4 of the pixel circuit 120, and the switch S6 of the video signal writing circuit 310 are turned on, and other switches. To OFF. Once the drain was disconnected, the gate of the second transistor DRT2 corresponding to the gradation current I _C - - the gate of the second transistor DRT2 holds the source potential to the second capacitor Cs2.

Then, in a state of electrically disconnecting the pixel 100 and the video signal line Xm, the base current I _B and the image signal writing circuit first voltage gradation current I _C stored in the power supply Vdd1 stored in the base current storage unit 200 Output to (0V). Thus, the gate of the drive transistor DRT corresponding to the drive current _{I D} is a difference _(I B -I _C) between the gradation current _{I C} and base current _{I B} - writing source potential to the capacitor Cs.

In the display period, the switch S4 and the output switch S8 of the pixel circuit 120 are turned on and the other switches are turned off. Accordingly, the drive current _ID stored in the drive current storage unit 121 is supplied to the display element 110 in a state where the pixel 100 and the video signal wiring Xm are electrically disconnected, and the display element 110 is operated.

  According to the seventh embodiment configured as described above, it is possible to obtain the same operational effects as those of the sixth embodiment described above. Further, according to the seventh embodiment, the first transistor DRT1 of the base current storage unit 200 is configured by a p-type thin film transistor, whereby the driving transistor DRT of the pixel circuit 120 configured by the p-type thin film transistor and the video signal writing are each configured. The second transistor DRT2 of the circuit 310 and the switches S to S8 can be formed by the same manufacturing process. Therefore, the formation process of the n-type thin film transistor can be omitted, and the manufacturing cost can be reduced.

The fixed base current I _B, when the gradation current I _C and the variable current can be suppressed variation of the first capacitor Cs1, compared with the case where both variable, more desirable. In the second to seventh embodiments, other configurations are the same as those of the first embodiment described above, and the same reference numerals are given to the same portions, and the detailed description thereof is omitted.
The present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

FIG. 1 is a schematic plan view showing an organic EL display device according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the organic EL display device. FIG. 3 is a schematic view showing a pixel of the organic EL display device. FIG. 4 is a schematic view showing a modification of the pixel in the organic EL display device. FIG. 5 is a schematic diagram showing a row of pixel circuits and a base current storage unit of the organic EL display device. FIG. 6 is a timing chart of each part of the organic EL display device. FIG. 7 is a schematic plan view of an organic EL display device according to the second embodiment of the present invention. FIG. 8 is a schematic view showing a part of the organic EL display device according to the second embodiment. FIG. 9 is a partial equivalent circuit of the organic EL display device according to the second embodiment. FIG. 10 is a diagram for explaining the operation of the organic EL display device according to the second embodiment. FIG. 11 is a timing chart of each part of the organic EL display device according to the second embodiment. FIG. 12 is a schematic view showing a part of an organic EL display device according to the third embodiment of the present invention. FIG. 13 is a schematic view showing a part of an organic EL display device according to the third embodiment of the present invention. FIG. 14 is a schematic plan view showing an organic EL display device showing a fourth embodiment of the present invention. FIG. 15 is a schematic plan view showing an organic EL display device according to the fifth embodiment of the present invention. FIG. 16 is a schematic diagram illustrating a pixel circuit and a base current storage unit of the organic EL display device according to the fifth embodiment. FIG. 17 is an equivalent circuit in the vicinity of the pixel circuit and the base current storage section of the organic EL display device according to the fifth embodiment. FIG. 18 is a timing chart of each part of the organic EL display device according to the fifth embodiment. FIG. 19 is a schematic plan view showing a pixel of an organic EL display device according to the sixth embodiment of the present invention. FIG. 20 is a timing chart of each part of the organic EL display device according to the sixth embodiment. FIG. 21 is a schematic diagram showing a base current write operation in the organic EL display device according to the sixth embodiment. FIG. 22 is a schematic diagram showing a video signal writing operation in the organic EL display device according to the sixth embodiment. FIG. 23 is a schematic diagram showing a drive current write operation in the organic EL display device according to the sixth embodiment. FIG. 24 is a schematic view showing a display operation in the organic EL display device according to the sixth embodiment. FIG. 25 is a schematic plan view showing a pixel of the organic EL display device according to the seventh embodiment of the present invention. FIG. 26 is a schematic diagram showing a base current write operation in the organic EL display device according to the seventh embodiment. FIG. 27 is a schematic diagram showing a video signal writing operation in the organic EL display device according to the seventh embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Organic EL display device, 2 ... Support substrate, 100 ... Pixel,
110 ... Display element 120 ... Pixel circuit 121 ... Drive current storage unit
130: Video signal driver 200: Base current storage unit,
300 ... Video signal driver, 310 ... Video signal writing circuit,
320: constant current circuit, 322: source IC

Claims (16)

A plurality of pixels including a display element and a pixel circuit that supplies a driving current to the display element, the pixels being arranged in a matrix on the substrate;
Video signal wiring arranged along the pixels;
A video signal driver that supplies a gradation current to the pixel through the video signal wiring after supplying a base current to the video signal wiring; and
Each pixel circuit includes a pixel switch that controls selection and non-selection of the pixel, stores the difference current between the gradation current and the base current when the pixel is selected, and stores the difference current when the pixel is not selected An active matrix display device that outputs a differential current as a drive current to the display element.   2. The base current is set to a value larger than a charge amount corresponding to a potential change amount in which a wiring capacity of the video signal wiring performs a maximum gradation display to a minimum gradation display in one horizontal scanning period. The active matrix display device described.   The active matrix display device according to claim 1, wherein the video signal driver is formed on the substrate.   4. The active matrix display device according to claim 1, wherein the display element is a self-light-emitting element having an organic light-emitting layer between opposed electrodes.   The active matrix display device according to claim 1, further comprising a scan driver that outputs a control signal for performing on / off control of the pixel switch, wherein the scan driver is formed on the substrate.   2. The active matrix display device according to claim 1, wherein the pixel circuit includes a thin film transistor using a semiconductor layer formed of polysilicon. A plurality of pixels including a display element and a pixel circuit that supplies a driving current to the display element, the pixels being arranged in a matrix on the substrate;
Video signal wiring arranged along the pixels;
A video signal driver that supplies a base current to the video signal wiring and supplies a grayscale current to the pixel via the video signal wiring;
A base current storage unit that stores a base current supplied from the video signal driver and outputs the base current to the video signal wiring;
Each pixel circuit includes a pixel switch that controls selection and non-selection of the pixel, stores the difference current between the gradation current and the base current when the pixel is selected, and stores the difference current when the pixel is not selected An active matrix display device that outputs a differential current as a drive current to the display element.   The active matrix display device according to claim 7, wherein the base current storage unit is provided for each pixel.   The active matrix display device according to claim 7, wherein the base current storage unit is provided for each video signal wiring.   The active matrix display device according to claim 7, wherein the base current storage unit is connected in common to the video signal lines and is connected to different video signal lines every predetermined period. A plurality of pixels including a display element and a pixel circuit that supplies a driving current to the display element, the pixels being arranged in a matrix on the substrate;
A plurality of video signal lines arranged along the pixels;
A video signal driver for supplying a base current and a gradation current to the pixel via the video signal wiring,
Each of the pixels includes a base current storage unit that stores a base current supplied from the video signal driver, and a video signal writing circuit that stores a gradation current supplied from the video signal driver.
Each of the pixel circuits includes a pixel switch that controls selection and non-selection of the pixel, and stores the base current and the gradation current in the base current storage unit and the video signal writing circuit when the pixel is selected. And an active matrix display device that outputs a difference current between the base current and the gradation current stored when the pixel is not selected to the display element as a drive current.   The video signal driver includes a first current supply unit that supplies the base current and a second current supply unit that supplies the gray-scale current, and the first current supply unit is integrally formed on the substrate. The active matrix display device according to claim 11 formed.   The active matrix type of claim 12, wherein the first current supply unit includes a constant current circuit that supplies a predetermined base current, and the second current supply unit includes a source IC that supplies a variable gray-scale current. Display device.   14. The active matrix display device according to claim 12, wherein the first current supply unit and the second current supply unit are provided corresponding to each video signal wiring. The pixel circuit includes a driving transistor configured by a p-type thin film transistor connected in series with the display element and an output switch between a constant voltage power source, and a storage capacitor for holding a potential difference between a gate and a source of the driving transistor constant. The drain of the driving transistor is connected to the video signal wiring through the pixel switch,
The base current storage unit has a source connected to a constant voltage power source and a drain connected to the video signal line through the pixel switch, and includes a first transistor formed of an n-type thin film transistor, and the first transistor A first capacitor for maintaining a constant potential difference between a gate and a source of the transistor,
The video signal writing circuit includes a second transistor configured by a p-type thin film transistor having a source connected to a constant voltage power source and a drain connected to the video signal wiring through the pixel switch, and the second transistor The active matrix display device according to claim 11, further comprising a second capacitor that maintains a constant potential difference between the gate and the source. The pixel circuit includes a driving transistor configured by a p-type thin film transistor connected in series with the display element and an output switch between a constant voltage power source, and a storage capacitor for holding a potential difference between a gate and a source of the driving transistor constant. The drain of the driving transistor is connected to the video signal wiring through the pixel switch,
The base current storage unit has a drain connected to a constant voltage power source and a source connected to the video signal line through the pixel switch, and includes a first transistor formed of a p-type thin film transistor, and the first transistor A first capacitor that maintains a constant potential difference between the gate and source of the transistor, and a switch that is provided between the gate and drain of the first transistor and that is on / off controlled;
The video signal writing circuit includes a second transistor configured by a p-type thin film transistor having a source connected to a constant voltage power source and a drain connected to the video signal wiring through the pixel switch, and the second transistor The active matrix display device according to claim 11, further comprising a second capacitor that maintains a constant potential difference between the gate and the source.

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