JP2006208746A - Pixel circuit and display device, and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit capable of sufficiently writing even a fine signal current of black level, and a display device and a driving method thereof. <P>SOLUTION: The pixel circuit 2 includes transistors Tr6 and Tr7 and a couple of pixel capacitors Cs1 and Cs2, and the 1st capacitor wherein a signal voltage Vcs2 is sampled and the 2nd capacitor Cs1 where a reference voltage Vcs1 is sampled are connected to each other to obtain a difference Vcs2', which is held as a control voltage in the 2nd capacitor Cs2. A driving transistor Trd receives the control voltage Vcs2' held in the 2nd capacitor Cs2 at its gate G and supplies a driving current Ids flowing between its source S and drain D to a light emitting element EL, which is made to emit light. When the signal voltage and reference voltage have a small relative difference, the light emission quantity of the light emitting element becomes small and absolute levels of the signal current and reference current are set large enough to enable sampling. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit that drives a light emitting element arranged for each pixel in a current and a driving method thereof. In addition, the pixel circuit is a display device in which the pixel circuits are arranged in a matrix (matrix), and the amount of current supplied to a light emitting element such as an organic EL is controlled by an insulated gate field effect transistor provided in each pixel circuit. The present invention relates to a so-called active matrix display device and a driving method thereof.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, the current flowing through the light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  FIG. 15 is a schematic block diagram showing a conventional active matrix organic EL display. As shown in the figure, this display device is composed of a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit section includes a current driver 3, a write scanner 4, a drive scanner 5, a correction scanner 7, and the like. The pixel array 1 includes row-like scanning lines WS and column-like signal lines SL, and pixels R, G, and B arranged in a matrix at the intersection of the two. In order to enable color display, RGB three primary color pixels are prepared, but monochrome display monochrome pixels may be used instead. Each pixel R, G, B is composed of a pixel circuit 2. The signal line SL is driven by a current driver 3 so that a signal current flows. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS and AZ are also wired in parallel with the scanning line WS. The scanning line DS is scanned by the drive scanner 5. The drive scanner 5 controls the light emission period of the light emitting elements included in each pixel. The scanning line AZ is scanned by the correction scanner 7. The light scanner 4, the drive scanner 5, and the correction scanner 7 constitute a scanner unit as a whole, and sequentially scan the pixel rows every horizontal period.

  FIG. 16 is a circuit diagram showing a configuration example of the pixel circuit shown in FIG. As shown in the drawing, the pixel circuit 2 is composed of four transistors Tr1, Tr4, Tr5, Trd, one pixel capacitor Cs, and one light emitting element EL. All of the four transistors are thin film transistors. Among these, the transistors Tr1, Tr4 and Tr5 are control switching transistors, and all of them are N-channel type. On the other hand, the transistor Trd is a driving transistor for driving the light emitting element EL, and uses a P-channel type. The light-emitting element EL is a two-terminal self-light-emitting element having an anode and a cathode. For example, an organic EL element can be used.

  The source S of the drive transistor Trd is connected to the power supply Vcc. The drain D is located on the anode side of the light emitting element EL. The cathode side of the light emitting element EL is grounded. The gate G of the drive transistor Trd is connected to one end of the pixel capacitor Cs. The other end of the pixel capacitor Cs is connected to the power supply Vcc.

  The source / drain of the switching transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Trd. The gate of the switching transistor Tr1 is connected to the scanning line WS. The source / drain of the switching transistor Tr4 is connected between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr4 is connected to the scanning line AZ. The source / drain of the switching transistor Tr5 is connected between the drain D of the driving transistor Trd and the anode of the light emitting element EL. The gate of this transistor Tr5 is connected to the scanning line DS.

The drive transistor Trd operates in the saturation region, and its characteristics are expressed by the following Equation 1.

  In Equation 1, Vgs is a gate voltage and represents a voltage between the source S and the gate G of the drive transistor Trd. Ids is a drain current, which flows between the source S and the drain D of the driving transistor Trd and is supplied to the light emitting element EL. Vth represents the threshold voltage of the drive transistor Trd. μ similarly represents the carrier mobility of the drive transistor Trd. K is a constant and is given by Cox · W / L. Here, Cox is the gate capacitance of the drive transistor Trd, W is the channel width, and L is the channel length. The constant k may be called a size factor. When the drive transistor Trd operates in the saturation region, the drain current Ids begins to flow from the time when the gate voltage Vgs exceeds the threshold voltage Vth, as is apparent from the above formula 1. The magnitude of the drain current Ids increases in proportion to the square of the gate voltage Vgs. In this specification, the threshold voltage Vth of the driving transistor is assumed to be an absolute value of the threshold voltage of the driving transistor. Incidentally, since the threshold voltage has a negative value in a P-channel transistor, it is not correct if the value is directly put into the above equation 1. Therefore, in this specification, an absolute value is taken and Vth is handled as a positive value.

  The drive transistor Trd is, for example, a TFT having a polycrystalline silicon thin film as an active layer. As the polycrystalline silicon thin film, low-temperature polysilicon crystallized by laser annealing is often used. In general, low-temperature polysilicon TFTs tend to vary in threshold voltage Vth and carrier mobility μ for each device. In other words, Vth and μ of the drive transistor Trd are different for each pixel circuit 2.

上記数式２は数式１のドレイン電流Ｉｄｓを信号電流Ｉｓｉｇで置き換えたものとなっている。 The pixel circuit 2 performs a sampling operation and a light emission operation roughly. In the first sampling operation, the transistor Tr5 is turned off while the transistors Tr1 and Tr4 are turned on. When the signal line SL is driven by the current driver 3 in this state, the signal current Isig flows from the power source Vcc to the signal line SL through the driving transistor Trd and the switching transistors Tr4 and Tr1. The operating characteristic of the drive transistor Trd at this time is expressed by the following Equation 2.

Equation 2 above is obtained by replacing the drain current Ids of Equation 1 with the signal current Isig.

The gate voltage Vgs appearing between the gate G and the source S of the drive transistor Trd when the signal current Isig flows is expressed as the following Expression 3 by solving Expression 2 with Vgs.

  The gate voltage Vgs expressed by Equation 3 is held in the pixel capacitor Cs. In this manner, in the sampling operation, the gate voltage Vgs corresponding to the level of the signal current Isig supplied by the current driver 3 is written into the pixel capacitor Cs. In short, the signal current Isig is written to the gate of the drive transistor Trd.

Subsequently, in the light emitting operation, the transistors Tr1 and Tr4 are turned off while the Tr5 is turned on. As a result, the drive current Ids flows from the drive transistor Trd to the light emitting element EL, and emits light with a predetermined luminance. At this time, the drive current Ids flowing through the drive transistor Trd is expressed by the following Equation 4.

  Substituting Vgs obtained by Equation 3 into Vgs of Equation 4 results in cancellation of the terms of mobility μ and threshold voltage Vth, and Ids = Isig. Therefore, even if the mobility μ and the threshold voltage Vth of the drive transistor Trd vary from pixel to pixel, the signal current writing operation described above cancels all of them, and the screen uniformity can be maintained.

  The conventional pixel circuit shown in FIG. 16 has an advantage that the same drive current Ids as the signal current Isig can be supplied to the light emitting element EL regardless of variations in the mobility μ of the drive transistor and the threshold voltage Vth. The current driver 3 can change the luminance of the light emitting element EL from the black level to the white level through the intermediate gray level by controlling the level of the signal current Isig. At the black level, the signal current Isig is weak and approaches 0, while at the white level, the signal current Isig is large. However, the parasitic capacitance of the signal line SL is relatively large, such as several tens of pF, and in the conventional configuration shown in FIG. 16, the black level signal current Isig having a weak current value is assigned to one horizontal video period ( 1H), there was a problem that writing could not be performed sufficiently.

  FIG. 17 schematically shows this problem. The pixel array 1 constitutes a screen, and is a case where a white window is displayed on a black background. A gray area appears below the white window. Originally, this gray part belongs to the background and must be black. However, in the conventional pixel circuit configuration shown in FIG. 16, black level signal current cannot be written to the pixel located below the white window, and black floating and vertical crosstalk as shown in the figure occur. It has become a problem to be solved.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a pixel circuit and a display device capable of sufficiently writing a black level signal current, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, according to the present invention, a light emitting element, a driving transistor that supplies a driving current to the light emitting element, a signal line through which a signal current flows and a scanning line that supplies a control signal intersect, and the control signal. A pixel circuit comprising a control unit that operates and controls the drive current of the drive transistor based on the signal current, the control unit passing the signal current flowing through the signal line through the drive transistor and generating at the gate at that time A first sampling means for sampling a signal voltage to be processed into a first capacitor, and a second reference voltage generated at the gate through a predetermined reference current flowing through the signal line before and after the signal current. A second sampling means for sampling into a capacitor, a first capacitor that samples the signal voltage, and a second capacitor that samples the reference voltage; Difference means for obtaining a difference and holding the obtained difference as a control voltage in one of the first or second capacitor, and the drive transistor uses the control voltage held in one of the first or second capacitor. A driving current received between the gate and the source / drain is supplied to the light emitting element to emit light.

  Specifically, the signal voltage and the reference voltage sampled respectively by the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element is small and when the difference is large, the light emission amount is large. On the other hand, even when the relative difference between the two is small, the absolute levels of the signal current and the reference current are set so as to enable sampling. In one aspect, the control unit detects the threshold voltage of the drive transistor before determining the difference, holds the threshold voltage in a third capacitor, and then stores the held threshold voltage in the first or second capacitor. Correction means for adding to the control voltage held in one of the two, cancels the influence of the threshold voltage from the drive current. In another aspect, the control unit detects the threshold voltage of the driving transistor after obtaining the difference, holds the detected threshold voltage on the other side of the first or second capacitor, and stores the held threshold voltage. Correction means for adding to the control voltage held in one of the first and second capacitors is provided, and the influence of the threshold voltage is canceled from the drive current. Preferably, the control unit uses a first capacitor and a second capacitor having the same capacitance value.

  The present invention also includes a pixel array section, a driver section, and a scanner section, and the pixel array section includes column-shaped signal lines, row-shaped scanning lines, and matrix-shaped pixels arranged at portions where the two intersect. The driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, and each pixel circuit supplies a light emitting element and a driving current to the light emitting element. A display device comprising: a driving transistor to be supplied; and an in-pixel control unit that operates in accordance with the control signal and controls the driving current of the driving transistor based on the signal current, wherein the in-pixel control unit includes: A first sampling means for sampling a signal voltage generated at the gate of the signal current flowing in the signal line through the drive transistor into a first capacitor; and a predetermined reference current flowing in the signal line before and after the signal current. The second sampling means for sampling the reference voltage generated at the gate through the driving transistor at that time into the second capacitor, and the first capacitor for sampling the signal voltage and the second capacitor for sampling the reference voltage are mutually connected. Differential means for connecting and obtaining the difference and holding the obtained difference as a control voltage in one of the first or second capacitor, and the drive transistor is held in one of the first or second capacitor The control light is received by the gate, and a driving current flowing between the source and the drain is supplied to the light emitting element to emit light.

  Specifically, the signal voltage and the reference voltage sampled respectively by the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element is small and when the difference is large, the light emission amount is large. On the other hand, even when the relative difference between the two is small, the absolute levels of the signal current and the reference current are set so as to enable sampling. In one aspect, the intra-pixel control unit detects a threshold voltage of the driving transistor before obtaining the difference, holds the threshold voltage in a third capacitor, and then stores the held threshold voltage in the first or second. Correction means for adding to the control voltage held in one of the capacitors, and canceling the influence of the threshold voltage from the drive current. In another aspect, the intra-pixel control unit detects the threshold voltage of the driving transistor after obtaining the difference, holds the detected threshold voltage on the other side of the first or second capacitor, and holds the held threshold value. Correction means for adding the voltage to the control voltage held in one of the first and second capacitors is provided, and the influence of the threshold voltage is canceled from the drive current. Preferably, the intra-pixel control unit uses a first capacitor and a second capacitor having the same capacitance value.

  The present invention further includes a light emitting element, a driving transistor that supplies a driving current to the light emitting element, a signal line through which a signal current flows and a scanning line that supplies a control signal, and a control signal corresponding to the control signal. A pixel circuit driving method comprising: a control unit configured to operate and control a driving current of the driving transistor based on the signal current, wherein the signal current flowing through the signal line is passed through the driving transistor and generated at the gate at that time A first sampling procedure for sampling the signal voltage into the first capacitor, and a predetermined reference current flowing through the signal line before and after the signal current is passed through the drive transistor, and the reference voltage generated at the gate at that time is the second capacitor. A second sampling procedure for sampling the signal voltage, and a first capacitor for sampling the signal voltage and a second capacitor for sampling the reference voltage, A difference procedure for obtaining a difference and holding the obtained difference as a control voltage in one of the first and second capacitors, and applying the control voltage to the gate of the drive transistor to generate a drive current flowing between the source and the drain. And a light emission procedure to be supplied to the element.

  In addition, the present invention includes a pixel array unit, a driver unit, and a scanner unit, and the pixel array unit has a matrix signal line, a row-shaped scanning line, and a matrix-like arrangement arranged at the intersection of the two. The pixel circuit includes a pixel circuit, the driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, and each pixel circuit supplies a light emitting element and a driving current to the light emitting element. A display device driving method for controlling a driving current of the driving transistor based on the signal current according to the control signal, wherein a signal current flowing through the signal line is passed through the driving transistor at that time. A first sampling procedure for sampling the signal voltage generated at the gate into the first capacitor, and a predetermined reference current flowing through the signal line before and after the signal current is passed through the drive transistor, A second sampling procedure for sampling a reference voltage generated in the second capacitor into a second capacitor, a first capacitor that samples the signal voltage, and a second capacitor that samples the reference voltage are connected to each other to obtain a difference. A difference procedure for holding the obtained difference as a control voltage in one of the first and second capacitors, and a drive current flowing between the source and the drain by applying the control voltage to the gate of the drive transistor to the light emitting element And a light emission procedure to be supplied.

  The display device according to the present invention supplies not only a signal current but also a reference current from the current driver side. The pixel circuit samples the signal current and the reference current into a pair of capacitors before and after, and further obtains the difference between the two by a capacitance canceling operation, which is used as the gate control voltage of the driving transistor. Thereby, the drive transistor can drive the light emitting element according to the difference of the signal current with respect to the reference current. At this time, the difference in the light emission luminance at the black level is close to 0, and the signal current is substantially the same as the reference current. Even in such a state, the absolute values of the signal current and the reference current can be set sufficiently higher than the parasitic capacitance of the signal line. Therefore, even a black level current can be written into each pixel at a sufficiently high speed, and black floating and vertical crosstalk, which have been problems in the past, can be prevented. Since the level of the signal current and the reference current can be set high without depending on the luminance gradation to be displayed, even the black display current can be sufficiently written to the pixels within one horizontal period, and the luminance is sufficiently reduced. It is possible to express black and obtain high contrast characteristics. In addition, since the drive current for the light emitting element is controlled by obtaining the difference between the signal current and the reference current without depending on the threshold voltage or mobility of the drive transistor, a high uniformity is achieved without being affected by variations in the characteristics of the drive transistor. Mitty's image can be displayed. In particular, the effect of the present invention is significant in a pixel circuit using a low-temperature polysilicon TFT whose mobility and threshold voltage vary greatly.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic circuit diagram showing a first embodiment of a pixel circuit according to the present invention. The pixel circuit 2 is arranged at a portion where the column-shaped signal line SL and the row-shaped scanning lines WS1, WS2, WS3, AZ, DS intersect. A signal current Isig and a reference current Iref are passed through the signal line SL from a current driver (not shown). Control signals WS1, WS2, WS3, AZ, and DS are supplied from the corresponding scanners to the scanning lines WS1, WS2, WS3, AZ, and DS, respectively. In this specification, in order to simplify the notation, the same reference numerals are used for the scanning lines and the corresponding control signals. The pixel circuit shown in FIG. 1 can be incorporated into a pixel array of a display device as shown in FIG. 15, for example. In this case, the corresponding control signals WS1, WS2 and WS3 are supplied from the write scanner 4 to the scanning lines WS1, WS2 and WS3, respectively. A control signal AZ is supplied to the scanning line AZ from the correction scanner 7. Further, a control signal DS is supplied from the drive scanner 5 to the scanning line DS.

  The pixel circuit 2 includes eight switching transistors Tr1 to Tr8, one drive transistor Trd, three pixel capacitors Cs1 to Cs3, and a light emitting element EL. The switching transistors Tr1 to Tr8 are all N-channel thin film transistors. The drive transistor Trd is a P-channel thin film transistor. The light emitting element EL is a two-terminal (diode type) light emitting element having an anode and a cathode, and for example, an organic EL element can be used. In the above embodiment, the transistors Tr1 to Tr8 are all N-channel type, but they may all be P-channel type or a mixture of N-channel type and P-channel type.

  The drive transistor Trd has its source S connected to the power supply Vcc, its drain D connected to the anode side of the light emitting element EL via the switching transistor Tr1, and its gate G connected to one end of the pixel capacitor Cs3. A control signal DS is applied from the scanning line DS to the gate of the switching transistor Tr1 interposed between the drive transistor Trd and the light emitting element EL. A switching transistor Tr2 is connected between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr2 is connected to the scanning line AZ.

  The source / drain of the switching transistor Tr3 is connected between the signal line SL and the other end of the pixel capacitor Cs3. The gate of the transistor Tr3 is connected to the scanning line WS1. The switching transistor Tr5 is connected between the other end of the pixel capacitor Cs3 and one end of the pixel capacitor Cs1. The gate of the switching transistor Tr5 is connected to the scanning line WS1 like the transistor Tr3. The other end of the pixel capacitor Cs1 is connected to the power supply Vcc. The switching transistor Tr4 is connected between the power supply Vcc and one end of the pixel capacitor Cs2. The gate of the switching transistor Tr4 is connected to the scanning line WS2. The other end of the pixel capacitor Cs2 is connected to the other end of the pixel capacitor Cs3. The switching transistor Tr6 is connected between one end of the pixel capacitor Cs1 and one end of the pixel capacitor Cs2. The gate of the transistor Tr6 is connected to the scanning line WS3. The transistor Tr7 is connected between the other end of the pixel capacitor Cs1 and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr7 is connected to the scanning line WS3 like Tr6. Finally, the switching transistor Tr8 is connected between the drain D of the driving transistor Trd and the other end of the pixel capacitor Cs3. The gate of the transistor Tr8 is connected to the scanning line WS1 like the switching transistors Tr3 and Tr5.

  FIG. 2 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. A change in the waveform of the control signals DS, AZ, WS1, WS2, and WS3 is represented along the time axis T. At the same time, the waveform change of the signal current Isig is also shown. The signal level of the signal current Isig changes every horizontal period (1H). Further, after the signal current Isig flows in the first half within each horizontal period, the second half switches to a predetermined reference current Iref. While the reference current Iref is fixed, the signal current Isig changes according to the video signal. This display device writes one screen in the pixel array in one field. In the timing chart of FIG. 2, it is described that one field starts from the timing T1.

  In a period T0 before the timing T1 when the field starts, the control signal DS is at a high level, while the remaining control signals AZ, WS1, WS2, and WS3 are at a low level. Since the control signal DS is at a high level, the switching transistor Tr1 is turned on, and the light emitting element EL is driven by the drive transistor Trd and is in a light emitting state.

  When the field starts at timing T1, the control signals AZ and WS3 are switched from the low level to the high level. Thus, a preparation state for detecting the threshold voltage Vth of the drive transistor Trd is entered. Subsequently, at timing T2, the control signal DS is switched from the high level to the low level, the light emitting element EL changes from the light emitting state to the non-light emitting state, and the threshold voltage Vth of the driving transistor Trd is detected. Subsequently, at timing T3, the control signals AZ and WS3 become low level, and the detected threshold voltage is held and fixed. This held and fixed Vth is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd at a later light emission stage. Therefore, a period T2-T3 from timing T2 to timing T3 may be referred to as a Vth correction period.

  When the timing T4 is reached, the control signals WS1 and WS2 are switched to a high level. At this time, the signal current Isig flows through the signal line SL. This signal current Isig is sampled and written into the pixel circuit 2. Subsequently, when the control signal WS2 is switched to the low level at the timing T5, the Isig writing is completed. A period in which Isig is sampled from timing T4 to timing T5 may be referred to as an Isig writing period.

  Subsequently, when the current flowing through the signal line SL is switched from the signal current Isig to Iref after the timing T5, the reference current Iref is sampled. When the control signal WS1 returns to the low level at the timing T6, the writing of Iref is completed. A period T5-T6 from timing T5 to timing T6 is called an Iref writing period.

  As is clear from the above description, Isig writing and Iref writing are sequentially performed while the control signal WS1 is at the high level from timing T4 to T6. The period T4-T6 during which the control signal WS1 is at the high level is exactly one horizontal period (1H). It is possible to sample Isig and Iref sequentially in one horizontal period 1H assigned to the pixel circuit 2.

  Thereafter, the control signal WS3 rises at timing T7, and the control signal WS3 falls similarly at timing T8. The difference between Isig and Iref is obtained in the period T7-T8 when the control signal WS3 is at the high level. This difference is performed by the cancel operation of the pixel capacitors Cs1 and Cs2. Therefore, this period T7-T8 may be referred to as a capacity cancellation period.

  At timing T9, the control signal DS changes to high level and the control signal WS2 also becomes high level. As a result, the pixel capacitors Cs2 and Cs3 are coupled, and the drive current Ids is supplied from the drive transistor Trd to the light emitting element EL, and the light emission operation is performed.

  FIG. 3 is a schematic diagram showing a Vth cancel operation performed in the Vth correction period T2-T3 shown in FIG. In this period T2-T3, the switching transistors Tr1, Tr3, Tr4, Tr5, Tr8 are turned off, while Tr2, Tr6, and Tr7 are turned on. As a result, one end of the pixel capacitor Cs3 is connected to the gate of the drive transistor Trd, while the other end is connected to the power supply Vcc via the transistor Tr7. When the switch Tr1 is turned off while a current is flowing from the power source Vcc toward the light emitting element EL, the current path is cut off, so that the pixel capacitor Cs3 is charged through the transistor Tr2. With this charging, the gate potential of the drive transistor Trd rises. The drive transistor Trd is cut off just when the gate potential becomes Vth of the drive transistor Trd. Vth of the drive transistor Trd detected at this time is held at both ends of the pixel capacitor Cs3. Thereafter, the transistor Tr2 is turned off, and Vth held in the pixel capacitor Cs3 is fixed. The Vth held and fixed in this way is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd in a later light emission operation.

上記数式５において、Ｖｇｓは駆動トランジスタＴｒｄのゲートソース間に現れるゲート電圧を表し、Ｖｔｈは同じく駆動トランジスタＴｒｄの閾電圧を表し、ｋは同じく駆動トランジスタＴｒｄのサイズファクタを表し、μは同じく移動度を表している。 FIG. 4 is a schematic diagram showing the Isig write operation performed in the period T4-T5 shown in the timing chart of FIG. In this period, the signal current Isig flows through the signal line. Further, the transistors Tr1, Tr2, Tr6, Tr7 are turned off, while the transistors Tr3, Tr4, Tr5, Tr8 are turned on. As a result, the signal current Isig flows from the power source Vcc to the signal line side through the drive transistor Trd, the switching transistor Tr8, and the switching transistor Tr3. In other words, Isig flows through the drive transistor Trd as a drain current. Therefore, in accordance with the basic characteristics of the transistor expressed by Equation 1, the drain current Isig is expressed by Equation 5 below.

In Equation 5, Vgs represents the gate voltage appearing between the gate and source of the drive transistor Trd, Vth represents the threshold voltage of the drive transistor Trd, k represents the size factor of the drive transistor Trd, and μ represents the mobility. Represents.

Here, when formula 5 is arranged for Vgs, the following formula 6 is obtained.

Referring to FIG. 4, pixel capacitors Cs2 and Cs3 are connected in series between the source and gate of the drive transistor Trd. Here, when the voltage held at both ends of the pixel capacitor Cs2 is Vcs2, and the voltage held in the pixel capacitor Cs3 is Vcs3, the gate voltage Vgs = Vcs2 + Vcs3. Here, Vcs3 is set to Vth by the previous Vth cancel operation. Therefore, Vgs = Vcs2 + Vth. By substituting Vgs given in Formula 24 for Vgs in this formula, the voltage Vcs2 held in the pixel capacitor Cs2 is given by Formula 7 below.

  As is clear from Equation 7, the voltage Vcs2 held in the pixel capacitor Cs2 is proportional to the square root of the signal current Isig. In other words, the voltage Vcs2 corresponding to the signal current Isig is sampled and held in the pixel capacitor Cs2 by the Isig writing operation in the period T4-T5.

FIG. 5 is a schematic diagram showing an Iref write operation performed in the period T5-T6 shown in FIG. When the Isig write operation shown in FIG. 4 proceeds to the Iref write operation of this figure, the control line WS2 goes low, and as a result, the transistor Tr4 is turned off. The states of the other switching transistors are maintained as they are. Therefore, as apparent from a comparison between FIGS. 4 and 5, the pixel capacitance Cs2 is switched to the pixel capacitance Cs1. More specifically, in the Isig write operation of FIG. 4, the pixel capacitors Cs2 and Cs3 are connected in series between the source / gate of the drive transistor Trd, whereas in the Iref write operation of FIG. 4, the drive transistor Trd. A pixel capacitor Cs1 and a pixel capacitor Cs3 are connected in series between the source and the gate. That is, as a circuit operation, Cs2 is simply replaced by Cs1. At this time, Iref flows in the signal line instead of the previous Isig. More specifically, the reference current Iref flows from the power source Vcc through the drive transistor Trd and further flows to the signal line side via the switching transistors Tr8 and Tr3. At this time, a part of the gate voltage Vgs generated between the source and the gate of the drive transistor Trd is held in the pixel capacitor Cs1. Assuming that this voltage is Vcs1, it is expressed as in the following Expression 8 in exactly the same manner as in Expression 7.

  Here, as apparent from a comparison between Expression 7 and Expression 8, the left side of the expression is replaced from Vcs2 to Vcs1, while the right side of the expression is replaced from Isig to Iref. As is apparent from Equation 8, the voltage Vcs1 held in the pixel capacitor Cs1 corresponds to the square root of the reference current Iref. In other words, in this Iref writing operation, a voltage corresponding to the reference current Iref is sampled in the pixel capacitor Cs1.

FIG. 6 is a schematic diagram illustrating the capacity canceling operation performed in the period T7 to T8 in the timing chart illustrated in FIG. In this operation, the switching transistors Tr3, Tr5 and Tr8 are turned off, while Tr6 and Tr7 are turned on. As a result, the negative terminal of the pixel capacitor Cs1 and the positive terminal of the pixel capacitor Cs2 are connected, and the positive terminal of the pixel capacitor Cs1 and the negative terminal of the pixel capacitor Cs2 are connected. Thereby, the capacity cancellation of the pixel capacities Cs1 and Cs2 is performed between Vcs1 and Vcs2. That is, a difference between the voltage Vcs1 held in the pixel capacitor Cs1 and the voltage Vcs2 held in the pixel capacitor Cs2 is obtained, and this difference is held at both ends of the pixel capacitor Cs2. Here, when the pixel capacitors Cs1 and Cs2 have the same capacitance, the potential Vcs2 ′ held in the pixel capacitor Cs2 after the capacitance cancellation is given by the following Equation 9.

  As is apparent from Equation 9, Vcs2 ′ is a value corresponding to the difference between the signal current Isig and the reference current Iref. Precisely, a voltage corresponding to the difference between the square root of Isig and the square root of Iref is held as Vcs2 ′ in the pixel capacitor Cs2.

  FIG. 7 is a schematic diagram showing capacitive coupling and light emission operation in a light emission period performed after timing T9 shown in FIG. When the timing T9 is reached, the control signals DS and WS2 become high level, while the other control signals are all at low level. Accordingly, the switching transistors Tr4 and Tr1 are turned on, while the remaining switching transistors Tr3, Tr5, Tr6, Tr7, Tr2, and Tr8 are turned off. Since Tr4 is turned on, the pixel capacitors Cs2 and Cs3 are coupled between the source and gate of the drive transistor Trd. At this time, since the gate capacitance Cg of the drive transistor Trd is sufficiently small, the pixel capacitances Cs2 and Cs3 are coupled in a state in which the mutual charges are held. That is, the gate voltage Vgs of the drive transistor Trd during light emission is Vgs = Vcs3 + Vcs2 ′ = Vth + Vcs2 ′.

When Vgs obtained in this way is included in the basic characteristic equation of the transistor shown in Equation 1, a drive current Ids as shown in Equation 10 below can be obtained.

  In the first stage of Equation 10, Vth + Vcs2 ′ is substituted for Vgs. As a result, Vth is canceled and the drive current Ids takes a form proportional to the square of Vcs2 ′. Further, as shown in the second stage of Expression 10, Expression 9 is substituted into Vcs2 ′. Thereafter, the mobility μ appearing in the denominator and the mobility μ of the coefficient part are canceled, and finally the form represented by the third stage of Equation 10 is obtained. As is apparent from this equation, the drive current (light emission current) Ids is determined by the current difference value between Isig and Iref, and high uniformity image quality can be obtained regardless of variations in Vth and mobility μ of the drive transistor. . Furthermore, in the pixel circuit of the present invention, Isig = Iref is set during black display. As is apparent from Equation 10, when Isig = Iref, Ids = 0 and the light emission current disappears. This results in a complete black display. On the other hand, even in black display, the absolute value of Iref can be set to a sufficiently high level, and a black signal can be sufficiently written within one horizontal period (1H). As a result, it is possible to suppress the occurrence of black floating and vertical crosstalk, and it is possible to express completely sunken black and obtain high contrast characteristics.

  As described above, the pixel circuit according to the first embodiment of the present invention shown in FIG. 1 includes the signal line SL through which the signal current Isig flows and the scanning lines WS1, WS2, WS3, AZ, DS that supply control signals. It is arranged at the intersection of and. The pixel circuit 2 includes a light-emitting element EL, a drive transistor Trd that supplies a drive current Ids to the light-emitting element EL, and operates according to control signals WS1, WS2, WS3, AZ, DS, and a drive transistor based on the signal current Isig. It is comprised with the control part which controls the drive current Ids of Trd. The control unit includes first sampling means, second sampling means, and difference means. The first sampling means is composed of transistors Tr3, Tr4, Tr8 and a pixel capacitor Cs2. A signal current Isig flowing through the signal line SL is passed through the drive transistor Trd, and the signal voltage Vcs2 generated at the gate G at that time is a first voltage. Sampling is performed on the capacitor Cs2. The second sampling means is composed of transistors Tr3, Tr5, Tr8 and a pixel capacitor Cs1, and passes a predetermined reference current Iref flowing in the signal line SL before and after the signal current Isig through the driving transistor Trd, and a reference generated at the gate G at that time. The voltage Vcs1 is sampled to the second capacitor Cs1. The difference means includes transistors Tr6 and Tr7 and a pair of pixel capacitors Cs1 and Cs2, and connects the first capacitor Cs2 sampled from the signal voltage Vcs2 and the second capacitor Cs1 sampled from the reference voltage Vcs1 to each other. Then, the difference Vcs2 ′ is obtained, and the obtained difference Vcs2 ′ is held in Cs2, which is one of the first and second capacitors, as the control voltage. The drive transistor Trd receives the control voltage Vcs2 ′ held in Cs2 which is one of the first and second capacitors at the gate G, and outputs a drive current Ids flowing between the source (S) and the drain (D) to the light emitting element EL. To emit light.

  The signal voltage Vcs2 and the reference voltage Vcs1 sampled respectively by the first and second sampling means are such that the light emission amount of the light emitting element EL is small when the relative difference Vcs2 ′ between them is small and the light emission amount is large when the difference Vcs2 ′ is large. On the other hand, the absolute levels of the signal current Isig and the reference current Iref are set so as to enable sampling even when the relative difference Vcs2 ′ between them is small.

  The control unit in the pixel circuit 2 described above has correction means in addition to the first and second sampling means and the difference means. This correction means is composed of transistors Tr1, Tr2, Tr7 and a pixel capacitor Cs3, and detects the threshold voltage Vth of the driving transistor Trd and holds it in the third capacitor Cs3 before obtaining the above-described difference Vcs2 ′. Thereafter, the held threshold voltage Vth is added to the control voltage Vcs2 ′ held in Cs2 which is one of the first and second capacitors. Thereby, the influence of the threshold voltage Vth can be canceled from the drive current Ids.

  FIG. 8 is a schematic circuit diagram showing a second embodiment of the pixel circuit according to the present invention. For easy understanding, the parts corresponding to those in the first embodiment shown in FIG. The pixel circuit 2 is arranged at a portion where the column-shaped signal line SL and the row-shaped scanning lines WS1, WS2, WS3, AZ1, AZ2, and DS intersect. A signal current Isig and a reference current Iref are passed through the signal line SL from a current driver (not shown). Control signals WS1, WS2, WS3, AZ1, AZ2, and DS are supplied from the corresponding scanners to the scanning lines WS1, WS2, WS3, AZ1, AZ2, and DS, respectively. For example, the pixel circuit 2 can be integrated in the pixel array of the display device shown in FIG. In that case, the peripheral write scanner 4 supplies the control signals WS1, WS2 and WS3 to the pixel array 1, the correction scanner 7 supplies the control signals AZ1 and AZ2 to the pixel array 1, and the drive scanner 5 controls the control signal DS. Are also supplied to the pixel array 1. On the other hand, the current driver 3 supplies the signal current Isig and the reference current Iref to each signal line SL of the pixel array 1 in one horizontal cycle (1H).

  The pixel circuit 2 includes seven switching transistors Tr1 to Tr7, one drive transistor Trd, two pixel capacitors Cs1 and Cs2, and a light emitting element EL. As is clear from the comparison with the first embodiment shown in FIG. 1, the second embodiment of FIG. 8 has one fewer transistors and one fewer pixel capacitors. Therefore, the second embodiment is advantageous in terms of cost compared to the first embodiment. However, as the number of elements is reduced, the number of control lines is increased by one. Specifically, the first embodiment uses one control line AZ, while the second embodiment uses two control lines AZ1 and AZ2. The switching transistors Tr1 to Tr7 are all N-channel type thin film transistors. On the other hand, the drive transistor Trd is a P-channel thin film transistor. However, the present invention is not limited to this, and N-channel and P-channel thin film transistors can be freely combined depending on the device design. The light emitting element EL is a two-terminal (diode type) light emitting element having an anode and a cathode, and for example, an organic EL element can be used.

  The drive transistor Trd has its source S connected to the power supply Vcc, its drain D connected to the anode side of the light emitting element EL via the switching transistor Tr1, and its gate G connected to one end of the pixel capacitor Cs2. A control signal DS is applied from the scanning line DS to the gate of the switching transistor Tr1 interposed between the drive transistor Trd and the light emitting element EL. A switching transistor Tr2 is connected between the gate G and the drain D of the drive transistor Trd. The gate of the transistor Tr2 is connected to the scanning line AZ1.

  On the other hand, the switching transistor Tr3 located on the input side of the pixel circuit has its source / drain connected between the signal line SL and the gate G of the driving transistor Trd. The gate of the transistor Tr3 is connected to the scanning line WS1. The switching transistor Tr5 is connected between the gate G of the drive transistor Trd and one end of the pixel capacitor Cs1. The gate of the switching transistor Tr5 is connected to the scanning line AZ1. The other end of the pixel capacitor Cs1 is connected to the power supply Vcc. The switching transistor Tr4 is connected between the power supply Vcc and the other end of the pixel capacitor Cs2. The gate of the switching transistor Tr4 is connected to the scanning line AZ2. The switching transistor Tr6 is connected between one end of the pixel capacitor Cs1 and the other end of the pixel capacitor Cs2. The gate of the transistor Tr6 is connected to the scanning line WS3. The transistor Tr7 is connected between the other end of the pixel capacitor Cs1 and one end of the pixel capacitor Cs2. The gate of the switching transistor Tr7 is connected to the scanning line WS2.

  FIG. 9 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. A change in the waveform of the control signals DS, AZ1, WS1, AZ2, WS2, and WS3 is represented along the time axis T. At the same time, the waveform change of the signal current Isig is also shown. The signal level of the signal current Isig changes every horizontal period (1H). Further, after the signal current Isig flows in the first half in each horizontal period, the second half is switched to a predetermined reference current Iref. While the reference current Iref is fixed, the signal current Isig changes according to the video signal. This display device writes one screen in the pixel array in one field. The timing chart of FIG. 9 is drawn so that one field starts from timing T1.

  In the period T0 before the timing T1 when the field starts, the control signals DS and WS3 are at the high level, while the remaining control signals AZ1, AZ2, WS1, and WS2 are at the low level. Since the control signal DS is at a high level, the switching transistor Tr1 is turned on, and the light emitting element EL is driven by the drive transistor Trd and is in a light emitting state. Since the control signal WS3 is also at a high level, the switching transistor Tr6 is turned on, and the pair of pixel capacitors Cs1 and Cs2 are connected in series between the power supply Vcc and the gate G of the drive transistor Trd.

  When the field starts at timing T1, the control signals DS and WS3 are switched from the high level to the low level. As a result, the switching transistor Tr1 is turned off, and light emission is stopped. In other words, when the field starts, the light emission state of the previous field is temporarily switched to the non-light emission state. At the same time, the transistor Tr6 is also turned off, so that the pair of pixel capacitors Cs1 and Cs2 are separated from each other.

  When the timing T2 is reached, the control signals AZ1, WS1, and AZ2 are switched to a high level. At this time, the signal current Isig flows through the signal line SL. This signal current Isig is sampled and written into the pixel circuit 2. Subsequently, when the control signal AZ2 is switched to the low level at the timing T3, the Isig writing is completed. A period in which Isig is sampled from timing T2 to timing T3 may be referred to as an Isig writing period. Subsequently, when the current flowing through the signal line SL is switched from the signal current Isig to Iref at timing T4, the reference current Iref is sampled. When the control signals AZ1 and WS1 return to the low level at the timing T5, the writing of Iref is completed. A period T4-T5 from timing T4 to timing T5 is called an Iref write period. As is apparent from the above description, Isig writing and Iref writing are sequentially performed while the control signals AZ1 and WS1 are at the high level from timing T2 to T5. The period T2-T5 in which the control line WS1 is at the high level is exactly one horizontal period (1H). It is possible to sample Isig and Iref sequentially in one horizontal period 1H assigned to the pixel circuit 2. When the control signals WS1 and AZ1 return to the low level at timing T5, the writing of Iref is completed.

  Thereafter, the control signals WS2 and WS3 rise at timing T6, and the control signals WS2 and WS3 fall at timing T7. The difference between Isig and Iref is obtained in the period T6-T7 in which the control signals WS2 and WS3 are at the high level. This difference is performed by the cancel operation of the pixel capacitors Cs1 and Cs2. Therefore, this period T6-T7 may be referred to as a capacity cancellation period.

  At timing T8, the control signal DS switches from the low level to the high level. At subsequent timing T9, the control signal AZ1 is switched from the low level to the high level. Thus, a preparation state for detecting the threshold voltage Vth of the drive transistor Trd is entered. Subsequently, at timing T10, the control signal DS returns from the high level to the low level, and the threshold voltage Vth of the drive transistor Trd is detected. Subsequently, at timing T11, the control signal AZ1 returns to the low level, and the detected threshold voltage Vth is held and fixed. This held and fixed Vth is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd in the subsequent light emission stage. Therefore, the period T10-T11 from timing T10 to T11 may be referred to as a Vth correction period.

  At timing T12, the control signal DS changes to high level again and the control signal WS3 also changes to high level. As a result, the pixel capacitors Cs1 and Cs2 are coupled, and the drive current Ids is supplied from the drive transistor Trd to the light emitting element EL to perform the light emission operation. This light emission operation continues until the field ends.

FIG. 10 is a schematic diagram showing the Isig write operation performed in the Isig write period T2-T3 shown in FIG. In this period, the signal current Isig flows through the signal line. Further, the transistors Tr1, Tr6, Tr7 are turned off, while the transistors Tr3, Tr4, Tr5 are turned on. As a result, the signal current Isig flows from the power source Vcc to the signal line side through the drive transistor Trd, the switching transistor Tr2, and the switching transistor Tr3. In other words, Isig flows through the drive transistor Trd as a drain current. In this manner, the signal current Isig flowing in the signal line is passed through the drive transistor Trd, and the signal voltage Vgs generated at the gate G at that time is sampled in the pixel capacitor Cs2. This signal voltage Vgs is expressed by the following Expression 11 in the same manner as Expression 6 above.

FIG. 11 is a schematic diagram showing an Iref write operation performed in the period T4-T5 shown in FIG. When the Isig write operation shown in FIG. 10 progresses to the Iref write operation of this figure, the control line AZ2 becomes low level, so that the transistor Tr4 is turned off. The states of the other switching transistors are maintained as they are. Therefore, as apparent from a comparison between FIGS. 10 and 11, the pixel capacitance Cs2 is switched to the pixel capacitance Cs1. More specifically, the pixel capacitance Cs2 is connected between the source / gate of the drive transistor Trd in the Isig write operation of FIG. 10, whereas the source / gate of the drive transistor Trd is connected in the Iref write operation of FIG. Is connected to the pixel capacitor Cs1. That is, as a circuit operation, Cs2 is merely replaced with Cs1. At this time, Iref flows in the signal line instead of the previous Isig. More specifically, the reference current Iref flows from the power supply Vcc through the drive transistor Trd and further flows to the signal line side via the switching transistors Tr2 and Tr3. At this time, the reference voltage Vgs ′ generated at the gate G of the drive transistor Trd is sampled in the pixel capacitor Cs1. This reference voltage Vgs ′ is expressed as in the following expression 12 in the same manner as in expression 11.

FIG. 12 is a schematic diagram illustrating the capacity canceling operation performed in the period T6-T7 of the timing chart illustrated in FIG. In this operation, the switching transistors Tr1, Tr2, Tr3, Tr4, Tr5 are turned off, while Tr6 and Tr7 are turned on. As a result, the negative terminal of the pixel capacitor Cs1 and the positive terminal of the pixel capacitor Cs2 are connected, and the positive terminal of the pixel capacitor Cs1 and the negative terminal of the pixel capacitor Cs2 are connected. Thereby, the capacitance cancellation of the pixel capacitors Cs1 and Cs2 is performed between the reference voltage Vgs ′ and the signal voltage Vgs. That is, a difference between the reference voltage Vgs ′ held in the pixel capacitor Cs1 and the signal voltage Vgs held in the pixel capacitor Cs2 is obtained, and this difference is held at both ends of the pixel capacitor Cs2. Here, when the capacitance values of the pixel capacitors Cs1 and Cs2 are equal, the control voltage Vcs2 held in the pixel capacitor Cs2 after the capacitance cancellation is given by Equation 13 below.

  As is apparent from the equation 13, the control voltage Vcs2 has a value corresponding to the difference between the signal current Isig and the reference current Iref. More precisely, a voltage corresponding to the difference between the square root of Isig and the square root of Iref is held as the control voltage Vcs2 in the pixel capacitor Cs2.

  FIG. 13 is a schematic diagram showing a Vth cancel operation performed in the Vth correction period T10-T11 shown in FIG. In this period T10-T11, the switching transistors Tr1, Tr3, Tr4, Tr6, Tr7 are turned off, while the switching transistors Tr2, Tr5 are turned on. As a result, one end of the pixel capacitor Cs1 is connected to the gate G of the drive transistor Trd, and the other end is connected to the power supply Vcc. When the switch Tr1 is turned off while a current flows from the power source Vcc toward the light emitting element EL, the current path is cut off, so that the pixel capacitor Cs1 is charged through the transistor Tr2. With this charging, the gate potential of the drive transistor Trd rises. The drive transistor Trd is cut off just when the gate potential becomes Vth of the drive transistor Trd. Vth of the drive transistor Trd detected at this time is held at both ends of the pixel capacitor Cs1. Thereafter, the transistor Tr2 is turned off, and Vth held in the pixel capacitor Cs1 is fixed. The Vth held and fixed in this way is used for canceling or correcting variations in the threshold voltage of the drive transistor Trd in a later light emission operation. Here, unlike the first embodiment shown in FIG. 1, the second embodiment uses the pixel capacitance Cs1 that has been used in the previous capacitance cancel operation in order to hold the detected Vth. As a result, this embodiment can reduce the number of elements of the pixel capacitance to two. On the other hand, the first embodiment includes the pixel capacitor Cs3 for holding Vth in addition to the pair of pixel capacitors Cs1 and Cs2 used for holding the signal voltage and the reference voltage.

  FIG. 14 is a schematic diagram showing capacitive coupling and light emission operation in the light emission period performed after timing T12 shown in FIG. When the timing T12 is reached, the control signals DS and WS3 are at a high level, while the other control signals are all at a low level. Accordingly, the switching transistors Tr1, Tr6 are turned on, while the remaining switching transistors Tr2, Tr3, Tr4, Tr5, Tr7 are turned off. Since Tr6 is turned on, the pixel capacitors Cs1 and Cs2 are coupled in series between the source S and the gate G of the drive transistor Trd. At this time, since the gate capacitance Cg of the drive transistor Trd is sufficiently small, the pixel capacitances Cs1 and Cs2 are coupled in a state in which the mutual charges are held. That is, the gate voltage Vgs of the drive transistor Trd during light emission is represented by the sum of the threshold voltage Vth and the control voltage Vcs2, and Vgs = Vth + Vcs2.

When the Vgs obtained in this way is put into the basic characteristic equation of the transistor shown in Equation 1, a drive current Ids as shown in Equation 14 below can be obtained.

  In the first stage of Equation 14, Vth + Vcs2 is substituted for Vgs. As a result, Vth is canceled, and the drive current Ids takes a form proportional to the square of Vcs2. Further, as shown in the second stage of Equation 14, the previous Equation 13 is substituted into Vcs2. Thereafter, the mobility μ appearing in the denominator and the mobility μ of the coefficient part are canceled, and finally the form expressed by the third stage of Equation 14 is obtained. As is apparent from this equation, the drive current (light emission current) Ids is determined by the current difference value between Isig and Iref, and high uniformity image quality can be obtained regardless of variations in Vth and mobility μ of the drive transistor. . Furthermore, in the pixel circuit of the present invention, Isig = Iref is set during black display. As is apparent from Equation 14, when Isig = Iref, Ids = 0 and the light emission current disappears. This results in a complete black display. On the other hand, even in black display, the absolute value of Iref can be set to a sufficiently high level, and a black signal can be sufficiently written within one horizontal period (1H). As a result, it is possible to suppress the occurrence of black floating and vertical crosstalk, and it is possible to express completely sunken black and obtain high contrast characteristics.

  As described above, the pixel circuit according to the second embodiment of the present invention shown in FIG. 8 includes the signal line SL through which the signal current Isig flows and the scanning lines WS1, WS2, WS3, AZ1, and AZ2 that supply the control signals. , DS are arranged at the intersection. The pixel circuit 2 operates in accordance with the light emitting element EL, the driving transistor Trd that supplies the driving current Ids to the light emitting element EL, and the control signals WS1, WS2, WS3, AZ1, AZ2, and DS, and is based on the signal current Isig. And a control unit that controls the drive current Ids of the drive transistor Trd. The intra-pixel control unit includes first sampling means, second sampling means, and difference means. The first sampling means is composed of switching transistors Tr2, Tr3, Tr4, Tr5 and a pixel capacitor Cs2. The signal current Isig flowing through the signal line SL is passed through the drive transistor Trd and the signal voltage Vgs generated at the gate G at that time is the first. Sampling is performed to a capacitance Cs2 of 1. The second sampling means is composed of switching transistors Tr2, Tr3, Tr5 and a pixel capacitor Cs1, and passes a predetermined reference current Iref flowing in the signal line before and after the signal current Isig through the drive transistor Trd, at which time the reference voltage Vgs generated at the gate G 'Is sampled in the second capacitor Cs1. The difference means includes switching transistors Tr6 and Tr7. The first capacitor Cs2 that samples the signal voltage Vgs and the second capacitor Cs1 that samples the reference voltage Vgs ′ are connected to each other to obtain a difference. Is held at Cs2 which is one of the first and second capacitors as the control voltage Vcs2. The drive transistor Trd receives the control voltage Vcs2 held in Cs2 which is one of the first and second capacitors at the gate G, and supplies the drive current Ids flowing between the source (S) and the drain (D) to the light emitting element EL. To emit light. Further, the control unit has a correcting means composed of the switching transistors Tr2 and Tr5. After obtaining the above-mentioned difference, the control unit detects the threshold voltage Vth of the driving transistor Trd, and this is detected by the other of the first and second capacitors. The threshold voltage Vth held in a certain pixel capacitor Cs1 is added to the control voltage Vcs2 held in Cs2 which is one of the first and second capacitors. Thereby, the influence of the threshold voltage Vth can be canceled from the drive current Ids.

1 is a circuit diagram illustrating a first embodiment of a pixel circuit according to the present invention. FIG. 2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 1. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a circuit diagram which shows 2nd Embodiment of the pixel circuit concerning this invention. 9 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 8. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a whole block diagram which shows an example of the conventional display apparatus. FIG. 16 is a circuit diagram illustrating a configuration of a pixel circuit included in the conventional display device illustrated in FIG. 15. It is a schematic diagram which shows an example of the screen of the conventional display apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel circuit, 3 ... Current driver, 4 ... Write scanner, 5 ... Drive scanner, 7 ... Correction scanner, Trd ... Drive transistor, Tr1 ... switching transistor, Tr2 ... switching transistor, Tr3 ... switching transistor, Tr4 ... switching transistor, Tr5 ... switching transistor, Tr6 ... switching transistor, Tr7 ... switching transistor, Tr8 ... Switching transistor, EL ... Light emitting element, Cs1 ... Pixel capacitance, Cs2 ... Pixel capacitance, Cs3 ... Pixel capacitance

Claims (12)

The signal line through which the signal current flows and the scanning line that supplies the control signal are arranged at the intersection,
A pixel circuit comprising: a light emitting element; a driving transistor that supplies a driving current to the light emitting element; and a control unit that operates according to the control signal and controls the driving current of the driving transistor based on the signal current. ,
The control unit passes a signal current flowing through the signal line through the drive transistor, and then samples a signal voltage generated at the gate into a first capacitor;
Second sampling means for passing a predetermined reference current flowing through the signal line before and after the signal current through the driving transistor and sampling a reference voltage generated at the gate at that time into a second capacitor;
A first capacitor that samples the signal voltage and a second capacitor that samples the reference voltage are connected to each other to obtain a difference, and the obtained difference is held as a control voltage in one of the first and second capacitors. Difference means to
The driving transistor receives the control voltage held in one of the first and second capacitors at the gate and supplies a driving current flowing between the source and the drain to the light emitting element to emit light. Pixel circuit.   The signal voltage and the reference voltage sampled by each of the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element decreases and when the difference is large, the light emission amount increases. 2. The pixel circuit according to claim 1, wherein the absolute levels of the signal current and the reference current are set so as to enable sampling even when the relative difference between them is small.   The controller detects the threshold voltage of the driving transistor before obtaining the difference and holds it in a third capacitor, and then holds the held threshold voltage in one of the first or second capacitor. 2. The pixel circuit according to claim 1, further comprising correction means for adding to the control voltage, wherein the influence of the threshold voltage is canceled from the drive current. The control unit detects the threshold voltage of the driving transistor after obtaining the difference, holds the detected threshold voltage on the other side of the first or second capacitor, and holds the held threshold voltage on the first or second level. 2. The pixel circuit according to claim 1, further comprising correction means for adding to the control voltage held in one of the capacitors, and canceling the influence of the threshold voltage from the drive current.
Pixel circuit.   The pixel circuit according to claim 1, wherein the control unit uses a first capacitor and a second capacitor having the same capacitance value. It consists of a pixel array part, a driver part, and a scanner part.
The pixel array section is composed of a column-shaped signal line, a row-shaped scanning line, and a matrix-shaped pixel circuit arranged at a portion where both intersect.
The driver section sends a signal current to each signal line,
The scanner unit supplies a control signal to each scanning line,
Each pixel circuit includes a light emitting element, a driving transistor that supplies a driving current to the light emitting element, an in-pixel control unit that operates according to the control signal and controls the driving current of the driving transistor based on the signal current, A display device comprising:
The in-pixel control unit passes a signal current flowing through the signal line through the driving transistor, and then samples a signal voltage generated at the gate into a first capacitor;
Second sampling means for passing a predetermined reference current flowing through the signal line before and after the signal current through the driving transistor and sampling a reference voltage generated at the gate at that time into a second capacitor;
A first capacitor that samples the signal voltage and a second capacitor that samples the reference voltage are connected to each other to obtain a difference, and the obtained difference is held as a control voltage in one of the first and second capacitors. Difference means to
The driving transistor receives the control voltage held in one of the first and second capacitors at the gate and supplies a driving current flowing between the source and the drain to the light emitting element to emit light. Display device.   The signal voltage and the reference voltage sampled by each of the first and second sampling means are such that when the relative difference between them is small, the light emission amount of the light emitting element decreases and when the difference is large, the light emission amount increases. 7. The display device according to claim 6, wherein the absolute levels of the signal current and the reference current are set large so as to enable sampling even when the relative difference between them is small.   The intra-pixel control unit detects the threshold voltage of the driving transistor before obtaining the difference, holds the threshold voltage in a third capacitor, and then stores the held threshold voltage in one of the first and second capacitors. The display device according to claim 6, further comprising a correction unit that adds to the control voltage held in the display, and cancels the influence of the threshold voltage from the drive current.   The intra-pixel control unit detects the threshold voltage of the driving transistor after obtaining the difference, holds the threshold voltage on the other side of the first or second capacitor, and holds the held threshold voltage on the first or second side. 7. The display device according to claim 6, further comprising correction means for adding to the control voltage held in one of the second capacitors, and canceling the influence of the threshold voltage from the drive current.   The display device according to claim 6, wherein the intra-pixel control unit uses a first capacitor and a second capacitor having the same capacitance value. A signal line through which a signal current flows and a scanning line that supplies a control signal are arranged at a crossing portion, and a light emitting element, a driving transistor that supplies a driving current to the light emitting element, and a signal that operates according to the control signal A pixel circuit driving method comprising a control unit that controls a driving current of the driving transistor based on a current,
A first sampling procedure for passing a signal current flowing through the signal line through the drive transistor and sampling a signal voltage generated at the gate at that time into a first capacitor;
A second sampling procedure in which a predetermined reference current flowing in the signal line before and after the signal current is passed through the driving transistor and a reference voltage generated at the gate at that time is sampled in a second capacitor;
A first capacitor that samples the signal voltage and a second capacitor that samples the reference voltage are connected to each other to obtain a difference, and the obtained difference is held as a control voltage in one of the first and second capacitors. Difference procedure to
A method for driving a pixel circuit, comprising: applying a control voltage to the gate of the driving transistor and supplying a driving current flowing between the source and drain to the light emitting element. The pixel array unit is composed of a pixel array unit, a driver unit, and a scanner unit, and the pixel array unit is composed of a column-shaped signal line, a row-shaped scanning line, and a matrix-shaped pixel circuit arranged at a portion where the two intersect. The driver unit supplies a signal current to each signal line, the scanner unit supplies a control signal to each scanning line, and each pixel circuit includes a light emitting element and a driving transistor that supplies a driving current to the light emitting element. And a display device driving method for controlling the driving current of the driving transistor based on the signal current in response to the control signal,
A first sampling procedure for passing a signal current flowing through the signal line through the drive transistor and sampling a signal voltage generated at the gate at that time into a first capacitor;
A second sampling procedure in which a predetermined reference current flowing in the signal line before and after the signal current is passed through the driving transistor and a reference voltage generated at the gate at that time is sampled in a second capacitor;
A first capacitor that samples the signal voltage and a second capacitor that samples the reference voltage are connected to each other to obtain a difference, and the obtained difference is held as a control voltage in one of the first and second capacitors. Difference procedure to
A driving method of a display device, comprising: applying a light emitting procedure for applying the control voltage to the gate of the driving transistor and supplying a driving current flowing between the source and the drain to the light emitting element.

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