JP2008203656A - Display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which has high uniformity of a screen by suppressing bootstrap loss as much as possible. <P>SOLUTION: A sampling transistor Tr1 writes a video signal in a holding capacitor Cs. A driving transistor Trd supplies a driving current corresponding to the written video signal to a light emitting element EL. The holding capacitor Cs performs bootstrap operation so that the potential at the gate G follows up the potential of the source S to vary when the sampling transistor Tr1 turns off to disconnect the gate G of the driving transistor Trd from a signal line SL. The holding capacitor Cs is composed of a dielectric film in the same layer with a gate insulating film of the sampling transistor Tr1, and the dielectric film is less in thickness than the gate insulating film, thereby suppressing a decrease in bootstrap gain representing the ratio of variation in gate potential to variation in source potential of the driving transistor Trd. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device that performs display by driving a light emitting element arranged for each pixel. Specifically, the present invention relates to a so-called active matrix display device that controls the amount of current that is supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel circuit. The present invention also relates to an electronic apparatus including an active matrix display device.

  In a display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel according to image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A JP 2006-215213 A

  FIG. 17 is a schematic diagram showing an example of a conventional pixel circuit. This pixel circuit is arranged at a portion where a row-shaped scanning line for supplying a control signal and a column-shaped signal line SL for supplying a video signal intersect, and includes a sampling transistor Tr1, a storage capacitor Cs, a drive transistor Trd, and a light emitting element EL. Including. The sampling transistor Tr1 conducts according to the control signal supplied from the scanning line and samples the video signal supplied from the signal line SL. The holding capacitor Cs holds an input voltage corresponding to the sampled video signal. The drive transistor Trd supplies the output current Ids during a predetermined light emission period according to the input voltage held in the holding capacitor Cs. In general, the output current Ids depends on the carrier mobility μ and the threshold voltage Vth in the channel region of the drive transistor Trd. The light emitting element EL emits light with the luminance corresponding to the video signal by the output current supplied from the drive transistor Trd. In the conventional example of FIG. 11, the storage capacitor Cs is connected between the gate G of the drive transistor Trd and the power supply potential Vcc. On the other hand, the light emitting element EL has an anode connected to the source S of the drive transistor Trd and a cathode grounded. The drain of the drive transistor Trd is connected to the power supply potential Vcc.

  The drive transistor Trd receives the input voltage held in the holding capacitor Cs at the gate G, causes the output current Ids to flow between the source S / drain D, and energizes the light emitting element EL. In general, the light emission luminance of the light emitting element EL is proportional to the amount of current supplied. Further, the output current supply amount of the drive transistor Trd is controlled by the gate voltage Vgs, that is, the input voltage written in the storage capacitor Cs. This pixel circuit controls the amount of current supplied to the light emitting element EL by changing the input voltage applied to the gate G of the drive transistor Trd in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  By the way, the drive current Ids required for a light emitting element such as an organic EL element is as large as several μA per pixel, and the drive transistor has a high mobility μ in order to reduce the amplitude of the video signal and reduce the power consumption. A channel type is desirable. The pixel circuit shown in FIG. 11 is a source follower type in which an N-channel transistor is used as the drive transistor Trd.

  However, the pixel circuit shown in FIG. 17 has a problem that the deterioration of the current-voltage characteristic (IV characteristic) of the light emitting element EL cannot be corrected. FIG. 17 is a graph showing the IV characteristics of the light emitting element EL. The horizontal axis represents the anode voltage Va of the light emitting element, and the vertical axis represents the drive current Ids. In the circuit of FIG. 17, the anode potential Va is equal to the source potential of the drive transistor Trd, and the drive current is the drain current Ids flowing through the drive transistor Trd. As shown in the graph of FIG. 18, the light-emitting element such as an organic EL device has a IV characteristic that deteriorates with the passage of time, and a characteristic curve appears with the passage of time. For this reason, in the source follower type pixel circuit shown in FIG. 17, the operating point (source potential) of the drive transistor Trd changes due to the deterioration of the IV characteristics of the light emitting element, and image burn-in remains. End up.

  In order to cope with this conventional problem, a bootstrap type pixel circuit has recently been proposed instead of the source follower type pixel circuit. This bootstrap pixel circuit has a configuration in which a storage capacitor is connected between a gate G and a source S of a drive transistor. In this bootstrap type pixel circuit, the gate voltage Vgs of the drive transistor Trd is always held in the holding capacitor even if the anode potential (that is, the source potential of the drive transistor) fluctuates due to the time-dependent change of the IV characteristic of the light emitting element. Therefore, the output current Ids corresponding to the gate voltage Vgs can be continuously supplied to the light emitting element without being affected by the IV characteristics of the light emitting element EL. As a result, even if the IV characteristics of the light emitting element are deteriorated, there is no deterioration in screen brightness or image quality such as image sticking.

  In the pixel circuit, in addition to fluctuations in the IV characteristics of the light emitting elements, the characteristics of the drive transistors Trd themselves vary depending on the individual pixels. Actually, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon or amorphous silicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. In view of this, a pixel circuit incorporating a function of canceling variations in the threshold voltage of the drive transistor has been developed, and is disclosed in, for example, Patent Document 3 described above.

  As described above, when the sampling transistor is turned off and the gate of the drive transistor is disconnected from the signal line, the bootstrap type pixel circuit follows the source potential of the drive transistor so that the gate potential fluctuates. Perform the action. Here, the ratio of the fluctuation of the gate potential to the fluctuation of the source potential is called a bootstrap gain. Ideally, when the bootstrap operation is performed completely, the source potential and the gate potential fluctuate upward by the same amount, so that the bootstrap gain is 1. However, in reality, the bootstrap gain does not become 1 due to the influence of the parasitic capacitance included in the pixel circuit, and there is a loss. Hereinafter, this bootstrap gain loss may be referred to as bootstrap gain loss or bootstrap loss.

  Factors that determine the magnitude of the bootstrap loss include the threshold voltage of the drive transistor Trd in addition to the parasitic capacitance. As described above, the threshold voltage varies among individual pixels. Therefore, the variation of the threshold voltage Vth itself can be removed by the function of canceling the threshold voltage (threshold voltage correction function), but the influence of the variation of the threshold voltage Vth remaining in the bootstrap loss cannot be canceled. Therefore, if the bootstrap loss is large to some extent, the influence of the variation in the threshold voltage Vth appears, and there is a problem that the light emission luminance varies from pixel to pixel and the uniformity of the screen is impaired.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device with high screen uniformity while suppressing bootstrap loss as much as possible. The following measures were taken to achieve this objective. That is, the present invention includes a pixel array unit and a driving unit that drives the pixel array unit to display an image, and the pixel array unit includes a row-shaped scanning line, a column-shaped signal line, each scanning line, and each signal line. And a matrix-like pixel disposed at a portion where the pixel and the pixel cross each other, and the driving unit supplies a control signal to each scanning line and a video signal to each signal line, and each pixel includes at least a sampling transistor and The sampling transistor has a gate connected to the scan line, a source and a drain connected between the signal line and the gate of the drive transistor, and a drive transistor, a storage capacitor, and a light emitting element. The drive transistor has a drain connected to the power supply line, a source connected to the light emitting element, and the storage capacitor connected between the gate and the source of the drive transistor. The sampling transistor is turned on in response to a control signal supplied from the scanning line and writes a video signal supplied from the signal line to the storage capacitor, and the drive transistor is connected to the storage capacitor. A driving current corresponding to the video signal written to the light-emitting element is supplied to the light-emitting element, and the storage capacitor is connected to the drive transistor when the sampling transistor is turned off and the gate of the drive transistor is disconnected from the signal line. A bootstrap operation is performed so that the gate potential fluctuates following the source potential, and the storage capacitor is formed of a dielectric film in the same layer as the gate insulating film of the sampling transistor, and the dielectric film Has a thickness smaller than that of the gate insulating film, and the gate potential with respect to the variation of the source potential is reduced. Characterized in that to suppress a decrease in the bootstrap gain representing the ratio of the dynamic content.

  Preferably, the pixel includes threshold voltage correction means for writing a voltage corresponding to a threshold voltage of the drive transistor to the storage capacitor prior to writing of the video signal. In addition, when writing the video signal, the pixel negatively feeds back a driving current flowing through the drive transistor to the storage capacitor, and mobility correction means for applying correction according to the mobility of the drive transistor to the video signal. Including.

  The loss of the bootstrap gain (that is, the bootstrap loss) is determined by the parasitic capacitance and the holding capacitance included in the pixel circuit. In principle, the larger the parasitic capacitance, the larger the bootstrap loss. On the other hand, the larger the retention capacitance, the smaller the bootstrap loss, and the screen uniformity improves. Here, the parasitic capacitance includes a gate capacitance of a transistor included in the pixel circuit. On the other hand, the storage capacitor is usually composed of a dielectric film in the same layer as the gate insulating film. Therefore, the thickness of the dielectric film is reduced by, for example, selective etching compared to the gate insulating film. This increases the storage capacity compared to the gate parasitic capacity and eliminates the bootstrap loss as much as possible. Even if the threshold voltage of the drive transistor varies, the uniformity of the screen is hardly affected. Can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, this display device basically includes a pixel array section 1, a scanner section, and a signal section. The pixel array unit 1 includes a first scanning line WS, a second scanning line AZ1, a third scanning line AZ2, and a fourth scanning line DS arranged in a row, a signal line SL arranged in a column, and these scans. A matrix pixel circuit 2 connected to the lines WS, AZ1, AZ2, DS and the signal line SL, and a plurality of first potential Vss1, second potential Vss2 and third potential Vcc necessary for the operation of each pixel circuit 2 Power line. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72, and the first scanning line WS, the fourth scanning line DS, the second scanning line AZ1, and the third scanning, respectively. A control signal is supplied to the line AZ2 to sequentially scan the pixel circuit for each row.

  FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit incorporated in the display device illustrated in FIG. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a storage capacitor Cs, and a light emitting element EL. Including. The sampling transistor Tr1 conducts according to a control signal supplied from the first scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the holding capacitor Cs. The storage capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 is turned on in response to a control signal supplied from the second scanning line AZ1 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vss1. The second switching transistor Tr3 is turned on according to a control signal supplied from the third scanning line AZ2 prior to the sampling period, and sets the source S of the drive transistor Trd to the second potential Vss2. The third switching transistor Tr4 is turned on in response to a control signal supplied from the fourth scanning line DS prior to the sampling period to connect the drive transistor Trd to the third potential Vcc, and thus to the threshold voltage Vth of the drive transistor Trd. The corresponding voltage is held in the holding capacitor Cs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 conducts again in response to the control signal supplied from the fourth scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vcc, and causes the output current Ids to flow through the light emitting element EL. .

  As is apparent from the above description, the pixel circuit 2 includes five transistors Tr1 to Tr4 and Trd, one holding capacitor Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 3 is a schematic diagram in which only the pixel circuit 2 is extracted from the display device shown in FIG. In order to facilitate understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. Hereinafter, the operation of the pixel circuit 2 will be described with reference to FIG.

  FIG. 4 is a timing chart of the pixel circuit shown in FIG. The operation of the pixel circuit shown in FIG. 3 will be specifically described with reference to FIG. FIG. 4 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2 and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level, and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 4, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr2 and Tr3 are turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the storage capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the holding capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the video signal Vsig is written in the storage capacitor Cs. The storage capacitor Cs is sufficiently smaller than the equivalent capacitor Coled of the light emitting element EL. As a result, most of the video signal Vsig is written in the storage capacitor Cs. To be precise, for Vss1. The difference Vsig−Vss1 of Vsig is written to the storage capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. In the following description, assuming Vss1 = 0V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T6 when the control signal WS returns to the low level. That is, the timing T5-T6 corresponds to the sampling period.

  Subsequently, at timing T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. At the previous timing T6, the control signal WS becomes low level, and the sampling transistor Tr1 is already turned off. For this reason, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased with the switching transistor Tr4 being turned on, and is increased with the source potential (S). In the pixel circuit of this embodiment, the source of the drive transistor Trd and the anode of the light emitting element EL are connected. Therefore, the source potential (S) of the drive transistor Trd is also the anode potential Va of the light emitting element EL. The timing chart of FIG. 4 also shows the anode potential Va of the light emitting element EL. This light emission period ends at the timing T8 before entering the next field.

As described above, at the timing T7, the gate potential (G) of the drive transistor Trd can be increased, and the source potential (S) is increased in conjunction with this. This is the bootstrap operation. During this bootstrap operation, the gate / source voltage Vgs held in the holding capacitor Cs maintains the value of (Vsig + Vth). In other words, this bootstrap operation enables the anode potential Va of the light emitting element EL to be increased while keeping Vgs held in the holding capacitor Cs constant. As the source potential (S) of the drive transistor increases, that is, the anode potential Va of the light emitting element EL increases, the reverse bias state of the light emitting element EL is canceled. Start. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = k · μ (Vgs−Vth) ² = K · μ (Vsig) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. In addition, the pixel circuit always maintains the gate voltage Vgs constant without depending on the source potential of the drive transistor, that is, the anode potential Va of the light emitting element. Due to this bootstrap function, the pixel circuit can stably maintain the screen luminance without being affected by the temporal variation of the IV characteristic of the light emitting element EL.

  As described above, the pixel circuit incorporating the bootstrap function and the threshold voltage correction function still has problems to be solved. This point will be briefly described with reference to FIG. 5 before describing the present invention. FIG. 5 is a schematic view of one pixel circuit extracted from the display device shown in FIG. Although it is basically the same as the schematic diagram of the pixel circuit shown in FIG. 3, a parasitic capacitance Cp is also added for convenience of explanation. A thin film transistor has a parasitic capacitance Cp between its gate and source. In this pixel circuit, in particular, the parasitic capacitance Cp of the sampling transistor Tr1 and the switching transistor Tr2 adversely affects the operation of the drive transistor Trd. Specifically, a voltage loss occurs in the bootstrap operation due to the parasitic capacitance Cp of these transistors Tr1 and Tr2, and this is entangled with variations in the threshold voltage Vth of the drive transistor Trd, resulting in a luminance difference on the screen. In an ideal bootstrap operation, the increase in the source potential of the drive transistor and the increase in the gate potential are completely the same, and the gate voltage Vgs is kept constant. In other words, the bootstrap gain is ideally 1. However, in reality, a loss occurs in the bootstrap gain due to the influence of the parasitic capacitance Cp, and the increase in the gate potential is less than that in the source potential. The problem here is that this bootstrap gain loss is not constant between pixels but varies due to the influence of the threshold voltage Vth of the drive transistor of each pixel circuit. Due to the variation in the bootstrap gain loss, a luminance difference is generated between pixels on the screen, and uniformity is impaired.

The bootstrap gain loss will be described in detail with reference to FIG. The gate-source voltage Vgs of the drive transistor Trd after the signal voltage Vsig is written is Vgs = Vsig−Vss1 + Vth because Vth correction is performed in advance. Next, when the sampling transistor Tr1 is turned off and then the switching transistor Tr4 is turned on, the drive transistor Trd is connected to the power supply Vcc, and the drain current Ids flows through the light emitting element EL. At this time, a voltage corresponding to the drain current Ids is applied to the anode terminal of the light emitting element EL. In the timing chart of FIG. 4, the anode voltage (source voltage of the drive transistor) at this time is represented by Va. Therefore, during the light emission operation, the source voltage of the drive transistor increases by Va−Vss1 + Vth. On the other hand, since the gate voltage of the drive transistor Trd has a parasitic capacitance Cp, the increase is (Va−Vss1 + Vth) × Cs / (Cs + Cp). As described above, Vgs after the bootstrap operation is expressed by Equation 3 below. The drain current Ids corresponding to this Vgs is given by the following equation 4. However, in Equation 3 below, Vss1 is set to 0 V for simplicity.
Vgs = Vsig−Vss1 + Vth−
(Va−Vss1 + Vth) · Cp / (Cs + Cp)
= Vsig + Vth- (Va + Vth) .Cp / (Cs + Cp) (3)

Ids = k · μ (Vsig− (Va + Vth) · Cp / (Cs + Cp)) ² · (4)

  The above Equation 3 representing Vgs after bootstrapping includes a bootstrap gain loss term in the three items, and is smaller than an ideal value. Looking at this bootstrap gain loss term, variables Va and Vth are included with Cp / (Cs + Cp) as a coefficient part. In general, there is not much variation in light emitting element characteristics between pixels, and therefore variation in anode potential Va can be ignored. On the other hand, the threshold voltage Vth of the drive transistor varies from pixel to pixel. For this reason, the bootstrap gain loss term varies from pixel to pixel, and the light emission luminance is not uniform between pixels.

  Generally, the holding capacitor Cs is about 200 fF, and the parasitic capacitance Cp is about 5 fF. Therefore, the bootstrap gain loss Cp / (Cs + Cp) is about 2.5%. For this reason, a variation of about 2.5% of the Vth variation is included in the light emission current Ids expressed by Equation 4. For example, if the minimum maximum width of Vth variation of the drive transistor Trd is 2V, the Vgs variation due to the bootstrap gain loss is 50 mV. Here, when white display where the screen uniformity is most conspicuous is Vgs = 2V, the luminance variation due to the difference of 50 mV is about 5%, which is visually observed. This reduces the yield of the panel. In general, variations in the drive transistor Vth are distributed in a streak pattern on the screen in the manufacturing process. Therefore, streaky unevenness occurs on the screen and the yield of the panel decreases.

  It is difficult to reduce the variation of the threshold voltage Vth of the drive transistor in terms of device structure and manufacturing process. Therefore, it is inevitable that a factor of Vth variation is included in the bootstrap loss that causes Vgs variation. In this case, by reducing the bootstrap loss as much as possible, the influence of Vth variation can be reduced accordingly. As described above, the bootstrap loss is determined by Cp / (Cs + Cp). As apparent from this equation, the bootstrap loss can be reduced by increasing the storage capacitor Cs. For example, if the conventional storage capacitor Cs is about 200 fF and the capacity is increased to 400 fF, the bootstrap loss can be suppressed to about half of the conventional 2.5%. Therefore, the luminance unevenness due to Vth variation is about 2.5%, which is about 5% of the conventional one. In general, the luminance difference visually observed with a uniformity of white gradation is 2 to 3%. Therefore, as described above, when the storage capacitor Cs is at least doubled compared to the conventional case, the luminance variation due to the bootstrap loss is hardly visible. It is possible. Thereby, the manufacturing yield of the panel can be improved.

  The storage capacitor Cs of the normal pixel circuit is composed of a dielectric film that is the same layer as the gate insulating film of the sampling transistor Tr1. As a feature of the present invention, the dielectric film has a smaller thickness than the gate insulating film, and the capacitance value of the storage capacitor Cs is increased accordingly. As a result, a decrease in bootstrap gain can be suppressed, leading to improvement in uniformity. As shown in FIG. 5, the parasitic capacitance Cp that adversely affects the bootstrap gain is the gate capacitance of the sampling transistor Tr1 and the gate capacitance of the switching transistor Tr2. On the other hand, since the switching transistors Tr3 and Tr4 are not directly connected to the gate of the drive transistor Trd, the parasitic capacitance is not a problem. Therefore, the gate insulating films of the switching transistors Tr3 and Tr4 may be made as thin as the dielectric film of the storage capacitor Cs. Of course, like the sampling transistor Tr1 and the switching transistor Tr2, the gate insulating films of the switching transistors Tr3 and Tr4 may remain thick. In some cases, an auxiliary capacitor Csub may be connected in parallel with the light emitting element EL in order to assist the equivalent capacitor Coled of the light emitting element EL. In this case, the auxiliary capacitor Csub may have a thin dielectric film like the storage capacitor Cs. Alternatively, since the auxiliary capacitor Csub does not participate in the bootstrap gain, the thickness of the dielectric film may remain large.

  FIG. 6 is a schematic cross-sectional view showing the device structure of a pixel included in the display device according to the present invention shown in FIGS. 1 and 2. In order to facilitate understanding, the portions of the sampling transistor Tr1 and the storage capacitor Cs are shown. Although not shown, a laminated light emitting element in which an organic EL light emitting layer is sandwiched between an anode electrode and a cathode electrode is disposed on the transistor Tr1 and the storage capacitor Cs.

  Next, a method for manufacturing the sampling transistor Tr1 and the storage capacitor Cs will be described with reference to FIG. First, the gate electrode 41 of the sampling transistor Tr1 is formed on the glass substrate 40. At the same time, the lower electrode 41a of the storage capacitor Cs is formed. Although not shown, the lower electrode 41a is connected to the source S of the drive transistor Trd. As a specific process, a refractory metal such as Mo that becomes the gate electrode 41 and the lower electrode 41a is formed to a thickness of about 100 nm by sputtering or the like. The refractory metal is patterned into a predetermined shape by lithography and dry etching or wet etching, and processed into the gate electrode 41 of the sampling transistor Tr1 and the lower electrode 41a of the storage capacitor Cs.

  Further, a silicon nitride film 42 to be a gate insulating film is formed to a thickness of about 100 nm by low pressure chemical vapor deposition (LP-CVD), plasma CVD, sputtering, or the like. Further, a silicon oxide film 43 serving as a gate insulating film is similarly formed to about 100 nm by LP-CVD, plasma CVD, sputtering, or the like. Here, the silicon oxide film 43 is selectively removed from the lower electrode 41a of the storage capacitor Cs by dry etching or wet etching. As a result, the gate insulating film of the sampling transistor Tr1 has a two-layer structure of the silicon nitride film 42 and the silicon oxide film 43, and the thickness is about 200 nm. On the other hand, the dielectric film of the storage capacitor Cs consists only of the silicon nitride film 42, and its thickness is about 100 nm. In this way, the gate insulating film has a two-layer structure, and by selectively removing only one layer from the lower electrode 41a of the storage capacitor Cs, the dielectric film can be made thinner. However, the present invention is not limited to this, and the thickness may be reduced by selectively etching a part of the thickness of the single-layer gate insulating film.

  Further, a semiconductor thin film 44 serving as an active layer of the thin film transistor is deposited with a thickness of about 40 nm, for example, so as to overlap the gate insulating film and the dielectric film. In this example, amorphous silicon (amorphous silicon) is deposited as the semiconductor thin film 44. Instead, polycrystalline silicon (polysilicon) having a relatively small grain size may be deposited. The deposited semiconductor thin film 44 is patterned into a predetermined shape to form an element region of the sampling transistor Tr1. At this time, a part of the semiconductor thin film 44 extends to the upper part of the lower electrode 41a of the storage capacitor Cs and becomes the upper electrode 44a of the storage capacitor Cs. Thereafter, pulsed laser light is irradiated with an excimer laser to convert the semiconductor thin film 44 made of amorphous silicon or polycrystalline silicon having a relatively small particle size into polycrystalline silicon having a relatively large particle size. As a result, the grain size of the polycrystalline silicon is expanded to about 300 to 400 nm, for example. Subsequently, impurities are implanted into the polycrystalline semiconductor thin film 44 through a predetermined mask to form a source region S and a drain region D. A portion where impurities are not implanted by the mask is left as a channel region CH. This channel region CH is substantially aligned with the gate electrode 41. As is apparent from the figure, the drain region D of the sampling transistor Tr1 extends as it is to form the upper electrode 44a of the storage capacitor Cs.

  An insulating film 45 is formed so as to cover the sampling transistor Tr1 and the storage capacitor Cs thus created. For example, about 300 nm of silicon oxide is deposited by CVD. A contact hole communicating with the source region S and the drain region D is opened in the insulating film 45 by etching. A metal film made of aluminum or a compound of aluminum and silicon is formed on the insulating film 45 by a sputtering method, for example, to a thickness of about 500 nm. The deposited metal is patterned with a predetermined mask and processed into wirings 46S and 46D of the sampling transistor Tr1. A wiring 46S connected to the source S of the sampling transistor Tr1 is connected to a signal wiring (not shown). On the other hand, the wiring 46D connected to the drain region D of the sampling transistor Tr1 is connected to the gate G of the drive transistor Trd (not shown).

  FIG. 7 is a schematic cross-sectional view showing another example of the device structure of a pixel included in the display device according to the present invention. Although the device structure shown in FIG. 6 uses a polycrystalline silicon thin film transistor, this example is an example of an amorphous silicon thin film transistor. First, a gate electrode 51 made of a metal having a two-layer structure of aluminum (film thickness of 300 nm) to which about 1% neodymium is added and molybdenum (film thickness of 50 nm) as an upper layer is patterned on the glass substrate 50. At the same time, the lower electrode 51a of the storage capacitor Cs is patterned with the same metal material.

  Thereafter, a silicon nitride film 52 is formed to a thickness of about 100 nm by plasma CVD, and a silicon oxide film 53 is subsequently formed to a thickness of about 100 nm. As a result, a gate insulating film having a two-layer structure composed of the silicon nitride film 52 and the silicon oxide film 53 formed thereon is obtained. Thereafter, the silicon oxide film 53 is removed from the lower electrode 51a of the storage capacitor Cs, and the dielectric film is thinned. Subsequently, a channel layer 54 made of amorphous silicon (amorphous silicon) is formed on the silicon oxide film 53 with a film thickness of 50 nm, for example. Subsequent to the formation of the channel layer 54, a heat treatment is performed to remove hydrogen in the channel layer 54. Subsequent to this heat treatment, hydrogenation treatment is performed on the surface of the channel layer 54. As this hydrogenation treatment, hydrogen plasma treatment is performed in which the channel layer 54 is exposed to hydrogen gas plasma. Subsequently, a protective stopper layer 57 made of silicon nitride is formed to a thickness of 200 nm on the channel layer 54 by plasma CVD. Subsequently, through a photolithography process and an etching process, patterning is performed so that the protective stopper layer 57 is left only immediately above the gate electrode 51.

  Thereafter, an n-type amorphous silicon film 58 containing phosphorus is formed on the channel layer 54 so as to cover the patterned protective stopper layer 57 to a thickness of about 50 nm. Thereafter, the n-type amorphous silicon film 58 and the underlying channel layer 54 are patterned in an island shape through photolithography and etching processes. Subsequently, a source / drain electrode film 56 is formed by sputtering while covering the n-type amorphous silicon film 58. Thereafter, the source / drain electrode film 56 is patterned to form the source electrode 56S and the drain electrode 56D. At this time, the drain electrode 56D extends to the upper part of the lower electrode 51a of the storage capacitor Cs, and serves as the upper electrode 56a of the storage capacitor Cs. Through the above steps, the amorphous silicon thin film transistor Tr1 in which the channel layer 54 is protected by the protective stopper layer 57 is formed. The thin film transistor Tr1 is a bottom gate type thin film transistor having a channel layer 54 made of amorphous silicon on a gate insulating film having a silicon oxide film 53 as a surface layer. At this time, a storage capacitor Cs is also formed. As is apparent from the figure, the thickness of the dielectric film of the storage capacitor Cs is made thinner than the thickness of the gate insulating film of the sampling transistor Tr1.

  FIG. 8 is a timing chart showing another example of a method for driving the display device shown in FIGS. The notation similar to the timing chart shown in FIG. 4 is employed to facilitate understanding. The difference from the driving method shown in FIG. 4 is that this driving method performs a mobility correction operation in addition to the threshold voltage correction operation and the bootstrap operation. Hereinafter, the driving method shown in FIG. 8 will be described in detail. At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr2 and Tr3 are turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the storage capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the holding capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the video signal Vsig is written in the storage capacitor Cs. The storage capacitor Cs is sufficiently smaller than the equivalent capacitor Coled of the light emitting element EL. As a result, most of the video signal Vsig is written in the storage capacitor Cs. To be precise, for Vss1. The difference Vsig−Vss1 of Vsig is written to the storage capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. In the following description, assuming Vss1 = 0V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in this example, the mobility correction is performed in a period T6-T7 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written to the capacitor C = Cs + Coled obtained by combining both the storage capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 4, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the holding capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the holding capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 5 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 5
In the above formula 5, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 5 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 5 just. Therefore, the drain current Ids substantially depends only on the video signal Vsig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  FIG. 9 is a circuit diagram showing a state of the pixel circuit 2 in the mobility correction period T6-T7. As shown in the figure, in the mobility correction period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are on, while the remaining switching transistors Tr2 and Tr3 are off. In this state, the source potential (S) of the drive transistor Tr4 is Vss1-Vth. This source potential (S) is also the anode potential of the light emitting element EL. By setting Vss1−Vth <VthEL as described above, the light emitting element EL is placed in a reverse bias state, and exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd flows into the combined capacitance C = Cs + Coled of the storage capacitor Cs and the equivalent capacitance Coled of the light emitting element EL. In other words, a part of the drain current Ids is negatively fed back to the storage capacitor Cs, and the mobility is corrected.

  FIG. 10 is a graph of the transistor characteristic equation 5 described above, where Ids is plotted on the vertical axis and Vsig is plotted on the horizontal axis. The characteristic formula 5 is also shown below the graph. In the graph of FIG. 10, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example, when the signal potential Vsig of the video signal of the same level is written in both the pixels 1 and 2, the output current Ids 1 ′ flowing through the pixel 1 having the high mobility μ is equal to the mobility μ unless the mobility is corrected. A large difference is generated as compared with the output current Ids2 'flowing through the small pixel 2. In this way, a large difference occurs between the output currents Ids due to the variation in the mobility μ, so that unevenness occurs and the uniformity of the screen is impaired.

  Therefore, in this embodiment, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As apparent from the previous transistor characteristic equation 1, the drain current Ids increases when the mobility is large. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 10, the negative feedback amount ΔV1 of the pixel 1 having a high mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 having a low mobility. Therefore, the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown in the figure, when ΔV1 is corrected in the pixel 1 having a high mobility μ, the output current greatly decreases from Ids1 ′ to Ids1. On the other hand, since the correction amount ΔV2 of the pixel 2 having the low mobility μ is small, the output current Ids2 ′ does not decrease so much to Ids2. As a result, Ids1 and Ids2 are substantially equal, and the variation in mobility is cancelled. Since the cancellation of the variation in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen becomes extremely high. In summary, when there are pixels 1 and 2 having different mobility, the correction amount ΔV1 of the pixel 1 having high mobility is smaller than the correction amount ΔV2 of the pixel 2 having low mobility. That is, as the mobility increases, ΔV increases and the decrease value of Ids increases. As a result, pixel current values having different mobilities are made uniform, and variations in mobility can be corrected.

Hereinafter, the numerical analysis of the mobility correction described above is performed. As shown in FIG. 9, the analysis is performed by taking the source potential of the drive transistor Trd as a variable V in a state where the transistors Tr1 and Tr4 are turned on. Assuming that the source potential (S) of the drive transistor Trd is V, the drain current Ids flowing through the drive transistor Trd is as shown in Equation 6 below.

Further, due to the relationship between the drain current Ids and the capacitance C (= Cs + Coled), Ids = dQ / dt = CdV / dt is established as shown in Equation 7 below.

Both sides are integrated by substituting Equation 6 into Equation 7. Here, the initial state of the source voltage V is -Vth, and the mobility variation correction time (T6-T7) is t. When this differential equation is solved, the pixel current with respect to the mobility correction time t is given by Equation 8 below.

In the pixel circuit configuration shown in FIG. 9, the drive current Ids flows through the light emitting element EL during light emission, and the potential of the source S of the drive transistor Trd increases. The increase width is determined by the IV characteristic of the light emitting element EL with respect to the drive current Ids flowing through the drive transistor Trd. On the other hand, since the potential of the gate G of the drive transistor Trd is connected to the source S via the storage capacitor Cs and is in a high impedance state, the potential of the gate G also rises as the potential of the source S rises. Here, the gate G of the drive transistor Trd has a parasitic capacitance Cp composed of the diffusion capacitance of the sampling transistor Tr1, and the increase ΔVg of the gate potential is smaller than the increase ΔVs of the source potential as shown in Equation 9. End up.
ΔVg = ΔVs × Cs / (Cs + Cp) Equation 9

さらに式１０の結果から駆動電流Ｉｄｓは以下の式１１のようになる。

つまりＶｔｈばらつきがブートストラップゲインによって式１１の右辺に入ってしまい、そのため発光輝度に差が生じてしまう。パネルが高精細化するにつれ、保持容量Ｃｓを十分に取ることが困難になるので、このブートストラップ分のＶｔｈばらつきの割合は大きくなってしまう。そこで本発明は、上述したようにドライブトランジスタＴｒｄのゲートＧとソースＳの間に挿入された保持容量Ｃｓを大きくしている。具体的には誘電体膜を薄膜化している。一方でドライブトランジスタＴｒｄのゲートＧに接続しているサンプリングトランジスタＴｒ１やスイッチングトランジスタＴｒ２はそのゲート絶縁膜を薄膜化しない。これによりブートストラップゲインを向上することが出来、ブートストラップロスによる駆動トランジスタＴｒｄのＶｔｈばらつきに起因する画質低下を抑制し、高いユニフォーミティを得ることが出来る。 The difference between ΔVs and ΔVg falls in the voltage term of Equation 8. Here, since ΔVs is determined by Voled at the time of light emission and Vth of the drive transistor Trd, this difference term is expressed by Equation 10 below.

Further, from the result of Expression 10, the drive current Ids is expressed by Expression 11 below.

In other words, the Vth variation enters the right side of Equation 11 due to the bootstrap gain, which causes a difference in light emission luminance. As the panel becomes higher in definition, it becomes difficult to obtain a sufficient storage capacitor Cs, so that the ratio of Vth variation for this bootstrap increases. Therefore, according to the present invention, the storage capacitor Cs inserted between the gate G and the source S of the drive transistor Trd is increased as described above. Specifically, the dielectric film is thinned. On the other hand, the sampling transistor Tr1 and the switching transistor Tr2 connected to the gate G of the drive transistor Trd do not thin the gate insulating film. As a result, the bootstrap gain can be improved, the deterioration of the image quality due to the Vth variation of the drive transistor Trd due to the bootstrap loss can be suppressed, and a high uniformity can be obtained.

  The display device according to the present invention includes a flat module shape as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all fields which display the image signal produced | generated in the inside as an image or an image | video. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 12 shows a television to which the present invention is applied, which includes a video display screen 11 composed of a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 13 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 14 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters and the like, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 15 shows a portable terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 16 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

1 is a block diagram showing an overall configuration of a display device according to the present invention. It is a circuit diagram which shows the pixel formed in the display apparatus shown in FIG. FIG. 3 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 2. It is a timing chart with which it uses for operation | movement description of the display apparatus shown in FIG.2 and FIG.3. It is a typical circuit diagram with which it uses for description of the display apparatus concerning this invention. It is sectional drawing which shows the device structure of the pixel contained in the display apparatus concerning this invention. It is a typical sectional view showing other examples of device structure similarly. FIG. 4 is another timing chart for explaining the operation of the display device shown in FIGS. 2 and 3. FIG. It is a schematic diagram with which it uses for description of the display apparatus concerning this invention. It is a graph with which it uses for description of the display apparatus concerning this invention similarly. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention. It is a circuit diagram which shows an example of the conventional pixel circuit. It is a graph which shows the current-voltage characteristic of a light emitting element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel circuit, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 40 ... Glass substrate, 41 ... Gate electrode, 41a ... lower electrode, 42 ... silicon oxide film, 43 ... silicon nitride film, 44 ... semiconductor thin film, 44a ... upper electrode, 45 ... insulating film, 71 ... First correction scanner, 72 ... second correction scanner, Tr1 ... sampling transistor, Tr2 ... first switching transistor, Tr3 ... second switching transistor, Tr4 ... third switching transistor, Trd: drive transistor, Cs: holding capacitor, EL: light emitting element, Vss1: first power supply potential, Vss2: second power supply potential, Vcc: third power supply Potential, WS · · · first scan line, AZ1 · · · second scan line, AZ2 · · · third scan line, DS · · · fourth scan lines

Claims (4)

Including a pixel array unit and a driving unit that drives the pixel array unit to display an image;
The pixel array unit includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect,
The driving unit supplies a control signal to each scanning line and a video signal to each signal line,
Each pixel includes at least a sampling transistor, a drive transistor, a storage capacitor, and a light emitting element,
The sampling transistor has a gate connected to the scanning line, a source and a drain connected between the signal line and the gate of the drive transistor,
The drive transistor has a drain connected to a power supply line, a source connected to the light emitting element,
The storage capacitor is a display device connected between a gate and a source of the drive transistor,
The sampling transistor is turned on in response to a control signal supplied from the scanning line and writes a video signal supplied from the signal line to the storage capacitor.
The drive transistor supplies a drive current corresponding to the video signal written in the storage capacitor to the light emitting element,
The holding capacitor performs a bootstrap operation so that when the sampling transistor is turned off and the gate of the drive transistor is disconnected from the signal line, the gate potential changes following the source potential of the drive transistor. ,
The storage capacitor is composed of a dielectric film in the same layer as the gate insulating film of the sampling transistor,
The dielectric film has a thickness smaller than that of the gate insulating film, and suppresses a decrease in bootstrap gain indicating a ratio of the gate potential variation to the source potential variation. apparatus.   2. The display device according to claim 1, wherein the pixel includes threshold voltage correction means for writing a voltage corresponding to a threshold voltage of the drive transistor to the storage capacitor prior to writing of the video signal.   The pixel includes a mobility correction unit that negatively feeds back a drive current flowing through the drive transistor to the storage capacitor when the video signal is written, and applies a correction corresponding to the mobility of the drive transistor to the video signal. The display device according to claim 1.   An electronic device comprising the display device according to claim 1.

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