JP2003344873A - Bootstrap circuit and planar display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent parasitic capacitance from being formed across a control electrode of a transistor and a counter electrode placed opposite thereto. <P>SOLUTION: A source electrode 53 of a transistor Tr1 is extended up to the position of a gate electrode 51. With this structure, the part of the gate electrode 51 exposed to the counter electrode 14 is covered by the source electrode 53, therefore, the parasitic capacitance Ccom is prevented from being formed across the gate electrode 51 and the counter electrode 14. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bootstrap circuit for setting the potential of an output signal of a transistor to a sufficient level and a flat panel display using the bootstrap circuit.

[0002]

2. Description of the Related Art A flat panel display device represented by a liquid crystal display device is used as a display for various devices because of its thinness, light weight and low power consumption. Above all, an active matrix type liquid crystal display device in which a transistor is arranged for each pixel is spreading as a display for a notebook type personal computer and a portable information terminal. In recent years, a technology has been established for forming a polysilicon thin film transistor having a higher electron mobility than a conventional amorphous silicon thin film transistor used in a liquid crystal display device by a relatively low temperature process, and the transistor used in the liquid crystal display device can be miniaturized. It has become possible. As a result, the pixel portion in which the pixel transistor is arranged at the intersection of the plurality of scanning lines and the plurality of signal lines and the driving circuit for driving the pixel transistor are integrally formed on the glass electrode substrate by the same manufacturing process. Can be formed.

Further, in order to shorten the manufacturing process and realize the cost reduction, the drive circuit and the pixel transistor are replaced by pMO.
It has become possible to use only one of the S and nMOS transistors.

However, when an attempt is made to output a low voltage, the pMOS transistor has its output increased by the threshold voltage Vth of the pMOS transistor, so that it is difficult to output a sufficiently low voltage. On the other hand, nMOS
It is difficult for a transistor to output a sufficiently high voltage. Therefore, a bootstrap circuit is conventionally used to obtain a sufficient level of output.

FIG. 10 is a circuit diagram showing a schematic configuration of a conventional bootstrap circuit. Transistor Tr of the same figure
For example, pMOS transistors are used for 11 and Tr12. The drain of the transistor Tr11 is connected to the input terminal 71, and the source is connected to the output terminal 72. The drain and gate of the transistor Tr12 are connected to the low level power supply voltage VSS, and the source is connected to the gate of the transistor Tr11. In addition, a capacitance C is provided between the output terminal 72 and the gate of the transistor Tr11.
Are connected. Note that here, a conductive path to the gate of the transistor Tr11 is referred to as a node n31.

FIG. 11 is a diagram showing operation waveforms of a conventional bootstrap circuit. First, when the high-level power supply voltage VDD is input to the input terminal 71 as the input signal IN, the transistor Tr12 whose gate is supplied with the power supply voltage VSS is in the ON state.
Through 12, the threshold voltage Vth of the transistor Tr12 is supplied to the node n31 together with the power supply voltage VSS. At this time, since the potential of the node n31 is low level, the transistor Tr11 is in the on state. Therefore, the output terminal 7
A high level input signal IN is applied to the transistor Tr1.
1 and a high level output signal OUT is output.

Next, when the input signal IN of the low level power supply voltage VSS is input to the input terminal 71, the transistor Tr11 remains in the ON state, and thus the output signal OUT is output.
Potential decreases from high level to low level. At this time, since the decrease in the potential of the output signal OUT is transmitted to the node n31 through the capacitor C, the node n3
The potential of 1 also drops by the amount corresponding to the drop of the output signal OUT. Therefore, the potential of the node n31 becomes lower than VSS. Therefore, the transistor Tr11 maintains the ON state because the potential of the gate becomes lower than the potential of the source. On the other hand, the transistor Tr12 is turned off because the gate potential becomes higher than the source potential. Therefore, the low-level input signal IN is output to the output terminal 72, and the sufficiently low-voltage output signal OUT is output.

As described above, the bootstrap circuit transmits the potential change of the output signal OUT from the transistor Tr11 to the gate of the transistor Tr11 via the capacitor C so that the transistor Tr11 can output a sufficiently low voltage. ing.

FIG. 12 is a diagram showing a configuration of a bootstrap circuit in which the capacitor C shown in FIG. 10 is connected between the gate and drain of the transistor Tr11. The bootstrap circuit of this configuration is similar to the circuit of FIG.
A sufficiently low voltage output signal OUT can be output.

[0010]

However, the liquid crystal display device has a structure including a counter substrate (second electrode substrate) made of glass which is arranged so as to face the array substrate (first electrode substrate). A counter electrode that electrically faces the pixel electrodes on the array substrate is formed on the surface of the substrate.

Therefore, in the layout on the substrate of the conventional bootstrap circuit as shown in the plan view of FIG.
As shown in the cross-sectional view of FIG. 14, a parasitic capacitance Ccom is formed between the gate electrode (control electrode) 61 of the transistor on the array substrate and the counter electrode 14 on the counter substrate 16. The equivalent circuit of the bootstrap circuit in this case is as shown in FIG. Transistor Tr11 shown in FIG.
The change in the gate potential of can be expressed by the following equation.

[0012]

[Formula 1] ΔVg = C / (C + Ccom) · ΔVout ··· (Equation 1) where ΔVg: Change in gate potential of the transistor Tr11 C: Bootstrap circuit capacitance Ccom: Parasitic between the gate electrode of the transistor Tr11 and the counter electrode Capacitance ΔVout: Change in potential of output signal OUT When the parasitic capacitance Ccom is formed in this way,
The change in the potential of the output signal OUT is not sufficiently transmitted to the gate of the transistor Tr11. For this reason,
As shown in the operation waveform of No. 6, there is a problem that the fall time of the pulse of the output signal OUT of the bootstrap circuit is delayed.

The present invention has been made in view of the above, and an object of the present invention is to form a parasitic capacitance between a control electrode of a transistor and a counter electrode arranged to face the control electrode of the transistor. It is to provide a bootstrap circuit capable of preventing the above.

[0014]

A bootstrap circuit according to a first aspect of the present invention is a bootstrap circuit in which a capacitance is provided between a control electrode of a transistor and an input electrode or an output electrode of the transistor. It is characterized in that it is extended to the position of the control electrode.

In the present invention, the output electrode of the transistor is extended to the position corresponding to the control electrode, so that the exposed portion of the control electrode with respect to the counter electrode is covered with the output electrode. Thus, the formation of parasitic capacitance between the control electrode and the counter electrode is prevented.

A flat panel display device according to a second aspect of the present invention is a bootstrap in which a capacitance is provided between a control electrode of a transistor and an input electrode or an output electrode, and the output electrode extends to the position of the control electrode. A first electrode substrate provided with a circuit, a second electrode substrate arranged to face the first electrode substrate, and a display layer held between the first electrode substrate and the second electrode substrate. It is characterized by

In the above flat panel display device, the bootstrap circuit is used for a pixel transistor.

In the above flat panel display device, the bootstrap circuit is used as an output circuit of a shift register included in a driving circuit.

In the above flat panel display device, the bootstrap circuit is used for an output circuit of a level shifter included in a drive circuit.

In the above flat panel display device, the shift register includes a first transistor having a conductive path between the first clock terminal and the output terminal, and a second transistor having a conductive path between the output terminal and the first voltage electrode. A third transistor having a conductive path between the input terminal and the control electrode of the first transistor, a conductive path between the first voltage electrode and the control electrode of the second transistor and the input terminal to the input terminal. An input circuit having a fourth transistor having a conductive path; a fifth transistor having a conductive path between the second clock terminal and the control electrode of the second transistor;
A reset circuit having a sixth transistor having a conductive path between the first voltage electrode and the control electrode of the first transistor and a conductive path to the control electrode of the second transistor; and a reset circuit to the control electrode of the first transistor. A seventh transistor having a conductive path and a conductive path to the first voltage electrode, an eighth transistor having a conductive path between the control electrodes of the seventh transistor and the second transistor, and a conductive path to the first clock terminal. And an inversion prevention circuit including.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a layout of a bootstrap circuit on a substrate according to one embodiment.
FIG. 2 is a cross-sectional view of the A′-A ′ portion of FIG. The circuit diagram of this bootstrap circuit is basically the same as that in FIG. 10, but the transistors Tr11 and Tr12 in FIG. 10 are replaced with transistors Tr1 and Tr2, respectively. For example, pMOS transistors are used for the transistors Tr1 and Tr2.

As shown in FIG. 1, a capacitor C is electrically connected between the gate electrode 51 and the source electrode 53 of the transistor Tr1. Gate electrode 5 of transistor Tr1
Reference numeral 1 corresponds to a control electrode, drain electrode 52 corresponds to an input electrode, and source electrode 53 corresponds to an output electrode. In addition, the source electrode of the transistor Tr2 is electrically connected to the gate electrode 51 of the transistor Tr1, and the gate electrode and drain electrode of the transistor Tr2 are electrically connected to the power supply voltage VSS.

As shown in FIG. 2, the channel layer 54, the gate insulating film 55, and the interlayer insulating film 56 are laminated in this order, and the gate electrode 51 is formed on a part of the contact surface between the gate insulating film 55 and the interlayer insulating film 56. Will be placed. The drain electrode 52 and the source electrode 53 are arranged so as to sandwich the gate electrode 51 from the surface of the interlayer insulating film 56 to the channel layer 54.

The feature of this embodiment is that the source electrode 53 extends to a position corresponding to the gate electrode 51 along the surface of the interlayer insulating film 56, as shown in FIGS. With this configuration, the exposed portion of the gate electrode 51 with respect to the counter electrode 14 on the counter substrate 16 is covered with the source electrode 53, so that the parasitic capacitance Ccom between the counter electrode 14 and the gate electrode 51. Are prevented from being formed.

FIG. 3 is a diagram showing operation waveforms of the bootstrap circuit. Since the formation of the parasitic capacitance Ccom is prevented in the bootstrap circuit, the output signal OU
Since the potential change of T is sufficiently transmitted to the gate of the transistor Tr1 via the capacitor C, the output signal OUT of the transistor Tr1 when the input signal IN is inverted to the low level has a short fall time and is sufficient. It becomes possible to output a low voltage.

Next, a case where the present bootstrap circuit is applied to a liquid crystal display device will be described. FIG. 4 is a circuit block diagram showing the configuration of the liquid crystal display device according to the present embodiment, and FIG. 5 is a sectional view of the present liquid crystal display device.

As shown in FIG. 4, the pixel portion 11 provided on the glass array substrate 10 has a plurality of scanning lines G.
1, G2 to Gn (hereinafter collectively referred to as G) and a plurality of signal lines S
1, S2, ..., Sm (hereinafter, collectively referred to as S) are arranged so as to intersect with each other, and the pixel transistor 12 and the pixel electrode 13 are arranged at each intersection of each scanning line G and each signal line S. For the pixel transistor 12, for example, a polysilicon thin film transistor is used. The gate of each pixel transistor 12 is connected to the scanning line G, the source is connected to the signal line S, and the drain is connected to the pixel electrode 13 and the auxiliary capacitance C.
connected to s. The scanning line drive circuit 21 and the signal line drive circuit 31 that drive the pixel transistors 12 are arranged in the pixel unit 1.
1 and 1 are integrally formed on the array substrate 10 by the same manufacturing process.

As shown in FIG. 5, a counter electrode 14 electrically opposed to the pixel electrode 13 is formed on the surface of a glass counter substrate 16 arranged so as to face the array substrate 10. A liquid crystal layer 15 is held between the array substrate 10 and the counter substrate 16, and a sealing material 17 is provided around both substrates.
It is sealed by. In this embodiment, the array substrate 10 corresponds to the first electrode substrate, the counter substrate 16 corresponds to the second electrode substrate, and the liquid crystal layer 15 corresponds to the display layer.

The scanning line drive circuit 21 includes a vertical shift register 22, a level shifter 25, and a buffer circuit (not shown).
It is a structure having. The level shifter 25 boosts the voltages of the vertical clock signal (CKV) and the vertical start signal (STV) input from the outside. The vertical shift register 22 shifts the phase of the vertical start signal synchronized with the vertical clock signal to the scanning lines G1 to Gn by one stage and outputs it as a vertical scanning pulse.

The signal line drive circuit 31 has a horizontal shift register 32, a video signal bus 33, a plurality of analog switches 34 provided for each signal line S, and a level shifter 35. The level shifter 35 boosts the voltages of the horizontal clock signal (CKH) and the horizontal start signal (STH) input from the outside. Horizontal shift register 32
Outputs a horizontal start signal synchronized with the horizontal clock signal to each analog switch 34 as a horizontal scanning pulse by shifting the phase by one stage. Analog switch 34
Is a video signal (DA that has been supplied to the video signal bus 33.
TA) is sampled according to the horizontal scanning pulse and output to the signal line S.

The three-phase shift register shown in FIG. 6 can be used for at least one of the vertical shift register 22 of the scanning line drive circuit 21 and the horizontal shift register 32 of the signal line drive circuit 31.

This three-phase shift register comprises a plurality of shift registers SR1, SR2, ...
SRn (hereinafter, generically SR), a clock line 36 for inputting any two of the three clock signals C1, C2, and C3 whose phases are shifted to each shift register SR, and an output from each shift register SR Output line 37 for outputting a signal
It is a structure having. The clock signals C1 to C3 are the vertical clock signals CKV in the vertical shift register 22.
And the horizontal clock signal CKH in the horizontal shift register 32.

Shift registers SR1, SR2, to SRn
Correspond to the first stage, the second stage, to the nth stage, respectively. Each shift register SR has a first clock terminal 41 and a second clock terminal 42. For example,
In the shift register SR1, C is used as the first clock signal.
1 is input to the first clock terminal 41, and C3 is input to the second clock terminal 42 as the second clock signal. In the shift register SR2, C3 is used as the first clock signal.
Is input to the first clock terminal 41, and C2 is input to the second clock terminal 42 as the second clock signal.

The start signal S is applied to the shift register SR1.
TP is input as the input signal IN, and the output signal from the shift register in the previous stage is input as the input signal IN in the shift registers SR in the second to nth stages. The start signal STP is the vertical start signal STV in the vertical shift register 22 and the horizontal start signal STH in the horizontal shift register 32.

Each shift register SR outputs an output signal OUT obtained by shifting the phase of the input signal IN in synchronization with two clock signals. The vertical shift register 22 outputs the output signal OUT from each shift register SR to each scanning line G as a vertical scanning pulse, and the horizontal shift register 3
2 outputs the output signal OUT from each shift register SR to each analog switch 34 as a horizontal scanning pulse.

FIG. 7 is a circuit diagram showing the structure of the shift register. This shift register has an output circuit, an input circuit,
It has a reset circuit and an inversion prevention circuit, and is formed by nine transistors. As an example, all the transistors are pMOS transistors.

The output circuit includes a first transistor T1 and a second transistor T1.
It is composed of a transistor T2. The drain of the first transistor T1 is electrically connected to the first clock terminal 41, and the source thereof is electrically connected to the output terminal 44. The first transistor T1 corresponds to the bootstrap circuit. That is, the first transistor T1 has its gate
The capacitor C is connected between the drains, and the source electrode is extended to the position of the gate electrode. The source of the second transistor T2 is electrically connected to the voltage electrode 46, and the drain thereof is electrically connected to the output terminal 44. The first clock signal C1 is input to the first clock terminal 41, and the high-level power supply voltage VDD is supplied to the voltage electrode 46.
The output circuit outputs the first clock signal C1 to the output terminal 44 when the first transistor T1 is on and the second transistor T2 is off, and when the first transistor T1 is off and the second transistor T2 is on. , And outputs the power supply voltage VDD to the output terminal 44.

The input circuit includes a third transistor T3 and a fourth transistor T3.
It is composed of a transistor T4. The drain and gate of the third transistor T3 are electrically connected to the input terminal 43, and the source thereof is electrically connected to the control electrode of the first transistor T1. The source of the fourth transistor T4 is electrically connected to the voltage electrode 46, the drain thereof is electrically connected to the control electrode of the second transistor T2, and the gate thereof is electrically connected to the input terminal 43. The input circuit inputs the input signal IN through the input terminal 43.
Receive. Here, the conductive path to the control electrode of the first transistor T1 is represented as a node n11, and the conductive path to the control electrode of the second transistor T2 is represented as a node n12.

The reset circuit is composed of a fifth transistor T5 and a sixth transistor T6. The drain and gate of the fifth transistor T5 are the second clock terminal 42.
The source is electrically connected to the control electrode of the second transistor T2. The drain of the sixth transistor T6 is electrically connected to the control electrode of the first transistor T1, the gate is electrically connected to the control electrode of the second transistor T2, and the source is electrically connected to the voltage electrode 46. The second clock signal C2 is input to the second clock terminal 42. The reset circuit turns on one of the first transistor T1 and the second transistor T2 and turns off the other.

The inversion prevention circuit is composed of a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is electrically connected to the control electrode of the first transistor T1, and the source thereof is electrically connected to the voltage electrode 46. The gate of the eighth transistor T8 is electrically connected to the first clock terminal 41, the drain thereof is electrically connected to the control electrode of the second transistor T2, and the source thereof is electrically connected to the drain of the seventh transistor T7. The inversion prevention circuit causes the control electrode of the second transistor T2 to float when the voltage of the first clock signal C1 is inverted from high level to low level when the first transistor T1 is on and the second transistor T2 is off. It is prevented that the voltage level at the control electrode of the second transistor T2 is inverted due to the state. Here, the floating state means a state in which the potential easily changes because the power supply voltage is not supplied.

The ninth transistor T9 is arranged on the node n11, the source of which is the connection point between the source of the third transistor T3 and the drain of the sixth transistor T6, the drain is the control electrode of the first transistor T1, and the gate is the gate. Each is electrically connected to the power supply voltage VSS. The ninth transistor T9 is always on. Here, the conductive path to the source of the ninth transistor T9 is referred to as the node n.
It is expressed as 13.

Next, the operation of the shift register thus configured will be described with reference to the timing chart of FIG.

Before the time t1, the potential of the input signal IN is at the high level, so that the third transistor T3 and the fourth transistor T4 are in the off state. Therefore, the second
Regardless of whether the potential of the clock signal C2 is high level or low level, the potential of the node n12 is low level and the second transistor T2 is on. Further, the sixth transistor T6 and the ninth transistor T9 are also in the ON state, and the potentials of the nodes n11 and n13 are at the high level, so the first transistor T1 is in the OFF state. In this way, when the first transistor T1 is off,
Since the second transistor T2 is on, regardless of whether the first clock signal C1 is at high level or low level,
The power supply voltage VDD is output to the output terminal 44 through the second transistor T2.

During the period from time t1 to t2, the input signal IN
Becomes a low level, and the potentials of the clock signals C1 and C2 maintain a high level. Therefore, the third transistor T3 and the fourth transistor T4 are turned on. Fourth
Since the potential of the node n12 becomes high level through the transistor T4, the second transistor T2 and the sixth transistor T6 are turned off. Since the potentials of the node n13 and the node n11 become low level through the third transistor T3, the first transistor T1 is turned on. Since the first transistor T1 is turned on and the second transistor T2 is turned off in this way, the high-level clock signal C1 is output to the output terminal 44 through the first transistor T1.

During the period from time t2 to t3, the input signal IN
Becomes high level, and the potentials of the clock signals C1 and C2 maintain high level. Therefore, the third transistor T3 and the fourth transistor T4 are turned off. As a result, the nodes n11 and n12 are brought into a floating state. The node n11 maintains a low level potential due to the parasitic capacitance between the gate and drain or between the gate and source of the first transistor T1. Similarly, the node n12 maintains a high level potential due to the parasitic capacitance of the second transistor T2. Therefore, the first
Since the transistor T1 maintains the ON state and the second transistor T2 maintains the OFF state, a high-level potential according to the first clock signal C1 is output to the output terminal 44 through the first transistor T1.

During the period from time t3 to t4, the potential of the clock signal C1 becomes low level, and the potentials of the input signal IN and the clock signal C2 maintain high level. Since the parasitic capacitance Ccom is not formed in the first transistor T1, the potential fluctuation of the first clock signal C1 is sufficiently transmitted to the node n11 in the floating state via the capacitance C, and thus the gate of the first transistor T1 is Is pulled down to a potential lower than VSS. As a result, the low-level potential of the first clock signal C1 is output to the output terminal 44 through the first transistor T1 in a sufficiently low state.

By the way, when the output signal OUT is inverted from the high level to the low level, the floating state n12 is affected by this and is inverted to the low level, and the second transistor T2 is turned on. In order to prevent this, in the inversion prevention circuit, the seventh transistor T7 is turned on when the node n11 is at high level, and the eighth transistor T7 is turned on when the first clock signal C1 is at low level.
The transistor T8 is turned on. This causes the power supply voltage VDD to pass through the transistors T7 and T8.
Are supplied to the node n12 to prevent the potential of the node n12 from being inverted.

During the period from time t4 to t5, the potential of the clock signal C1 becomes high level, and the potentials of the input signal IN and the clock signal C2 maintain high level. At this time,
The potential of the node n11 is returned to the normal low level via the capacitance C of the first transistor T1. The first transistor T1 is still on, and the output terminal 44 receives the first clock signal C1 through the first transistor T1.
The high level electric potential is output.

During the period from time t5 to t6, the potential of the clock signal C2 becomes low level, and the potentials of the input signal IN and the clock signal C2 maintain high level. At this time,
The fifth transistor T5 is turned on, and the potential of the node n12 becomes low level.

After the time t6, the node n11 maintains the high level potential and the node n12 maintains the low level potential unless the input signal IN becomes the low level. Therefore, the power supply voltage VDD is output to the output terminal 44 through the second transistor T2. With the above operation,
A series of pulse operations is completed.

Next, the case where this bootstrap circuit is applied to the output circuits of the level shifters 25 and 35 is shown in FIG.
This will be described with reference to the circuit diagram of FIG.

The level shifter shown in the figure is composed of seven transistors. All transistors have pMOS
A transistor is used.

The output circuit of the level shifter is composed of an eleventh transistor T11 and a twelfth transistor T12. The bootstrap circuit is applied to the eleventh transistor T11. That is, the capacitance C is connected between the gate and the source of the eleventh transistor T11, and the source electrode thereof extends to the position of the gate electrode. The output signal OU is output from the connection point between the source of the eleventh transistor T11 and the drain of the twelfth transistor T12.
T is output. The power supply voltage VSS is connected to the drain of the eleventh transistor T11,
The power source voltage VDD is connected to the source of 12.

The input circuit of the level shifter is composed of a fifteenth transistor T15, a sixteenth transistor T16 and a seventeenth transistor T17. The input signal IN is input to the gates of the sixteenth transistor T16 and the seventeenth transistor T17, and
An inverted input signal / IN obtained by inverting the input signal IN is input to the gate of 15. The connection point between the source of the fifteenth transistor T15 and the drain of the sixteenth transistor T16 is connected to the gate of the twelfth transistor T12. This conductive path is referred to as n21 here. The drain of the fifteenth transistor T15 is connected to the power supply voltage VSS,
The source of the 16th transistor T16 is connected to the power supply voltage VDD. The source of the seventeenth transistor T17 is the first
Connected to the gate of one transistor. This conductive path is referred to as a node n22 here. The drain of the seventeenth transistor T17 is connected to the power supply voltage VSS.

The level shifter further includes a thirteenth transistor T13 and a fourteenth transistor T14. The thirteenth transistor T13 has a drain connected to the node n22 and a gate connected to the power supply voltage VSS. The drain of the fourteenth transistor T14 is the thirteenth transistor T13.
, The gate is connected to the node n21, and the source is connected to the power supply voltage VDD.

When the input signal IN is input to the sixteenth transistor T16 and the inverted input signal / IN is input to the fifteenth transistor T15 of the level shifter having such a configuration, the node n21 is amplified by the transistors T15 and T16. An inverted signal of the input signal IN is output,
The inverted signal of the amplified input signal IN is input to the fourteenth transistor T14. Since the input signal IN is input to the seventeenth transistor T17, the input signal IN is amplified and output to the node n22. By this, the eleventh
The amplified signal of the input signal IN is input to the transistor T11, and the amplified input signal I is input to the twelfth transistor T12.
The inverted signal of N is input, and the further amplified input signal IN is output as the output signal OUT. At this time, when the potential of the output signal OUT becomes low level, the eleventh transistor T11 to which the present bootstrap circuit is applied can output the output signal OUT at a sufficiently low potential.

Therefore, according to the present embodiment, pM
Since the source electrode 53 of the OS transistor is extended to the position corresponding to the gate electrode 51, the exposed portion of the gate electrode 51 with respect to the counter electrode 14 is covered with the source electrode 53. It is possible to prevent the parasitic capacitance Ccom from being formed between the gate electrode 51 and the counter electrode 14.

As a result, the potential change of the output signal OUT changes via the capacitance C into the gate electrode 5 of the pMOS transistor.
Therefore, when the output signal OUT has a low level, the fall time is short and the output signal OUT can be output at a sufficiently low voltage.

In the present embodiment, pMOS transistors are used as the transistors forming the shift register and the level shifter.
An nMOS transistor may be used instead of the S transistor. In this case, the high level and low level of each signal are inverted and used for the pMOS transistor. With this configuration, the same effect as described above can be obtained.

In the present embodiment, the liquid crystal display device having the bootstrap circuit on the array substrate has been described as an application example of the bootstrap circuit to the flat display device. , Organic E between the first electrode substrate and the second electrode substrate which are arranged opposite to each other.
It can also be applied to a flat display device having a structure holding L. In this case, the organic EL corresponds to the display layer.

Further, it goes without saying that the circuit configurations of the shift register and the level shifter are not limited to the configurations described in the present embodiment as long as the claims are satisfied.

[0063]

As described above, according to the bootstrap circuit and the flat panel display device of the present invention, the output electrode of the transistor is extended to the position corresponding to the control electrode. On the other hand, since the exposed portion of the control electrode is covered with the output electrode, it is possible to prevent parasitic capacitance from being formed between the control electrode and the counter electrode.

[Brief description of drawings]

FIG. 1 is a plan view showing a layout of a bootstrap circuit on a substrate according to an embodiment.

FIG. 2 is a sectional view of an A′-A ′ portion of the bootstrap circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of the bootstrap circuit.

FIG. 4 is a circuit block diagram showing a configuration of a liquid crystal display device to which the bootstrap circuit is applied.

FIG. 5 is a cross-sectional view of the liquid crystal display device.

FIG. 6 is a circuit block diagram showing a configuration of a three-phase shift register used in a drive circuit of the liquid crystal display device.

FIG. 7 is a circuit diagram showing a configuration of a shift register used in the three-phase shift register.

FIG. 8 is a timing chart showing the operation of the shift register.

FIG. 9 is a circuit diagram showing a configuration of a level shifter used in a drive circuit of the liquid crystal display device.

FIG. 10 is a circuit diagram showing a schematic configuration of a conventional bootstrap circuit.

FIG. 11 is a diagram showing operation waveforms of a conventional bootstrap circuit.

FIG. 12 is a circuit diagram showing another schematic configuration of a conventional bootstrap circuit.

FIG. 13 is a plan view showing a layout of a conventional bootstrap circuit on a substrate.

FIG. 14 is a B- of the bootstrap circuit shown in FIG.
It is a sectional view of a B'portion.

FIG. 15 is a diagram showing an equivalent circuit when a conventional bootstrap circuit is applied to a flat panel display device.

FIG. 16 is a timing chart showing an operation when a conventional bootstrap circuit is applied to a flat panel display device.

[Explanation of symbols]

10 ... Array substrate 11 ... Pixel part 12 ... Pixel transistor 13 ... Pixel electrode 14 ... Counter substrate 15 ... Liquid crystal layer 16 ... Counter substrate 17 ... Sealing material 21 ... Scan line drive circuit 22 ... Vertical shift register 31 ... Signal line drive circuit 32 ... Horizontal shift register 33 ... Video signal bus 34 ... Analog switch 25, 35 ... Level shifter 41 ... First clock terminal 42 ... Second clock terminal 46 ... Voltage electrode 51 ... Gate electrode 52 ... Drain electrode 53 ... Source electrode 54 ... Channel layer 55 ... Gate insulating film 56 ... Interlayer insulating film 43, 71 ... Input terminals 44, 72 ... Output terminals C ... capacity Ccom ... parasitic capacitance Cs ... auxiliary capacity G1 to Gn ... scanning lines S1 to Sn ... Signal line Tr1, Tr2 ... Transistor Tr11, Tr12 ... Transistor T1 to T9 ... Transistor T11 to T17 ... Transistor T21 -... transistor SR1 to SRn ... Shift register VDD ... High-level power supply voltage VSS: Low level power supply voltage Vth ... threshold voltage

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 621M 5J056 622 622E 623 623H 624 624B 3/36 3/36 H03K 19/0175 H03K 19/094 C 19/094 19/00 101A F term (reference) 2H092 GA59 JA25 JA29 JA46 JB13 JB32 JB35 JB38 JB58 KA04 MA12 MA35 MA37 NA25 NA29 NA30 2H093 NA16 NC34 NC90 ND12 ND36 ND48 ND55 5C006 AF46 BC11 BC20 BC03 AF46 BC11 BC20 EB05 FA18 FA21 FA37 5C080 AA06 AA10 BB05 DD03 DD08 DD09 DD25 DD28 FF11 JJ02 JJ03 JJ04 JJ06 5C094 AA21 AA53 BA03 BA43 CA19 DA09 EA05 FA01 5J056 AA05 BB05 CC18 CC21 DD12 DD28 DD52 FF01 KK08 KK KK

Claims (6)

[Claims] 1. A bootstrap circuit in which a capacitance is provided between a control electrode of a transistor and an input electrode or an output electrode, wherein the output electrode extends to a position of the control electrode. circuit. 2. A first electrode substrate having a bootstrap circuit, wherein a capacitance is provided between a control electrode of a transistor and an input electrode or an output electrode, and the output electrode extends to a position of the control electrode. A flat display device comprising: a second electrode substrate that is arranged to face the first electrode substrate; and a display layer that is held between the first electrode substrate and the second electrode substrate. 3. The flat panel display device according to claim 2, wherein the bootstrap circuit is used for a pixel transistor. 4. The flat panel display device according to claim 2, wherein the bootstrap circuit is used in an output circuit of a shift register included in a driving circuit. 5. The flat panel display device according to claim 2, wherein the bootstrap circuit is used in an output circuit of a level shifter included in a drive circuit. 6. The shift register includes a first transistor having a conductive path between a first clock terminal and an output terminal,
An output circuit having a second transistor having a conductive path between the output terminal and a first voltage electrode, a third transistor having a conductive path between the input terminal and a control electrode of the first transistor, and the first voltage electrode An input circuit having a conductive path between the control electrode of the second transistor and a conductive path to the input terminal, and a conductive path between the second clock terminal and the control electrode of the second transistor. A sixth transistor having a fifth transistor, a conductive path between the first voltage electrode and the control electrode of the first transistor, and a conductive path to the control electrode of the second transistor.
A reset circuit having a transistor, a seventh transistor having a conductive path to the control electrode of the first transistor and a conductive path to the first voltage electrode, and a control electrode between the seventh transistor and the control electrode of the second transistor. 5. The flat panel display device according to claim 4, further comprising: an inversion prevention circuit having an eighth transistor having a conductive path and a conductive path to the first clock terminal.