JP2006191109A - ファセットチャンネルを有する半導体素子及びその製造方法 - Google Patents
ファセットチャンネルを有する半導体素子及びその製造方法 Download PDFInfo
- Publication number
- JP2006191109A JP2006191109A JP2005379754A JP2005379754A JP2006191109A JP 2006191109 A JP2006191109 A JP 2006191109A JP 2005379754 A JP2005379754 A JP 2005379754A JP 2005379754 A JP2005379754 A JP 2005379754A JP 2006191109 A JP2006191109 A JP 2006191109A
- Authority
- JP
- Japan
- Prior art keywords
- facet
- crystal orientation
- epitaxial
- semiconductor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title abstract description 23
- 239000013078 crystal Substances 0.000 claims abstract description 149
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 33
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 238000002955 isolation Methods 0.000 description 27
- 230000008569 process Effects 0.000 description 13
- 229910003465 moissanite Inorganic materials 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- 230000001747 exhibiting effect Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- -1 Si / Ge Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
【解決手段】半導体素子は第1及び第2活性領域を有する半導体基板を備える。前記第1及び第2活性領域はそれぞれ第1及び第2主表面を有し、前記第1及び第2主表面は第1結晶方位を有する。前記第2主表面から成長したファセットエピタキシャル半導体構造が提供される。前記ファセットエピタキシャル半導体構造は第2結晶方位を有する少なくとも1つのファセットを備える。前記第1主表面及び前記ファセットエピタキシャル半導体構造上にゲート誘電層が提供される。前記第1主表面上の前記ゲート誘電層上に第1ゲート電極が配置され、前記ファセットエピタキシャル半導体構造上の前記ゲート誘電層上に第2ゲート電極が配置される。また、前記半導体素子の製造方法をも提供する。
【選択図】図4
Description
[数式1]
LCcore>LCsurface
[数式2]
LCcore<LCsurface
本発明の一実施形態による製造工程を図6Aないし図6Eに図示して以下に詳しく後述する。図6Aに示したように、第1表面結晶方位1pを示すベース基板1の第1及び第2トランジスタ領域A、Bにそれぞれ第1及び第2ウェル3、5を形成する。上述したように、基板1は、例えば単結晶半導体基板を形成するのに適したSi、SiGe、またはSiCを含む多数の物質から選択することができる。その後、第1素子分離マスクパターン10a及び第2素子分離マスクパターン10bをそれぞれ第1及び第2ウェル3、5上に形成する。素子分離マスクパターン10a、10bはパッド酸化膜及びパッド窒化膜を順に形成し、前記パッド窒化膜及びパッド酸化膜を、フォトリソグラフィ工程を用いてパターニングすることで形成することができる。その結果、前記第1素子分離マスクパターン10aは順に積層されたパッド酸化膜パターン7a及びパッド窒化膜パターン9aを含むように形成することができ、前記第2素子分離マスクパターン10bは順に積層されたパッド酸化膜パターン7b及びパッド窒化膜パターン9bを含むように形成することができる。
単一活性領域61aに複数のエピタキシャルパターン701、702が形成されている本発明のまた他の実施形態による半導体素子が図7に示されている。図7に示すように、エピタキシャルパターンは一般的に平行な形態で配列されるが、このパターンは他の形態で、例えば互いに交差するように配列することもできる。多重エピタキシャルパターンは活性領域61aの効率的な表面領域を増加させる役割を果たし、これによって電流駆動力を改善する。
1p:結晶方位
3、5:第1及び第2導電型ウェル
11a:第1活性領域
17:コアエピタキシャル層、または第1エピタキシャルパターン
17t、17f1、17f2:コアエピタキシャル層の表面
19:表面エピタキシャル層、またはシェル(shell)エピタキシャル層
19t:上部ファセット
19f1、19f2:第1及び第2ファセット
20:エピタキシャルパターン
21:ゲート誘電層
23a、23b:第1及び第2ゲート電極
A、B:第1及び第2トランジスタ領域
Claims (30)
- 第1及び第2活性領域を備え、前記第1及び第2活性領域はそれぞれ第1及び第2主表面を有し、前記第1及び第2主表面は第1結晶方位を有する半導体基板と、
前記第2主表面から成長され、第2結晶方位を有する少なくとも1つのファセットを備えるファセットエピタキシャル半導体構造と、
前記第1主表面及び前記ファセットエピタキシャル半導体構造上に形成されたゲート誘電層と、
前記第1主表面上の前記ゲート誘電層上に形成された第1ゲート電極と、
前記ファセットエピタキシャル半導体構造上の前記ゲート誘電層上に形成された第2ゲート電極と、
を含むことを特徴とする半導体素子。 - 前記ファセットエピタキシャル半導体構造は、前記第2結晶方位と第2ミラー結晶方位とを有する一対の第1ファセット表面及び第3結晶方位と第3ミラー結晶方位とを有する一対の第2ファセット表面を備えることを特徴とする請求項1記載の半導体素子。
- 前記第1ファセット表面はそれぞれ等価{113}面の群から選択された相異なる結晶方位を有し、前記第2ファセット表面はそれぞれ等価{111}面の群から選択された相異なる結晶方位を有することを特徴とする請求項2記載の半導体素子。
- 前記ファセットエピタキシャル半導体構造は、前記第1結晶方位を有する上部面及び前記上部面と鈍角をなす一対のファセット表面を備えることを特徴とする請求項1記載の半導体素子。
- 前記ファセットエピタキシャル半導体構造は、コアエピタキシャルパターン及びこれを覆う表面エピタキシャルパターンを備えることを特徴とする請求項1記載の半導体素子。
- 前記コアエピタキシャルパターンは第1格子常数LCを有し、前記表面エピタキシャルパターンは第2格子常数LSを有することを特徴とする請求項6記載の半導体素子。
- 前記第1格子常数LCは前記第2格子常数LSよりも大きいことを特徴とする請求項7記載の半導体素子。
- 前記コアエピタキシャルパターン及び前記表面エピタキシャルパターンはそれぞれSi、SiC、SiGe、Ge、及びこれらの組合わせ層からなるグループから選択される2つの相異なる物質パターンであることを特徴とする請求項8記載の半導体素子。
- 前記第1格子常数LCは前記第2格子常数LSよりも小さいことを特徴とする請求項7記載の半導体素子。
- 前記コアエピタキシャルパターン及び前記表面エピタキシャルパターンは、それぞれSi、SiC、SiGe、Ge及びこれらの組合わせ層からなるグループから選択される2つの相異なる物質パターンであることを特徴とする請求項10記載の半導体素子。
- 前記第1結晶方位は(110)であり、PMOS素子が前記第1活性領域上に形成され、NMOS素子が前記第2活性領域上に形成されることを特徴とする請求項1記載の半導体素子。
- 前記少なくとも1つのファセットの表面は、{100}、{111}、及び{113}群からなるグループから選択される等価面のうちいずれか1つの結晶方位を有することを特徴とする請求項12記載の半導体素子。
- 前記少なくとも1つのファセットの表面は、(100)、(010)、(113)、及び(111)からなるグループから選択された1つの結晶方位を有することを特徴とする請求項13記載の半導体素子。
- 前記第1結晶方位は(100)であり、NMOS素子が前記第1活性領域上に形成され、PMOS素子が前記第2活性領域上に形成されることを特徴とする請求項1記載の半導体素子。
- 前記少なくとも1つのファセットの表面は(110)結晶方位を有することを特徴とする請求項15記載の半導体素子。
- 前記ファセットエピタキシャル半導体構造は前記第2主表面上に形成され互いに分離された第1及び第2ファセットエピタキシャル半導体構造を含み、
前記第1及び第2ファセットエピタキシャル半導体構造のそれぞれは第2結晶方位を有する少なくとも1つのファセット表面を備え、前記ゲート誘電層は前記第1及び第2ファセットエピタキシャル半導体構造の前記ファセット表面を覆うことを特徴とする請求項1記載の半導体素子。 - 半導体基板に第1主表面を有する第1活性領域及び第2主表面を有する第2活性領域を形成し、前記第1及び第2主表面は第1結晶方位を有することと、
前記第2主表面上に第2結晶方位を有する少なくとも1つのファセット表面を備えるファセットエピタキシャル半導体構造を形成することと、
前記第1主表面及び前記少なくとも1つのファセット表面上にゲート誘電層を形成することと、
前記ゲート誘電層上にゲート電極を形成することと、
を含むことを特徴とする半導体素子の形成方法。 - 前記ファセットエピタキシャル半導体構造を形成することは、
一対の第1ファセット表面を形成し、前記第1ファセット表面のうち1つは前記第2結晶方位を有するように形成されて他の1つは前記第2結晶方位と係わる第2ミラー結晶方位を有するように形成され、
前記第1ファセット表面から延長された一対の第2ファセット表面を形成することを含み、前記第2ファセット表面のうち1つは第3結晶方位を有するように形成されて他の1つは前記第3結晶方位と係わる第3ミラー結晶方位を有するように形成されることを特徴とする請求項18記載の半導体素子の形成方法。 - 前記ファセットエピタキシャル半導体構造を形成することは、
前記第2結晶方位を有する一対の第1ファセット表面を形成し、
前記第1ファセット表面間の上部面を形成することを含み、前記上部面は前記第1結晶方位を有するように形成されて前記第1ファセット表面は前記上部面と鈍角をなすように形成されることを特徴とする請求項18記載の半導体素子の形成方法。 - 前記ファセットエピタキシャル半導体構造を形成することは、
コアエピタキシャルパターンを形成することと、
前記コアエピタキシャルパターン上に表面エピタキシャルパターンを形成することと、
を含むことを特徴とする請求項18記載の半導体素子の形成方法。 - 前記コアエピタキシャルパターンは第1格子常数LCを有する物質で形成し、前記表面エピタキシャルパターンは前記第1格子常数LCよりも小さい第2格子常数LSを有する物質で形成されることを特徴とする請求項21記載の半導体素子の形成方法。
- 前記コアエピタキシャルパターン及び前記表面エピタキシャルパターンは、Si、SiC、SiGe、Ge、及びこれらの組合わせ層からなるグループから選択された2つの相異なる物質膜で形成されたことを特徴とする請求項22記載の半導体素子の形成方法。
- 前記コアエピタキシャルパターンは第1格子常数LCを有する物質で形成され、前記表面エピタキシャルパターンは前記第1格子常数LCよりも大きい第2格子常数LSを有する物質で形成されたことを特徴とする請求項21記載の半導体素子の形成方法。
- 前記コアエピタキシャルパターン及び前記表面エピタキシャルパターンは、Si、SiC、SiGe、Ge、及びこれらの組合わせ層からなるグループから選択された2つの相異なる物質膜で形成されたことを特徴とする請求項24記載の半導体素子の形成方法。
- 前記第1結晶方位は(110)であり、PMOS素子が前記第1活性領域上に形成され、NMOS素子が前記第2活性領域上に形成されることを特徴とする請求項18記載の半導体素子の形成方法。
- 前記少なくとも1つのファセット表面は、{100}、{111}及び{113}群からなるグループからの等価面のうちいずれか1つの結晶方位を有することを特徴とする請求項26記載の半導体素子の形成方法。
- 前記第1結晶方位は(100)であり、NMOS素子が前記第1活性領域上に形成され、PMOS素子が前記第2活性領域上に形成されることを特徴とする請求項18記載の半導体素子の形成方法。
- 前記少なくとも1つのファセット表面は、{110}、{111}、及び{113}群からなるグループからの等価面のうちいずれか1つの結晶方位を有することを特徴とする請求項28記載の半導体素子の形成方法。
- 前記ファセットエピタキシャル半導体構造は前記第2主表面上に互いに分離された第1及び第2ファセットエピタキシャル半導体構造を含むように形成することを特徴とし、
前記第1及び第2ファセットエピタキシャル半導体構造のそれぞれは第2結晶方位を有する少なくとも1つのファセット表面を備えて、前記ゲート誘電層は前記第1及び第2ファセットエピタキシャル半導体構造の前記ファセット表面を覆うことを特徴とする請求項18記載の半導体素子の形成方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050000584A KR100849177B1 (ko) | 2005-01-04 | 2005-01-04 | 패싯 채널들을 갖는 모스 트랜지스터를 채택하는 반도체집적회로 소자들 및 그 제조방법들 |
KR10-2005-0000584 | 2005-01-04 | ||
US11/281,599 | 2005-11-18 | ||
US11/281,599 US7671420B2 (en) | 2005-01-04 | 2005-11-18 | Semiconductor devices having faceted channels and methods of fabricating such devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006191109A true JP2006191109A (ja) | 2006-07-20 |
JP5085039B2 JP5085039B2 (ja) | 2012-11-28 |
Family
ID=36190410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005379754A Active JP5085039B2 (ja) | 2005-01-04 | 2005-12-28 | ファセットチャンネルを有する半導体素子及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1677350B1 (ja) |
JP (1) | JP5085039B2 (ja) |
TW (1) | TWI263328B (ja) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329474A (ja) * | 2006-06-06 | 2007-12-20 | Internatl Business Mach Corp <Ibm> | ハイブリッド・チャネル配向を有するcmosデバイスおよびファセット形成エピタキシを用いてハイブリッド・チャネル配向を有するcmosデバイを作製するための方法 |
JP2008218797A (ja) * | 2007-03-06 | 2008-09-18 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2009182264A (ja) * | 2008-01-31 | 2009-08-13 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2009182057A (ja) * | 2008-01-29 | 2009-08-13 | Toshiba Corp | 半導体装置とその製造方法 |
JP2009272527A (ja) * | 2008-05-09 | 2009-11-19 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2010206097A (ja) * | 2009-03-05 | 2010-09-16 | Toshiba Corp | 半導体素子及び半導体装置 |
US7842982B2 (en) | 2008-01-29 | 2010-11-30 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP2014199853A (ja) * | 2013-03-29 | 2014-10-23 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
WO2015104947A1 (ja) * | 2014-01-08 | 2015-07-16 | ソニー株式会社 | 半導体装置、メモリ回路、および半導体装置の製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7566949B2 (en) * | 2006-04-28 | 2009-07-28 | International Business Machines Corporation | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching |
US7393738B1 (en) * | 2007-01-16 | 2008-07-01 | International Business Machines Corporation | Subground rule STI fill for hot structure |
US8841701B2 (en) * | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
JP5612035B2 (ja) * | 2012-07-31 | 2014-10-22 | 株式会社東芝 | 半導体装置 |
US10734488B2 (en) | 2015-09-11 | 2020-08-04 | Intel Corporation | Aluminum indium phosphide subfin germanium channel transistors |
EP3472867A4 (en) * | 2016-06-17 | 2020-12-02 | INTEL Corporation | SELF-ALIGNED GATE ELECTRODE FIELD-EFFECT TRANSISTORS ON A SEMICONDUCTOR FIN |
JP6889048B2 (ja) * | 2017-06-30 | 2021-06-18 | 株式会社日立製作所 | 炭化ケイ素半導体装置およびその製造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220364A (ja) * | 1985-07-19 | 1987-01-28 | Hitachi Ltd | 半導体装置 |
JPH04368180A (ja) * | 1991-05-31 | 1992-12-21 | Samsung Electron Co Ltd | 絶縁ゲート形電界効果トランジスタの構造およびその製造方法 |
JPH0555493A (ja) * | 1991-08-26 | 1993-03-05 | Toshiba Corp | 半導体集積回路装置 |
JP2002118255A (ja) * | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2004235345A (ja) * | 2003-01-29 | 2004-08-19 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004319704A (ja) * | 2003-04-15 | 2004-11-11 | Seiko Instruments Inc | 半導体装置 |
JP2005056870A (ja) * | 2003-06-12 | 2005-03-03 | Toyota Industries Corp | ダイレクトコンバージョン受信の周波数変換回路、その半導体集積回路及びダイレクトコンバージョン受信機 |
WO2005038931A1 (ja) * | 2003-10-20 | 2005-04-28 | Nec Corporation | 半導体装置及び半導体装置の製造方法 |
JP2006024718A (ja) * | 2004-07-07 | 2006-01-26 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997016854A1 (de) * | 1995-11-01 | 1997-05-09 | Amo Gmbh | Halbleiter-bauelement mit prismenförmigem kanalbereich |
DE10131237B8 (de) * | 2001-06-28 | 2006-08-10 | Infineon Technologies Ag | Feldeffekttransistor und Verfahren zu seiner Herstellung |
JP3782021B2 (ja) * | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
US6864520B2 (en) * | 2002-04-04 | 2005-03-08 | International Business Machines Corporation | Germanium field effect transistor and method of fabricating the same |
US6645797B1 (en) * | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
EP1555688B1 (en) * | 2004-01-17 | 2009-11-11 | Samsung Electronics Co., Ltd. | Method of manufacturing a multi-sided-channel finfet transistor |
-
2005
- 2005-12-22 TW TW94145762A patent/TWI263328B/zh active
- 2005-12-28 JP JP2005379754A patent/JP5085039B2/ja active Active
- 2005-12-29 EP EP20050028620 patent/EP1677350B1/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220364A (ja) * | 1985-07-19 | 1987-01-28 | Hitachi Ltd | 半導体装置 |
JPH04368180A (ja) * | 1991-05-31 | 1992-12-21 | Samsung Electron Co Ltd | 絶縁ゲート形電界効果トランジスタの構造およびその製造方法 |
JPH0555493A (ja) * | 1991-08-26 | 1993-03-05 | Toshiba Corp | 半導体集積回路装置 |
JP2002118255A (ja) * | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2004235345A (ja) * | 2003-01-29 | 2004-08-19 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004319704A (ja) * | 2003-04-15 | 2004-11-11 | Seiko Instruments Inc | 半導体装置 |
JP2005056870A (ja) * | 2003-06-12 | 2005-03-03 | Toyota Industries Corp | ダイレクトコンバージョン受信の周波数変換回路、その半導体集積回路及びダイレクトコンバージョン受信機 |
WO2005038931A1 (ja) * | 2003-10-20 | 2005-04-28 | Nec Corporation | 半導体装置及び半導体装置の製造方法 |
JP2006024718A (ja) * | 2004-07-07 | 2006-01-26 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329474A (ja) * | 2006-06-06 | 2007-12-20 | Internatl Business Mach Corp <Ibm> | ハイブリッド・チャネル配向を有するcmosデバイスおよびファセット形成エピタキシを用いてハイブリッド・チャネル配向を有するcmosデバイを作製するための方法 |
JP2008218797A (ja) * | 2007-03-06 | 2008-09-18 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
US7842982B2 (en) | 2008-01-29 | 2010-11-30 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP2009182057A (ja) * | 2008-01-29 | 2009-08-13 | Toshiba Corp | 半導体装置とその製造方法 |
JP4543093B2 (ja) * | 2008-01-29 | 2010-09-15 | 株式会社東芝 | 半導体装置 |
JP2009182264A (ja) * | 2008-01-31 | 2009-08-13 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2009272527A (ja) * | 2008-05-09 | 2009-11-19 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2010206097A (ja) * | 2009-03-05 | 2010-09-16 | Toshiba Corp | 半導体素子及び半導体装置 |
US8013396B2 (en) | 2009-03-05 | 2011-09-06 | Kabushiki Kaisha Toshiba | Semiconductor component and semiconductor device |
JP2014199853A (ja) * | 2013-03-29 | 2014-10-23 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
WO2015104947A1 (ja) * | 2014-01-08 | 2015-07-16 | ソニー株式会社 | 半導体装置、メモリ回路、および半導体装置の製造方法 |
JPWO2015104947A1 (ja) * | 2014-01-08 | 2017-03-23 | ソニー株式会社 | 半導体装置、メモリ回路、および半導体装置の製造方法 |
US10269867B2 (en) | 2014-01-08 | 2019-04-23 | Sony Corporation | Semiconductor device, memory circuit, method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW200625603A (en) | 2006-07-16 |
TWI263328B (en) | 2006-10-01 |
EP1677350B1 (en) | 2011-02-02 |
JP5085039B2 (ja) | 2012-11-28 |
EP1677350A3 (en) | 2007-05-30 |
EP1677350A2 (en) | 2006-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5085039B2 (ja) | ファセットチャンネルを有する半導体素子及びその製造方法 | |
US7671420B2 (en) | Semiconductor devices having faceted channels and methods of fabricating such devices | |
US10418488B2 (en) | Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate | |
JP4493343B2 (ja) | 歪みフィンfet構造および方法 | |
US7208815B2 (en) | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof | |
KR101718191B1 (ko) | 핀형 전계효과 트랜지스터 구조체와 그 형성방법 | |
US7547641B2 (en) | Super hybrid SOI CMOS devices | |
KR100674914B1 (ko) | 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법 | |
TWI360197B (en) | Method of fabricating an integrated circuit channe | |
CN109216460B (zh) | 具有鳍结构的半导体器件 | |
US20070221956A1 (en) | Semiconductor device and method of fabricating the same | |
JP2005159362A (ja) | ゲルマニウムチャンネル領域を有する非平面トランジスタ及びその製造方法 | |
JPWO2006006438A1 (ja) | 半導体装置及びその製造方法 | |
US9620507B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region | |
JP2008514016A (ja) | 高移動性バルク・シリコンpfet | |
JP2010073869A (ja) | 半導体装置およびその製造方法 | |
US7453122B2 (en) | SOI MOSFET device with reduced polysilicon loading on active area | |
KR100612420B1 (ko) | 반도체 소자 및 그 제조 방법 | |
JP2006507684A (ja) | 2トランジスタnorデバイス | |
JP2022523346A (ja) | フィン形ブリッジ領域によって結合された垂直に積み重ねられたナノシートを有するトランジスタ・チャネル | |
US8017472B2 (en) | CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof | |
US11581226B2 (en) | Semiconductor device with tunable epitaxy structures and method of forming the same | |
KR100741468B1 (ko) | 반도체 장치 및 그 형성 방법 | |
CN113611743B (zh) | 半导体晶体管结构及其制作方法 | |
US7696575B2 (en) | Semiconductor device and method of manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081204 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120410 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120619 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120807 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120905 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5085039 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150914 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |