JP2006120870A - 配線形成方法及び装置 - Google Patents

配線形成方法及び装置 Download PDF

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Publication number
JP2006120870A
JP2006120870A JP2004307354A JP2004307354A JP2006120870A JP 2006120870 A JP2006120870 A JP 2006120870A JP 2004307354 A JP2004307354 A JP 2004307354A JP 2004307354 A JP2004307354 A JP 2004307354A JP 2006120870 A JP2006120870 A JP 2006120870A
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JP
Japan
Prior art keywords
wiring
film
conductive film
forming
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004307354A
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English (en)
Japanese (ja)
Other versions
JP2006120870A5 (enExample
Inventor
Akira Fukunaga
明 福永
Manabu Tsujimura
学 辻村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP2004307354A priority Critical patent/JP2006120870A/ja
Priority to US11/254,789 priority patent/US20060086618A1/en
Publication of JP2006120870A publication Critical patent/JP2006120870A/ja
Publication of JP2006120870A5 publication Critical patent/JP2006120870A5/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
JP2004307354A 2004-10-21 2004-10-21 配線形成方法及び装置 Pending JP2006120870A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004307354A JP2006120870A (ja) 2004-10-21 2004-10-21 配線形成方法及び装置
US11/254,789 US20060086618A1 (en) 2004-10-21 2005-10-21 Method and apparatus for forming interconnects

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004307354A JP2006120870A (ja) 2004-10-21 2004-10-21 配線形成方法及び装置

Publications (2)

Publication Number Publication Date
JP2006120870A true JP2006120870A (ja) 2006-05-11
JP2006120870A5 JP2006120870A5 (enExample) 2007-07-19

Family

ID=36205204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004307354A Pending JP2006120870A (ja) 2004-10-21 2004-10-21 配線形成方法及び装置

Country Status (2)

Country Link
US (1) US20060086618A1 (enExample)
JP (1) JP2006120870A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064803A (ja) * 2007-09-04 2009-03-26 Renesas Technology Corp 半導体装置
JP2010512002A (ja) * 2006-11-30 2010-04-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 銀を含む配線を有する半導体構造及びその形成方法
JP2011523780A (ja) * 2008-05-21 2011-08-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 導電性コンタクトの組み込みのための構造体及びプロセス
US8198730B2 (en) 2007-01-10 2012-06-12 Nec Corporation Semiconductor device and method of manufacturing the same
KR101458038B1 (ko) * 2006-11-30 2014-11-03 글로벌파운드리즈 인크. 은을 포함한 배선을 구비한 반도체 구조체와 그 형성 방법

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1894900A3 (en) * 2006-08-28 2010-02-24 Osaka University Catalyst-aided chemical processing method and apparatus
JP2008141088A (ja) * 2006-12-05 2008-06-19 Nec Electronics Corp 半導体装置の製造方法
US20130052368A1 (en) * 2010-03-19 2013-02-28 Sigma-Aldrich Co. Llc Methods for preparing thin films by atomic layer deposition using hydrazines
TW202138115A (zh) * 2019-12-24 2021-10-16 日商荏原製作所股份有限公司 基板處理裝置、基板處理方法及基板處理系統

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4067307B2 (ja) * 2000-04-27 2008-03-26 株式会社荏原製作所 回転保持装置
JP4644926B2 (ja) * 2000-10-13 2011-03-09 ソニー株式会社 半導体製造装置および半導体装置の製造方法
JP3664669B2 (ja) * 2001-06-27 2005-06-29 株式会社荏原製作所 電解めっき装置
AU2003217197A1 (en) * 2002-01-10 2003-07-30 Semitool, Inc. Method for applying metal features onto barrier layers using electrochemical deposition
US7223685B2 (en) * 2003-06-23 2007-05-29 Intel Corporation Damascene fabrication with electrochemical layer removal

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010512002A (ja) * 2006-11-30 2010-04-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 銀を含む配線を有する半導体構造及びその形成方法
KR101458038B1 (ko) * 2006-11-30 2014-11-03 글로벌파운드리즈 인크. 은을 포함한 배선을 구비한 반도체 구조체와 그 형성 방법
US8198730B2 (en) 2007-01-10 2012-06-12 Nec Corporation Semiconductor device and method of manufacturing the same
JP2009064803A (ja) * 2007-09-04 2009-03-26 Renesas Technology Corp 半導体装置
JP2011523780A (ja) * 2008-05-21 2011-08-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 導電性コンタクトの組み込みのための構造体及びプロセス

Also Published As

Publication number Publication date
US20060086618A1 (en) 2006-04-27

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