JP2006073702A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006073702A JP2006073702A JP2004253998A JP2004253998A JP2006073702A JP 2006073702 A JP2006073702 A JP 2006073702A JP 2004253998 A JP2004253998 A JP 2004253998A JP 2004253998 A JP2004253998 A JP 2004253998A JP 2006073702 A JP2006073702 A JP 2006073702A
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- circuit elements
- insulator layer
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Abstract
【解決手段】 半導体装置100は、基材20、半導体チップ10a、10b、チップ部品12a、12b、絶縁基材30、配線パターン34、ビアプラグ32、外部引出電極36、凹部40、樹脂50を含む。絶縁基材30は、多層構造を有しており、複数の絶縁体膜を積層して形成される。半導体チップ10aおよびチップ部品12aは、基材20にマウントされ絶縁基材30に埋め込まれている。半導体装置100の表面には凹部40が形成され、その深さはいずれかの配線導体層までとなっており、凹部40には、半導体チップ10b、チップ部品12bが実装される。
【選択図】 図1
Description
これらの態様の半導体装置の製造方法によれば、複数の回路素子の間隙部に好適に配線パターンを形成することができる。
図1は、本発明の第1の実施の形態に係る半導体装置100の断面図である。以降の図において、同一の構成要素には同一の符号を付し、適宜説明を省略する。
半導体装置100は、基材20、半導体チップ10a、10b、チップ部品12a、12b、絶縁基材30、配線パターン34、ビアプラグ32、外部引出電極36、凹部40、樹脂50を含む。図1において、便宜上、基材20の設けられた面を下方向とし、凹部40が設けられた面を上方向とする。
この凹部40に実装された半導体チップ10bは、樹脂50による封止工程前であれば内部に形成される抵抗、コンデンサのトリミングを行うことができる。従って、半導体装置100の組み立て後においても、回路特性の調整を行うことができ、歩留まりの向上を図ることができる。
さらに、絶縁基材30内の配線導体層に形成された配線パターン34が凹部40から露出している場合には、この配線パターンをトリミングすることによっても回路定数を変更することができる。
その結果、半導体チップ10aおよびチップ部品12aは絶縁性樹脂膜122内に押しまれる。導電性膜120は、配線導体層となり、後の工程により配線パターンが形成される。
逆に、基材20を収縮させた状態で半導体チップ10aおよびチップ部品12aを絶縁性樹脂膜122内に押し込む場合には、素子間の間隔が狭くなるため、高密度な素子配置が可能となる。
以上の工程を経て、第1の実施の形態に係る半導体装置100を製造することができる。
第2の実施の形態に係る半導体装置200について、上述の半導体装置100との相違点を中心に説明する。図3は、第2の実施の形態に係る半導体装置200の断面図である。
半導体装置200は、基材20、半導体チップ10a、チップ部品12a、絶縁基材30、配線パターン34、ビアプラグ32、外部引出電極36を含む。図3においても、便宜上、基材20を下方向とし、外部引出電極36が設けられた面を上方向とする。
通常の半導体チップ10aの厚みは100〜300μmであり、抵抗やコンデンサ等のチップ部品12aの高さはいわゆる0603サイズで300μm、1005サイズで500μm程度である。本実施の形態では、半導体チップ10a等が実装されていない間隙部にも、配線導体層を形成して、より高密度な配線を行っている。
絶縁性樹脂膜122の開口部150は、配線パターン34cを形成する箇所に設けられる。
まず、図6(a)に示すように、基材20に半導体チップ10aおよびチップ部品12aをダイ、チップボンディングする。次いで、図6(b)に示すように、配線パターン34cを形成したい箇所に局所的に樹脂ポッティングを行い、絶縁体層130aを形成する。続いて図6(c)〜(e)に示すように配線パターン34c、絶縁体層130bの形成し、ビアプラグ32を形成する。
Claims (9)
- 絶縁体層と配線導体層が積層された積層基板と、
前記積層基板の一方の面側の絶縁体層に形成された凹部と、
前記凹部が形成された絶縁体層とは異なる絶縁体層に埋め込まれた回路素子と、
を備え、前記凹部の底部は、配線導体層に到達していることを特徴とする半導体装置。 - 前記絶縁体層は、有機物を主成分として構成されることを特徴とする請求項1に記載の半導体装置。
- 前記凹部は、いずれかの配線導体層の配線パターンが外部からトリミングできるように該配線導体層の深さに形成されたこと特徴とする請求項1に記載の半導体装置。
- 絶縁体層と配線導体層が繰り返し積層された積層基板と、
前記積層基板の一方の面側の絶縁体層に形成された複数の凹部と、
前記凹部が形成された絶縁体層とは異なる絶縁体層に埋め込まれた回路素子と、
を備え、前記複数の凹部の底部は、それぞれいずれかの配線導体層に到達していることを特徴とする半導体装置。 - 複数の絶縁体層と配線導体層からなる積層基板と、
前記絶縁体層に埋め込まれた複数の回路素子と、
を備え、前記複数の回路素子が埋め込まれた絶縁体層は、その内部に配線導体層を備え、前記複数の回路素子の間隙部を利用して配線パターンが形成されることを特徴とする半導体装置。 - 基材と、
前記基材上に積層された、複数の絶縁体層と配線導体層からなる積層基板と、
前記積層基板の前記基材と隣接する絶縁体層に埋め込まれた複数の回路素子と、
を備え、前記複数の回路素子が埋め込まれた絶縁体層は、その内部に配線導体層を備え、前記複数の回路素子の間隙部を利用して配線パターンが形成されることを特徴とする半導体装置。 - 基材に複数の回路素子をマウントする工程と、
前記複数の回路素子の間隙部に、該回路素子よりも厚みの小さい絶縁体層を形成する工程と、
前記絶縁体層上に配線パターンを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 基材に複数の回路素子をマウントする工程と、
前記複数の回路素子の間隙部に対応する箇所に予め開口部が形成された第1の絶縁膜を前記基材に圧着する工程と、
前記開口部に、前記第1の絶縁膜より薄い第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上に配線パターンを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 基材に複数の回路素子をマウントする工程と、
第1の絶縁膜を前記複数の回路素子の上から前記基材に圧着する工程と、
前記第1の絶縁膜の回路素子の間隙部に開口部を形成する工程と、
前記開口部に、前記第1の絶縁膜より薄い第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上に配線パターンを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
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JP2004253998A JP4252019B2 (ja) | 2004-09-01 | 2004-09-01 | 回路装置およびその製造方法 |
US11/215,121 US7875980B2 (en) | 2004-09-01 | 2005-08-31 | Semiconductor device having laminated structure |
CN2005100980208A CN1744314B (zh) | 2004-09-01 | 2005-09-01 | 具有层积结构的半导体装置及其制造方法 |
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JP2008300560A (ja) * | 2007-05-30 | 2008-12-11 | Sony Corp | 半導体装置及びその製造方法 |
JP2009076833A (ja) * | 2007-09-18 | 2009-04-09 | Samsung Electro-Mechanics Co Ltd | 電子素子内蔵印刷回路基板及びその製造方法 |
WO2014091644A1 (ja) * | 2012-12-12 | 2014-06-19 | 日本特殊陶業株式会社 | 多層配線基板およびその製造方法 |
WO2018079278A1 (ja) * | 2016-10-25 | 2018-05-03 | 株式会社村田製作所 | 回路モジュール |
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US20110156261A1 (en) * | 2009-03-24 | 2011-06-30 | Christopher James Kapusta | Integrated circuit package and method of making same |
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CN105848416B (zh) * | 2016-03-31 | 2019-04-26 | 华为技术有限公司 | 一种基板及移动终端 |
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JP2008300560A (ja) * | 2007-05-30 | 2008-12-11 | Sony Corp | 半導体装置及びその製造方法 |
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JP2014116548A (ja) * | 2012-12-12 | 2014-06-26 | Ngk Spark Plug Co Ltd | 多層配線基板およびその製造方法 |
CN104854969A (zh) * | 2012-12-12 | 2015-08-19 | 日本特殊陶业株式会社 | 多层布线基板以及其制造方法 |
WO2018079278A1 (ja) * | 2016-10-25 | 2018-05-03 | 株式会社村田製作所 | 回路モジュール |
US10861759B2 (en) | 2016-10-25 | 2020-12-08 | Murata Manufacturing Co., Ltd. | Circuit module |
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JP4252019B2 (ja) | 2009-04-08 |
US20060043606A1 (en) | 2006-03-02 |
CN1744314A (zh) | 2006-03-08 |
US7875980B2 (en) | 2011-01-25 |
CN1744314B (zh) | 2011-05-04 |
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